KR100576486B1 - Non-volatile memory device using phase change resistor cell - Google Patents

Abstract

The present invention relates to a nonvolatile memory device using a phase change resistance cell, and discloses a technique for reducing the size of an entire memory by efficiently arranging a cross point cell array including a resistance memory element and a series PN diode chain. . The present invention relates to a phase change resistor cell array including a nonvolatile resistor memory device whose resistance state changes according to a current value and a series diode switch that does not require a separate gate control signal. And the upper portion of the circuit element region including the data buffer and the input / output port, and the like, and the overall chip size can be reduced by separating the cell array region and the circuit element region based on the interlayer insulating film.

Description

Non-volatile memory device using phase change resistor cell

1A to 1D are diagrams for explaining a conventional phase change resistance element.

2 is a block diagram of a phase change resistance cell according to the present invention;

3 is a cross-sectional view of the phase change resistance cell of FIG. 2.

4 is a plan view of the series diode switch of FIG.

5 is a plan view of the phase change resistance cell of FIG.

6 is a view for explaining the operation of the series diode switch of FIG.

7 is a configuration diagram of a nonvolatile memory device using a phase change resistance cell according to the present invention.

FIG. 8 is a layout diagram of the phase change resistance cell array of FIG. 7. FIG.

FIG. 9 is a detailed circuit diagram of the phase change resistance cell array of FIG. 7. FIG.

10 is a timing diagram of operation in a read mode of a nonvolatile memory device using a phase change resistance cell according to the present invention;

11 is a timing diagram of an operation in the write mode of a nonvolatile memory device using a phase change resistance cell according to the present invention;

12 is a view for explaining a temperature characteristic of a phase change resistance cell in the write mode of the nonvolatile memory device using the phase change resistance cell according to the present invention;

13 is a plan view of a nonvolatile memory device using a phase change resistance cell according to the present invention;

14 is another embodiment of a nonvolatile memory device using a phase change resistance cell according to the present invention;

15 is a cross-sectional configuration diagram of a nonvolatile memory device using a phase change resistance cell according to the present invention.

16 is a plan view of a pad array according to a first embodiment of the present invention.

17 is a cross-sectional configuration according to the embodiment of FIG.

18 is a plan view showing a pad array according to a second embodiment of the present invention.

19 is a cross-sectional view of the embodiment of FIG. 18.

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a nonvolatile memory device using a phase change resistance cell. The present invention relates to a technique for efficiently reducing the size of an entire memory by arranging a cross point cell array including a resistance memory device and a series diode switch.

In general, nonvolatile memories such as magnetic memory and phase change memory (PCM) have data processing speeds of about volatile random access memory (RAM) and preserve data even when the power is turned off. Has the property of being.

1A to 1D are diagrams for explaining a conventional phase change resistor (PCR) element 4.

When the phase change resistance element 4 applies a voltage and a current by inserting a phase change material (PCM) 2 between the top electrode 1 and the bottom electrode 3, a phase is applied. The high temperature is induced in the change layer 2 to change the state of electrical conduction according to the change in resistance. Here, AglnSbTe is mainly used as the material of the phase change layer 2.

That is, as shown in FIG. 1C, when a low current of less than or equal to a threshold flows through the phase change resistance element 4, the phase change layer 2 is at a temperature suitable for crystallization. As a result, the phase change layer 2 is in a crystalline phase to become a material having a low resistance state.

On the other hand, as shown in FIG. 1D, when a high current of more than a threshold flows through the phase change resistance element 4, the temperature of the phase change layer 2 becomes higher than the melting point. As a result, the phase change layer 2 is in an amorphous state and becomes a material of a high resistance state.

As described above, the phase change resistive element 4 can non-volatilely store data corresponding to the states of the two resistors. That is, if the phase change resistance element 4 is in the low resistance state, the data is "1", and in the high resistance state is the data "0", the logic state of the two data can be stored.

Meanwhile, a conventional memory device includes one switching element and one memory element for storing data. Here, the switching element of the conventional memory device mainly uses an NMOS transistor whose switching operation is controlled by a gate control signal.

However, when the cell array is implemented using the NMOS transistor as a switching device, there is a problem in that the overall chip size is increased.

Accordingly, as described above, a cross point cell is implemented by using a phase change resistance element having a nonvolatile characteristic and a series diode switch that does not need a separate gate control signal, and a cross point cell and a circuit element region for controlling the same are provided. There is a need for the present invention to efficiently reduce the overall chip size.

The present invention has been made to solve the above problems and has the following object.

First, the object of the present invention is to reduce the overall size of the nonvolatile memory by disposing a phase change resistance cell array on the upper side of the interlayer insulating layer and a circuit element region on the lower side.

Second, an object of the present invention is to efficiently reduce a cell size of a nonvolatile memory by efficiently disposing a pad array on top of the above-described phase change resistance cell array.

A nonvolatile memory device using a phase change resistance cell of the present invention for achieving the above object comprises: a plurality of phase change resistance cell arrays including a plurality of unit phase change resistance cells arranged in a row and column direction; A circuit element region formed on a silicon substrate provided under the plurality of phase change resistor cell arrays to drive and amplify the plurality of phase change resistor cell arrays; And an insulating layer formed between the plurality of phase change resistor cell arrays and the circuit element regions to insulate the plurality of phase change resistor cell arrays and the circuit element regions from each other. A phase change resistance element which senses a crystallization state that changes according to size and stores data corresponding to a change in resistance; And a series diode switch having at least two diode switches continuously connected in series and having a common connection node connected to one end of a phase change resistance element, wherein the series diode switches are selectively switched according to the magnitude of the voltage applied to the word line and the bit line. It is characterized by.
Hereinafter, with reference to the accompanying drawings will be described in detail an embodiment of the present invention.

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2 is a configuration diagram of a phase change resistance cell of a nonvolatile memory device using a phase change resistance cell according to the present invention.

The unit phase change resistor (PCR) cell includes one phase change resistor element PCR and one series diode switch 10. Here, the series diode switch 10 includes a PNPN diode switch 11 and a PN diode switch 12. The PNPN diode switch 11 and the PN diode switch 12 are connected in parallel between the bottom electrode of the phase change resistance element PCR and the bit line BL.

The PNPN diode switch 11 is connected in the reverse direction between one electrode of the phase change resistance element PCR and the bit line BL, and the PN diode switch 12 is connected in the forward direction between one electrode of the phase change resistance element PCR and the bit line BL. do. The other electrode of the phase change resistance element PCR is connected to the word line WL.

3 is a cross-sectional configuration diagram of the phase change resistance cell of FIG. 2.

The series diode switch 10 includes an insulating layer 31 formed on the silicon substrate 30 and a silicon layer 32 on the insulating layer 31 to form a silicon on insulator (SOI) structure. Here, an insulating layer 31 made of SiO 2 is stacked on the silicon substrate 30, and a silicon layer 32 is formed on the insulating layer 31. The silicon layer 32 is formed by stacking a PNPN diode switch 11 and a PN diode switch 12 made of growth silicon or polysilicon and connected in series.

The PNPN diode switch 11 alternately connects the P-type region and the N-type region in series, and the PN diode switch 12 has the P-type region and the N-type region in series in the N-type region adjacent to the PNPN diode switch 11. It has a connected structure.

The bit line BL is formed on the N-type region of the PN diode switch 12 and the P-type region of the PNPN diode switch 11 through the bitline contact node BLCN. In addition, the P-type region of the PN diode switch 12 and the N-type region of the PNPN diode switch 11 are connected to the bottom electrode 22 of the phase change resistance element PCR through the common contact node CN.

Here, the phase change resistance element PCR includes a top electrode 20, a phase change layer (PCM) 21, and a bottom electrode 22. The top electrode 20 of the phase change resistance element PCR is connected to the word line WL.

4 is a plan view of the series diode switch 10 of FIG. 3.

In the series diode switch 10, the PNPN diode switch 11 and the PN diode switch 12 made of the silicon layer 32 are continuously connected in series chain form. That is, one phase change resistance cell has a PN diode switch 12 and a PNPN diode switch 11 connected in series. The PN diode switch 12 and the PNPN diode switch 11 are connected in series with each other in the same direction as the one of the phase change resistor cells.

In addition, the series diode switch 10 is arranged in a plurality of layers, each of the upper series diode switch 10 and the lower series diode switch 10 is separated through an insulating layer 31.

Accordingly, one PN diode switch 12 and one PNPN diode switch 11 are sequentially selected among the diode elements connected in series to form one phase change resistance cell region.

FIG. 5 is a plan view of the phase change resistance cell 10 of FIG. 2.

The silicon layer 32 made of growth silicon or polysilicon forms a PNPN diode switch 11 and a PN diode switch 12 connected in series. Each silicon layer 32 is insulated from the upper and lower portions through the insulating layer 31. In the series diode switch 10, the P-type region of the PN diode switch 12 and the N-type region of the PNPN diode switch 11 are formed adjacent to each other so as to be commonly connected to the contact node CN of the phase change resistance element PCR.

In addition, the N-type region of the PN diode switch 12 and the P-type region of the PNPN diode switch 11 are connected to the bitline BL through the bitline contact node BLCN. The bitline contact node BLCN is commonly connected with the bitline contact node BLCN of the neighboring phase change resistance cell. That is, the same bit line contact node BLCN is commonly connected to the P-type region of the PNPN diode switch 11 and the N-type region of the PN diode switch 12 of the neighboring cell.

The word line WL is formed on the phase change resistance element PCR.

FIG. 6 is a diagram for describing an operation of the series diode switch 10 of FIG. 2.

When the applied voltage of the bit line BL increases in the positive direction based on the phase change resistance element PCR, the series diode switch 10 is kept off at the operating voltage Vo due to the operating characteristics of the PNPN diode switch 11. No current flows

Subsequently, when the applied voltage of the bit line BL is further increased to reach the threshold voltage Vc, the PNPN diode switch 11 is turned on and the series diode switch 10 is turned on according to the forward operation characteristic of the diode, thereby rapidly increasing the current. . At this time, the value of the current I consumed when the applied voltage of the bit line BL is greater than or equal to the threshold voltage Vc is due to the value of a resistor (not shown) connected to the bit line BL and serving as a load.

After the PNPN diode switch 11 is turned on, even a small voltage Vs is applied to the bit line BL, so that a large amount of current can flow. At this time, the PN diode switch 10 is maintained in the off state by the reverse operating characteristics.

On the other hand, when the applied voltage of the bit line BL increases in the negative direction based on the phase change resistance element PCR, that is, when a constant voltage is applied to the word line WL, the forward operation characteristic of the PN diode switch 10 is applied. This causes the series diode switch 10 to be turned on so that current flows at any operating voltage. At this time, the PNPN diode switch 11 maintains the off state due to the reverse operation characteristic.

7 is a configuration diagram of a nonvolatile memory device using a phase change resistance cell according to the present invention.

The present invention provides a plurality of PCR cell arrays 40, a plurality of word line drivers 50, a plurality of sense amplifiers 60, a data bus 70, a main amplifier 80, a data buffer 90 and input / output. The port 100 is provided.

Each PCR cell array 40 includes a plurality of unit phase change resistance cells having a structure as shown in FIG. 2 in a row and column direction. The plurality of word lines WLs arranged in the row direction are connected to the word line driver 50. The plurality of bit lines BL arranged in the column direction are connected to the sense amplifier 60.

Here, one PCR cell array 40 is connected in correspondence with one word line driver 50 and one sense amplifier 60.

The plurality of sense amplifiers 60 share one data bus 70. The data bus 70 is connected to the main amplifier 80, and the main amplifier 80 amplifies data applied from each sense amplifier 60 through the data bus 70.

The data buffer 90 buffers and outputs amplified data applied from the main amplifier 80. The input / output port 100 outputs output data applied from the data buffer 90 to the outside, or inputs input data applied from the outside to the data buffer 90.

8 is a layout diagram of the PCR cell array 40 of FIG. 7.

In the PCR cell array 40, a plurality of word lines WL are arranged in a row direction, respectively, and a plurality of bit lines BL are arranged in a column direction, respectively. In addition, since the unit cell C is positioned only in an area where the word line WL and the bit line BL cross each other, a cross point cell that does not require an additional area may be implemented.

Here, the cross point cell does not include an NMOS transistor device using a separate word line WL gate control signal. In addition, the structure of the phase change resistance device PCR using the series diode switch 10 having two connection electrode nodes can be positioned directly at the intersection of the bit line BL and the word line WL.

9 is a detailed circuit diagram of the PCR cell array 40 of FIG.

In the PCR cell array 40, a plurality of word lines WL <0> to WL <n> are arranged in a row direction, and a plurality of bit lines BL <0> to BL <m> are arranged in a column direction, respectively. The unit cell C is located only in an area where the word line WL and the bit line BL cross each other. Here, one unit cell C includes a phase change resistance element PCR and a series diode switch 10.

A plurality of sense amplifiers 60 are connected to each bit line BL in a one-to-one correspondence. Each sense amplifier 60 amplifies the result of comparing the voltage applied from the bit line BL with a predetermined reference voltage REF at the time of activation of the sense amplifier enable signal SEN.

In addition, the bit line pull-down element N1 is connected to the bit line BL <0>, and the bit line pull-down element N2 is connected to the bit line BL <m>. Accordingly, when the bit line pull-down signal BLPD is activated, the ground voltage is applied to the bit line BL to pull down the bit line BL to the ground level.

The PCR cell array 40 of this structure allows each phase change resistance element PCR to store one data.

10 is a timing diagram of an operation in a read mode of a nonvolatile memory device using a phase change resistance cell according to the present invention.

First, in the t0 period, the bit line pull-down signal BLPD is activated to turn on the NMOS transistors N1 and N2, thereby precharging the bit line BL to the ground level.

Subsequently, when the word line WL transitions high when the t1 section enters, and a constant voltage is applied to the word line WL, the PN diode switch 12 of the series diode switch 10 is turned on. Accordingly, the data of the PCR cell is transferred to the bitline BL. At this time, the bit line pull-down signal BLPD transitions to low.

Next, when the sense amplifier enable signal SEN transitions high in the period t2, the sense amplifier 60 operates to amplify the data carried on the bit line BL. When the column select signal CS transitions high, the column select switching unit (not shown) is turned on to output data D and / D on the bit line BL to the data bus 70 to read data stored in the PCR cell C. It becomes possible.

Subsequently, if the word line WL transitions low during the entry of the t3 section, the connection with the bit line BL is blocked to complete the read operation. At this time, both the PN diode switch 12 and the PNPN diode switch 11 of the series diode switch 10 maintain the turn-off state.

11 is a timing diagram of an operation in a write mode of a nonvolatile memory device using a phase change resistance cell according to the present invention.

In the write mode of the present invention, the sense amplifier enable signal SEN is kept low.

First, in the t0 period, the bit line pull-down signal BLPD is activated to turn on the NMOS transistors N1 and N2, thereby precharging the bit line BL to the ground level.

Thereafter, the bit line pull-down signal BLPD transitions low when the t1 period is entered. When the column select signal CS transitions high, the column select switching unit (not shown) is turned on so that new data D // D to be written through the data bus 70 is input to the bit line BL. Here, it is assumed that data applied to the bit line BL in the write mode is "high" or "low".

In this state, the voltage of the word line WL transitions to a negative voltage that is less than or equal to the threshold voltage Vc. That is, the difference between the low voltage level of the bit line BL and the negative voltage level of the word line WL does not reach the state of the threshold voltage Vc for turning on the PNPN diode switch 11 of the series diode switch 10.

However, according to the difference between the high amplification voltage of the bit line BL and the negative voltage of the word line WL, a voltage higher than or equal to the threshold voltage Vc for turning on the PNPN diode switch 11 is applied. As a result, the PNPN diode switch 11 is turned on so that data can be written to the phase change resistance element PCR.

At this time, after the PNPN diode switch 11 is turned on, as shown in the operating characteristic of FIG. 6, even if a small voltage Vs is applied to the phase change resistance device PCR, a large amount of current I can flow. Therefore, the current can flow sufficiently even if the voltage of the word line WL rises from the negative voltage to the low state again after the period t1.

Thereafter, the voltage drop level is different depending on the pattern of data applied to the bit line BL during the period t2 to tn.

That is, when the voltage level is applied to the bit line BL, the voltage level of the bit line BL is gradually decreased during the period t2 to tn. On the other hand, when the voltage level having the value of the data row is applied to the bit line BL, the voltage level of the bit line BL is continuously controlled during the t2 to tn period.

That is, as shown in FIG. 12, in order to keep the melting temperature of the phase change resistance element PCR that maintains the crystallization state at a low temperature at a low temperature when the data loaded on the bit line BL is "high". The level of the voltage applied to the voltage is dropped step by step. Accordingly, in the t1 section, the temperature characteristic of the data "high" gradually decreases after showing the peak value and shows low resistance characteristics.

Here, when the level of the voltage applied to the bit line BL is kept constant without dropping in voltage, the temperature of the phase change resistance element PCR is raised to change the phase change resistance element PCR in the crystallization state into an amorphous state. Accordingly, in the present invention, in order to maintain the crystallization temperature, the voltage level applied to the bit line BL is gradually dropped.

On the other hand, when the data loaded on the bit line BL is " low ", the level of the voltage applied to the bit line BL is kept constant in order to increase the melting temperature of the phase change resistance element PCR that maintains the amorphous state. That is, the higher the melting temperature, the higher the resistance characteristics and the characteristics of the phase change resistance element PCR in the amorphous state is improved. As a result, when a constant voltage is applied to the bit line BL, the temperature is increased to continuously maintain the amorphous state.

In the present invention, since data is stored in a phase change resistance device PCR having a nonvolatile characteristic, an operation process for restoring is unnecessary.

13 is a plan view illustrating a nonvolatile memory device using a phase change resistance cell according to the present invention.

According to the present invention, the PCR cell array 40 is disposed above the insulating layer 31, and the word line driver 50 for driving the PCR cell array 40 and a sense for driving the bit line are disposed below. A circuit element region 150 is disposed that includes an amplifier 60, a data bus 70, a main amplifier 80, a data buffer 90, an input / output port 100, and other circuits 110.

Here, the circuit element region 150 is formed on the silicon substrate 30, and the PCR cell array 40 is formed on the silicon layer 32 made of polysilicon or growth silicon. The PCR cell array 40 and the circuit element region 150 are separated from each other through the insulating layer 31.

Accordingly, the present invention can reduce the cell size without the need for a separate expansion region by arranging the PCR cell array 40 and the circuit element region 150 in different layers based on the insulating layer 31.

14 is another embodiment of a nonvolatile memory device using a phase change resistance cell according to the present invention.

14 shows the case where the PCR cell array 40 area of the present invention is divided into a plurality of cell array blocks. Each cell array block includes a word line driver 50, a sense amplifier 60, and a data bus 70 required for driving the cell array. In addition, the main amplifier 80, the data buffer 90, the input / output port 100, and the other circuits 110 are distributed in different cell array blocks.

15 is a cross-sectional configuration diagram of a nonvolatile memory device using a phase change resistance cell according to the present invention.

In the present invention, the PCR cell array 40 is disposed above the insulation layer 31. Here, the PCR cell array 40 includes a plurality of unit cells C connected in series. The unit cell C includes a series diode switch 10 including a PN diode switch 12 and a PNPN diode switch 11, a word line WL, a bit line BL, and a phase change resistance element PCR.

In addition, a plurality of circuit element regions 150 for driving the PCR cell array 40 are disposed in the lower silicon substrate 30 based on the insulating layer 31.

16 is a plan view illustrating a pad array 160 according to a first embodiment of the present invention.

In the embodiment of FIG. 16, the pad array 160 includes an address pin and a data pin to exchange data read / written from the PCR cell array 40 with an external controller of the chip. The pad array 160 is disposed in an outer region separate from the PCR cell array 40 and the circuit element region 150.

The present invention connects the metal layer required for the pad array 160 with the metal layer used in the circuit element region 160 so that the pad layer 160 can be used simultaneously. As a result, a space for forming a separate pad array 160 may be unnecessary, thereby reducing the mask layer.

17 is a cross-sectional view of the present invention according to the embodiment of FIG.

Referring to the configuration of FIG. 17, the pad array 160 is formed under the PCR cell array 40 and disposed at the same position as the insulating layer 31. The pad array 160 is connected to the circuit element region 150 to use the same metal layer.

18 is a plan view illustrating a pad array 160 according to a second embodiment of the present invention.

The pad array 160 is disposed in the same region as the PCR cell array 40 and the circuit element region 150.

The present invention includes a separate mask layer for the pad array 160 without connecting the metal layer required for the pad array 160 to the metal layer used for the circuit element region 160. As a result, a separate space for forming the pad array 160 is unnecessary, thereby reducing the size of the chip.

19 is a cross-sectional view of the present invention according to the embodiment of FIG. 18.

Looking at the configuration of Figure 19, the pad array 160 is formed on the upper side of the PCR cell array 40 to use a separate metal layer.

As described above, the present invention provides the following effects.

First, the phase change resistor cell array and the circuit element region can be efficiently arranged to reduce the overall size of the nonvolatile memory.

Second, in the above-described configuration, the pad array can be efficiently arranged to reduce the cell size of the nonvolatile memory.

Claims (12)

A plurality of phase change resistance cell arrays including a plurality of unit phase change resistance cells arranged in a row and column direction; A circuit element region formed on a silicon substrate disposed under the plurality of phase change resistor cell arrays to drive and amplify the plurality of phase change resistor cell arrays; And An insulating layer formed between the plurality of phase change resistance cell arrays and the circuit element region to insulate the plurality of phase change resistance cell arrays and the circuit element region from each other, The unit phase change resistance cell is A phase change resistance device configured to store a data corresponding to a change in resistance by detecting a crystallization state that changes according to a magnitude of a current applied from a word line; And A series diode switch having at least two diode switches continuously connected in series and having a common connection node connected to one end of the phase change resistance element, and selectively switched according to the magnitude of the voltage applied to the word line and the bit line. Non-volatile memory device using a phase change resistance cell, characterized in that provided. The method of claim 1, wherein the unit phase change resistance cell A bit line connected to both ends of the series diode switch through a bit line contact node; A contact node connecting a common node to which the at least two diode devices are connected and a bottom electrode of the phase change resistance device; And And a word line formed over the top electrode of the phase change resistance element. The nonvolatile memory device of claim 1, wherein the series diode switch is formed on at least one silicon layer of polysilicon and growth silicon. The method of claim 1, wherein the series diode switch A PN diode switch connected in a forward direction between the bottom electrode of the phase change resistance device and the bit line; And And a PNPN diode switch connected in a reverse direction between the bottom electrode of the phase change resistor and the bit line. The nonvolatile memory device of claim 4, wherein the P-type region of the PN diode switch is connected to the bottom electrode, and the N-type region is connected to the bit line. The nonvolatile memory device of claim 4, wherein an upper N-type region of the PNPN diode switch is connected to the bottom electrode, and a lower P-type region is connected to the bit line. The method of claim 1, wherein each of the plurality of phase change resistor cell arrays comprises: A plurality of unit phase change resistance cells positioned in an intersection region between the plurality of word lines and the plurality of bit lines arranged in the row and column directions, respectively; And And a plurality of bit line pull-down elements connected one-to-one to the plurality of bit lines, respectively. The method of claim 1, wherein the circuit element region A plurality of word line drivers selectively driving word lines of the plurality of phase change resistance cell arrays; A plurality of sense amplifiers for sensing and amplifying data applied from the plurality of phase change resistance cell arrays; A data bus shared by the plurality of sense amplifiers; A main amplifier for amplifying data applied from the data bus; A data buffer for buffering amplified data applied from the main amplifier; And And an input / output port configured to output the output data applied from the data buffer to the outside or to apply the input data applied from the outside to the data buffer. The method of claim 8, wherein the plurality of sense amplifiers are connected to the plurality of bit lines in a one-to-one correspondence, and the reference voltage and the voltage of the bit line are compared and amplified when the sense amplifier enable signal is activated. Nonvolatile memory device using a change resistance cell. The method of claim 8, wherein the plurality of phase change resistance cell arrays are divided into a plurality of cell array blocks, and the main amplifier, the data buffer, and the input / output port are separately disposed in separate cell array blocks. A nonvolatile memory device using a phase change resistance cell. The pad array of claim 1, further comprising a plurality of phase change resistor cell arrays and a pad array disposed in an outer region separate from the circuit element region and using the same metal layer as the circuit element region. Nonvolatile memory device using a phase change resistance cell. The phase change resistor cell of claim 1, further comprising a pad array formed on a metal layer formed on the plurality of phase change resistor cell arrays, the pad array configured to exchange an address and data with an external device. Nonvolatile Memory Device.

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