KR100607614B1 - Display module driving system comprising digital to analog converters - Google Patents

Abstract

It is directed to a display module driving system in which the digital pixel data of an image to be displayed is provided to a plurality of column drivers based on one row in series through a plurality of dedicated bus lines rather than one parallel bus line. The digital pixel data of the entire image row is divided into segments, each of which is for a plurality of column drivers. Each segment is then serialized and sent to the corresponding column driver, so that the entire digital pixel data of the row is simultaneously delivered to each of the plurality of column drivers. The column driver receives the segments and rearranges the data in parallel. The pixel is then preferably passed to the digital-to-analog converter two pixels at a time, each pixel being converted to analog red, green and blue signals. The analog sample and hold module samples each analog signal for every pixel in a given row of the display and stores these signals in the first capacitor of the plurality of sample and hold capacitor pairs. The sample and hold capacitor pairs, when one capacitor of each pair stores one of the analog red, green, and blue voltages for the subsequent row, cause the other capacitor to display the analog voltage signal from the current row of the display. To transmit to the column electrodes, the analog signal can be sampled and held on a row-by-row basis.

Timing Controllers, Serial-to-Parallel Conversion, Analog-to-Digital Conversion, Pixel Data, Thermal Drivers

Description

Display module driving system including digital to analog converter {DISPLAY MODULE DRIVING SYSTEM COMPRISING DIGITAL TO ANALOG CONVERTERS}

<Related Technology>

Under 35 of United States Patent Act Section 119 (e), this application claims the rights of U.S. Provisional Application No. 60 / 088,128, filed June 4, 1998.

The present invention relates to a drive system for an active matrix (thin film transistor) liquid crystal display. In particular, the present invention relates to a drive system for serially transferring segments of digital pixel data to a plurality of column drivers via independent serial bus lines, wherein the column drivers arrange the segments of digital pixel data in parallel and convert these segments into analog signals. And analog signals are driven to drive the column electrodes of the active matrix liquid crystal display.

With the recent technological advances in active matrix (thin film transistor) liquid crystal displays, active matrix displays have seen a sharp increase over the last few years. In an active matrix display, there is a gate composed of one transistor or switch corresponding to each display cell of the matrix. The active matrix display first applies a selection voltage for activating the gate of the row of the cell to the row electrode, and then applies an appropriate analog data voltage to the column electrode to charge each cell in the selected row to the desired voltage level.

Typically, an active matrix liquid crystal display includes a drive system that drives an analog data voltage to a column electrode using a column driver. Multiple column drivers are used to support all rows of the active matrix liquid crystal display. For example, for a matrix display with a pixel dimension of 1024 × 768, there are actually 3072 subpixels or display cells per row (each pixel having a red subpixel, a green subpixel, and a blue subpixel). Thus, such displays may require up to eight column drivers, each column driver preferably supporting 384 subpixels or display cells. Typically, each subpixel is represented by digital pixel data having a bit depth of 6 bits or 8 bits. Bit depth represents the number of bits available per subpixel to control the luminance of the red, green, and blue colors displayed in that subpixel. The pixel depth can vary depending on the drive system. Thus, in a conventional drive system, each column driver is loaded with at least 2304 bits (6 bits per subpixel × 384 subpixels). All bits are sequentially loaded into the column driver through a single parallel bus line so that they are loaded in turn into each column driver.

Once all the bits of the 384 subpixels have been loaded into any one column driver, the digital memory registers are used to hold the digital pixel data until all eight column electrodes are loaded. After loading into all eight column drivers, the digital pixel data of each subpixel is converted into analog red, green and blue signals. This is typically accomplished by using one digital-to-analog converter for each subpixel in each column driver. Thus, each column driver requires 384 digital-to-analog converters. These converters may be 8-bit or 6-bit converters, depending on the bit depth of the drive system. This requires a large number of digital-to-analog converters, which occupy a significant amount of die area, depending on whether each converter is a 6-bit or 8-bit converter. Further, the digital-to-analog converter in the prior art example is designed to operate all at the same rate so that all RGB analog signals are generated for all 384 subpixels at the same time. Therefore, such a design is very difficult and expensive.

Once the digital pixel data of each subpixel in all column decoders is converted into an RGB analog signal, the analog signals are typically applied to a buffer to generate enough current to drive the column electrodes of the active matrix liquid crystal display.

1 illustrates a conventional active matrix liquid crystal display drive system. As shown, the conventional system includes an active matrix liquid crystal display 100 having a resolution of 1024 x 768 pixels. This display is driven by gate modules 180a-180d and column drivers 160a-160h. Due to spatial constraints, FIG. 1 shows only the column drivers 160a, 160b, 160c, 160h, but eight column drivers are used in a conventional drive system for driving displays having a resolution of 1024 pixels by 768 pixels. It can be seen that each column driver supports 384 subpixels or memory cells. As shown in FIG. 1, timing controller 110 is coupled to each of column drivers 160a through 160h via parallel data bus line 150. Timing controller 110 is coupled to each of gate modules 180a through 180d to provide a row voltage for activating display cells in each row.

Timing controller 110 provides digital display data of the image to be displayed to the column driver in the form of digital pixel data for each row. Digital pixel data is provided in parallel using parallel data bus lines 150. The master clock signal MCLOCK 112 is used to control the rate at which digital pixel data is transmitted over the parallel data bus line 150. The timing controller 110 receives digital display data of an image to be displayed and stores the information in such a manner as to receive one display row amount of information from several external sources at a time. The external source may be a hard disk drive, CD-ROM drive, flash memory card, or other suitable external storage device in the computer. Alternatively, the external source may consist of an intranet or the internet. Digital display data is received as digital pixel data. Timing controller 110 stores digital pixel data in a memory array (not shown) within the timing controller. The timing controller 110 then uses the parallel data bus line 150 and the master clock MCLOCK signal 112 to transmit digital pixel data to the column drivers 160a through 160h in parallel. When each row of the image to be displayed is sent to the column driver via the parallel data bus line 150, the digital pixel data of the next row is received and stored in the internal memory of the timing controller 110.

Each pixel supports a red subpixel, a green subpixel, and a blue subpixel. In most video display applications, each pixel has a 6 or 8 bit pixel depth. This means that each red, green and blue subpixel requires 6 or 8 bits, so that the parallel data bus line 150 must be 36 or 48 bit line wide. This is typically because digital pixel data is transmitted over the parallel data bus line 150 two pixels at a time, ie two pixels per MCLOCK pulse at a 65 MHz clock rate in the case of a 6 bit pixel depth application. Thus, in the conventional drive system shown in FIG. 1, the parallel data bus line 150 is shown as a 36 bit bus line and transmits two 18 bit pixels at a time per MCLOCK signal pulse at a clock rate of 65 MHz [ (R0 (5: 0), G0 (5: 0), B0 (5: 0)) and (R1 (5: 0), G1 (5: 0), B1 (5: 0)).

Each of the column drivers 160a-160h is coupled to the parallel data bus line 150. In the prior art, the column drivers 160a through 160h receive two pixels simultaneously, while the digital pixel data is sequentially loaded. Thus, in the prior art drive system of FIG. 1, digital pixel data is loaded from the controller 100 into the first column driver 160a until all 384 subpixels are loaded into the first column driver 160a. Shift registers or some other suitable device are preferably used to track the loading process. Once the first column driver 160a is fully loaded, the enable signal 165 is then activated from the first column driver 160a to the second column driver 160b so that the second column driver 160b is digital. It is possible to begin downloading the pixel data from the parallel data bus line 150. Again, second column driver 160b includes a shift register or some other suitable device for tracking the loading process. Once the second column driver 160b loads all 384 subpixels, its enable signal 165 is activated from the second column driver 160b to the third column driver 160c, so that the third column driver ( Enable 160c to begin downloading digital pixel data from parallel data bus line 150. This process continues until all heat drivers are loaded.

Once all the column drivers 160a-160h are loaded. The timing controller sends a load signal 115 to each of the column drivers 160a-160h to tell them to start converting the digital pixel data for each subpixel into analog red, green, or blue signals. Instruct. The digital pixel data for each subpixel in column drivers 160a through 160h is then converted to an analog voltage. This is accomplished by loading each subpixel into a digital-to-analog converter. The load signal 115 from the timing controller instructs all column drivers to load each subpixel into the digital-to-analog converter. As such, each column driver 160a through 160h requires 384 different digital-to-analog converters to convert each subpixel into a red, green or blue analog signal. Thus, in the prior art embodiment shown in FIG. 1, each digital-to-analog converter must be a 6-bit converter and the conversion of each pixel from digital pixel data to an analog signal requires that all column drivers be loaded and the timing controller 110 Occurs after the load signal 115 is transmitted. Although the embodiment shown in FIG. 1 represents 6 bit depths per subpixel, the prior art can typically use 8 bit pixel depth, thus providing 384 8 bit digital to analog converters (one for each subpixel). It can be seen that it is necessary.

After the digital pixel data for each subpixel is converted to an analog signal, each of the analog red, green and blue signals is passed through a buffer and applied to the column electrodes based on the entire row to generate a sufficient current level. Thus, at the same time all the red, green and blue analog signals for each subpixel in the row are applied to the column electrodes so that the entire row is displayed in synchronization. The above-described whole steps are repeated on a row-by-row basis until the entire picture to be displayed is transmitted, converted and displayed.

2 shows a functional block diagram of a conventional column driver 160. As shown, a conventional column driver 160 includes a data register 200 for loading digital pixel data from a parallel data bus line 150 and a shift register 210 to keep track of the loading process. . The conventional column driver 160 also uses an independent holding register (figure 3) to hold 384 subpixel data once the completed row data for a particular column driver is loaded from the parallel data bus line 150. 220). In this manner, the conventional column driver 160 can process the 384 subpixel data received for the current row while continuing to sample the digital pixel data for the next row for display.

Digital pixel data is loaded into the data register 20 of the column driver, in 36 bits in a parallel fashion, or two pixels at a time. The shift register 210 is preferably a 64 stage shift register. Each time 36 bits or two pixels are loaded into the data register 200 of the column driver, the shift register 210 increments one stage. Thus, when 36 bits or two pixels are loaded from the parallel data bus line 150 into the data register 200, the shift register 210 increments one stage. When the next 36 bits or two pixels are loaded into the data register 200 in a parallel manner, the shift register 210 increments another stage. When all 128 pixels have been loaded into the data register 200, the shift register 210 increments to the final 64th stage, so that the column driver 160a sends the enable signal 165 to the next column driver 160b. By triggering column driver 160a to transmit to, next column driver 160b may begin downloading digital pixel data from parallel data bus line 150.

When all 128 pixels are loaded into the data register 200, the timing controller 110 transmits the load signal 115 to the hold register 220, and all 128 pixels are transferred in parallel to the hold register 220 and held. In this way, once the final column driver 160h is fully loaded, the first column driver 160a can once again begin downloading digital pixel data from the parallel bus line 150 to the data register 200.

Conventional column drivers also include 384 digital-to-analog converters (one for each subpixel). When all of the digital pixel data for each subpixel within a row is loaded into all column drivers 160a through 160h, each 6 bit subpixel (red, green, blue) is analog red in each column driver 160a through 160h. The signal is converted into a green or blue signal, which is buffered and delivered to the column electrodes of the display. Thus, each column driver requires 384 digital-to-analog converters, one for each subpixel, which can be either 6-bit or 8-bit converters (depending on the bit depth of the particular drive system involved). After all digital pixel data in all column drivers is converted into analog signals, the analog red, green and blue signals are buffered to generate sufficient current and delivered to the column electrodes of the display.

Typically, one row of data is provided one pixel at a time at a pixel rate of 65 MHz within 16 μsec or two pixels at a time at a pixel rate of 32.5 MHz. This 16 μsec is split between the column drivers because each column driver receives the digital pixel data sequentially, i.e. the preceding column driver receives all the digital pixel data and after the enable signal is activated. Thus, it can be seen that the amount of time required to transfer data to each column driver and convert this data to analog values is limited. As active matrix displays become larger, it becomes increasingly difficult to design the implementation and performance of the drive system. The number of column drivers increases, and the amount of time required to load data into each column driver and convert it to an analog signal decreases, so the driver must be faster each time the number of pixels or the resolution of the display increases.

Accordingly, there is a need for a system and method that can efficiently drive an active matrix liquid crystal display as the number of pixels or the resolution of the display increases.

Summary of the Invention

It is an object of the present invention to provide an improved display module drive system with six digital to analog converters per column driver instead of 384 digital to analog converters. Moreover, the improved display module drive system of the present invention, unlike conventional driver systems, transmits data simultaneously in series to each column driver without using parallel data bus lines. This configuration reduces EMI and current consumption, and increases the processing time allocated to each column driver for digital-to-analog conversion.

According to one aspect of the present invention, the drive system includes a controller that serially supplies digital display data to a plurality of column drivers via a plurality of dedicated serial bus lines rather than one parallel data bus line. The serial bus line may be two or three bit lines depending on the number of bits used per RGB subpixel. Instead of transferring pixel data in parallel over one parallel bus line, serially transferring digital pixel data to each column driver through dedicated serial bus lines, allowing each column driver to simultaneously receive and process digital display data. More time is allowed for processing parallel pixel data for the column driver.

According to another aspect of the present invention, a drive system includes a plurality of column drivers for driving column electrodes of an active matrix liquid crystal display. Each column driver receives digital pixel data in series over a dedicated bus line and arranges the digital pixel data in parallel. When the digital pixel data is arranged in parallel, each subpixel is converted into an analog signal at the stage of the column driver earlier than the prior art. The analog signal is then sampled and held until all column drivers have converted their digital pixel data. Since the conversion takes place at an earlier stage, each column driver only needs six digital-to-analog converters instead of 384 digital-to-analog converters.

According to yet another aspect of the invention, each column driver comprises an analog sample and hold module comprising six pairs of sample and hold capacitors and two different sets of switches. The analog signal is optionally sampled and used to charge one of the capacitors of each of the six pairs of sample and hold capacitors. Meanwhile, the other capacitors of each of the six pairs of sample and hold capacitors are discharged, and the voltage stored in the capacitors is transferred from the discharge capacitors to the heat driver to drive the display. In this way, the sample and hold capacitors alternately store and emit the analog voltages used to drive the column electrodes of the display, thus allowing the column driver to operate at high speed.

1 shows a conventional active matrix liquid crystal display drive system.

2 is a functional block diagram of a conventional heat driver.

3 is a functional block diagram of a display drive system according to the present invention.

4 illustrates the serial transmission of digital pixel data from the timing controller to each of the individual column drivers in the system of the present invention.

5 is a functional block diagram of a preferred embodiment of a controller used in the display drive system according to the present invention.

6 is a functional block diagram of a preferred embodiment of a heat driver for use in a display drive system according to the present invention.

7 is a schematic diagram illustrating operation of a preferred embodiment of a heat driver for use in a display drive system according to the present invention.
8 is a detailed view of a first stage according to the invention.

3 is a diagram illustrating a display drive system according to the present invention. The active matrix display is driven by gate modules 380a-380d and column drivers 340a-340h. Due to spatial limitations, FIG. 3 shows only thermal drivers 340a, 340b, 340c, and 340h. However, in the driving system of the present invention, eight column drivers are used to drive an active matrix display having a resolution of 1024 pixels by 768 pixels, each of which supports 384 subpixels or memory cells of the active matrix display. do.

As shown in FIG. 3, the timing controller 300 is connected to eight column drivers 340a-340h and four gate modules 380a-380d. Gate modules 380a-380d provide a row voltage to the active matrix display to activate the display cells in each row of the display. Timing controller 300 stores digital pixel data of the image to be displayed, and supplies this digital pixel data to column drivers 340a-340h. The digital data is preferably stored in the pair of memory modules 310a and 310b in the timing controller 300.

The memory modules 310a and 310b may each be formed of a matrix of memory cells arranged in rows and columns. Digital pixel data of an image to be displayed on an active matrix display is received by the timing controller 300 from an external source such as a CD-Rom, a hard disk drive, or a modem connected to an intranet / internet. The digital pixel data of the image to be displayed is preferably stored in each of the memory modules 310a and 310b of the timing controller as the data is received. The timing controller preferably stores a first row of digital pixel data in one module of memory module 310a or 310b and a second row of digital pixel data in another memory module 310a or 310b. In this way, when digital pixel data is read from one memory module 310a or 310b, the digital pixel data of the next row of the image to be displayed can be loaded into the other memory module 310a or 310b, and thus two Memory modules 310a and 310b are alternately read and written until all digital pixel data of each row of the image to be displayed is processed and displayed. Alternatively, the timing controller may use any other suitable memory device to temporarily store a separate row of digital pixel data, while the other row is read from the memory device for display while one row is being stored in the memory device. Is processed.

The timing controller 300 provides digital pixel data to the plurality of column drivers 340a-340h to drive the column electrodes of the active matrix liquid crystal display. Unlike the conventional display driving system, the timing controller 300 of the present invention is connected to each of the plurality of column drivers 340a-340h by a plurality of dedicated bus lines 325a-325h having one dedicated bus line per column driver. Connected. Each dedicated bus line 325a-325h is preferably a 3-bit bus line. Alternatively, each dedicated bus line may be a 2-bit bus line.

In operation, the pixel data of the entire row is retrieved by the timing controller 300 from the memory of the timing controller 300 on a parallel basis of each of the column drivers 340a-340h. The digital pixel data is then divided into eight parallel segments, with one parallel segment maintained for each column driver 340a-340h. The digital pixel data in each parallel segment is converted into serial form and transmitted to the column drivers 340a-340h via dedicated bus lines 325a-325h. Thus, the entire digital pixel data of one row in the image to be displayed is transmitted simultaneously to each of the column drivers 340a-340h so that either column driver receives its own individual segment of serial digital pixel data simultaneously. Each of the other column drivers also receive its own individual segment of serial digital pixel data. Thus, each column driver 340a-340h is able to start processing its own segment of serial digital pixel data without having to wait for the digital pixel data to be sent to each other column driver. Thus, unlike conventional column drivers, the column drivers 340a-340h of the present invention do not require an enable signal before being loaded.

In particular, the digital pixel data across the first row of the active matrix liquid crystal display is retrieved from the memory of the timing controller 300 and divided or broken into segments. Each segment is about 128 pixels long or preferably 348 RGB subpixels. Each segment of digital pixel data is transmitted in series to the corresponding column drivers 340a-340h via appropriate corresponding dedicated bus lines 325a-325h. Accordingly, the digital pixel data from the first segment is serially transmitted to the column driver 340a via the dedicated bus line 325a, while at the same time the digital pixel data from the final segment is transferred through the dedicated bus line 325h. 340h). In this way, digital pixel data is sent serially to each column driver, each column driver receiving digital pixel data corresponding to its row segment without having to wait for previous column drivers to receive their segment. .

Moreover, FIG. 4 illustrates the concept of how digital pixel data is transferred from timing controller 300 to each of column drivers 340a through 340h. 4 shows a digital pixel data stream 400 representing a row of an active matrix liquid crystal display 100. The entire digital pixel data actually consists of 1024 pixels of 18,432 bits, with each pixel in the row having a six-bit long red subpixel, a six-bit green subpixel, and a six-bit long blue subpixel. However, for ease of understanding the basic operation of the present invention, the illustrated digital pixel data is composed of blocks each representing one pixel. The total number of pixels is not equal and is reduced for illustrative purposes.

As shown, in FIG. 4, the entire parallel digital pixel data in a row is divided into eight portions 410a through 410h (one portion for each of the column drivers 340a through 340h). The first portion 410a of the entire parallel digital pixel data of the row is sent to the column driver 340a and the second portion 410b of the entire parallel digital pixel data of the row is sent to the column driver 340b. However, before portions 410a through 410h are transferred to their respective column drivers, these portions are each converted into segments of serial digital pixel data, one pixel at a time. The process of converting these parts from parallel digital pixel data to serial digital pixel data proceeds through all 128 pixels corresponding to the column driver.

Thus, the first portion of parallel digital pixel data 410a is converted into segments of serial digital pixel data one pixel at a time until all 128 pixels are converted. The segment of serial pixel data is then sent serially to first column driver 340a via dedicated bus line 325a. In a 6-bit pixel depth design (each subpixel is represented by 6 bits), dedicated bus line 325a is a dedicated bus line where two pixels are two bits at a time (one bit through each bitline) for each MCLOCK pulse. It is desirable to have a 2-bit width so that it can be transmitted serially over 325. Thus, all the bits of the red subpixel, green subpixel, and blue subpixel in two pixels are transmitted in series over two bit lines in eighteen MCLOCK pulses. The 128 pixels of data sent to one column driver would require 1152 clock cycles of 1 bit per line per clock cycle for a 65 MHz clock rate.

In another embodiment for an 8 pixel depth design (each subpixel is represented by 8 bits), each dedicated bus line has a 3 bit line width, so that 3 bits are simultaneously (one bit for each bit line) for each MCLOCK pulse. ) Is sent. Thus, in this alternative embodiment, all bits for the red subpixel, green subpixel, and blue subpixel are transmitted in series on three bit lines within 16 MCLOCK pulses. The 128 pixel data sent to a single column driver requires 1024 clock cycles, one bit per line per clock cycle, for a clock rate of 65 MHz. Alternatively, digital pixel data can be transmitted at half the clock rate and sampled on both the rising and falling edges of the clock pulse.

The second portion of parallel digital pixel data 410b is converted into segments of serial digital pixel data one pixel at a time until all 128 pixels are converted. Segments of serial pixel data are then transmitted via a dedicated bus line 325b to the second column driver 340b, preferably two pixels at a time. Again, in a preferred embodiment for 6-bit pixel depths (each sub-pixel is represented by 6 bits), the dedicated bus line 325b preferably has a 2-bit width, thus red sub-pixels, green sub-pixels and blue subs. All bits for a pixel are transmitted serially over two bit lines within 18 MCLOCK pulses.

The process is the same for all eight portions 410a-410h of all parallel digital pixel data in a row. All eight portions 410a-410h are converted into segments of serial digital pixel data and then transmitted to the appropriate column drivers 340a-340h via corresponding dedicated bus lines 325a-325h. As long as the parallel digital pixel data is divided into parts, the parts are aligned to the serial segments of the digital pixel data, and the segments of the digital pixel data are transmitted on dedicated bus lines 325a-325h. It should be appreciated that there may be other embodiments in the transmission of segments of serial digital pixel data from the column drivers 340a-340h.

5 shows a preferred embodiment of a timing controller 200 for use in a display drive system according to the present invention. As shown, the controller 200 includes a driver and gate timing control circuit 500, a data path control circuit 510, two separate memory modules 520a and 520b and a parallel-to-serial converter 525. have. In a preferred embodiment, each of the two memory modules holds 1024 digital pixel data with 6 bit red, green and blue subpixels, such that each memory is 18432 bits (1024 pixels x 3 subpixels x 6 bits per subpixel). Digital pixel data can be stored. In an alternative embodiment, each two memory modules hold 1024 pixels of digital pixel data with 8 bits of red, green and blue subpixels, such that each memory is 24576 bits (1024 pixels x 3 subpixels x subpixels). 8 bits) of digital data can be stored. Each memory is preferably a memory cell matrix arranged in a matrix. Alternatively, any other suitable temporary data storage means can be used as the memory.

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Digital pixel data is read out from an external source such as a CD-ROM via a 6 bit RGB signal line and stored one row in each of two memory modules 525a and 525b. Therefore, the digital pixel data of the first row of the 1024 pixel image is stored in the first memory. As this data is read in the column driver, the digital pixel data of the second row of the 1024 pixel image is stored in the second memory. Once all data from the first memory is transferred to the column driver, the second memory sends the second row of digital pixel data to the column decoder while the first memory stores the data corresponding to the third row of the image. In this way, one memory reads data to the column driver while the other memory receives data from an external source such as a CD-ROM. The data path control circuit 501 controls to receive input digital image data from an external source in some memories and to read digital pixel data to a column driver in some memories.

In the present invention, the controller 200 includes a parallel to serial data converter 525. Unlike conventional controllers, digital pixel data is provided in series to each of the column drivers 340a through 340h via dedicated bus lines 325a through 325h rather than parallel data bus lines. Parallel-to-serial data converter 525 retrieves data from memory in parallel and divides this data into segments, where the number of segments is equal to the number of column drivers. Each segment is converted into serial data and sent to the appropriate column driver through the corresponding dedicated bus line.

6 illustrates a preferred embodiment of a thermal drive system 340a used in a display drive system according to the present invention. As shown, the column driver 340a includes a frequency divider 610, where the frequency divider is coupled to the shift register 630, which is coupled to the analog sample and hold module 640. As shown in FIG. The column driver 340a also includes a serial-parallel converter 620 coupled between the frequency divider 610 and the digital-to-analog converter module 625. Digital-to-analog converter module 625 is comprised of six individual digital-to-analog converters 635a to 635f. Digital-to-analog converter module 625 is also coupled to analog sample and hold module 640. Finally, the column driver includes a buffer 650 coupled to the analog sample and hold module.

In operation, column driver 340a receives a segment of serial digital pixel data at serial-to-parallel converter 620 and converts the digital pixel data from serial format to parallel format so that each subpixel (red, green and blue) Rearranged into six parallel bits. Preferably, parallel digital pixel data is then fed to the digital-to-analog converter module 625 two pixels at a time on a 36-bit bus line so that each of the six digital-to-analog converters 635a through 635f is one 6 bit. Receive a subpixel.

As mentioned above, the digital-to-analog converter module 625 is preferably comprised of six individual digital-to-analog converters 635a to 635f, each of which is a six-bit subpixel. Is converted from the digital pixel data into an analog signal. Digital-to-analog converter module 625 preferably has at least 16 different reference voltages. Thus, each 6 bit subpixel is converted to one of at least 16 different reference voltages. Thus, two pixels are input to the digital-to-analog converter 625 and six analog signals are output, one analog signal for each 6-bit red, green and blue subpixel in the two pixels.

In alternative embodiments, digital pixel data may be passed to the digital analog converter module 625 at least two pixels at a time. In this alternative embodiment, the digital-to-analog converter module 625 will require six or more individual digital-to-analog converters 635a through 635f. For example, digital-to-analog converter 625 may receive digital pixel data at four pixels at a time over a 72-bitline bus. However, unlike the prior art, it is not required in the present invention that all subpixels are converted at the same time. Thus, 384 digital-to-analog converters are not necessary. In addition, it is intended that an alternative embodiment with a higher or lower reference voltage be included here, with the numerical value of the reference voltage being variable.

Preferably, after all two pixels have been converted, six analog signals are output from the digital-to-analog converter module 625 and one analog signal is for each digital-to-analog converter 635a to 635h. The analog signal is output over six line buses sampled by the sample and hold module 640. Frequency divider 610 and shift register 630 control the sampling rate of sample and hold module 640. Preferably, shift register 630 is a 64 stage shift register in which six analog signals (one for each subpixel in two pixels) are sampled at each stage. Thus, when digital-to-analog converter module 625 converts digital pixel data two pixels at a time, it outputs six analog signals that are sampled when the shift register cycles through each of its 64 stages. Therefore, when the shift register 630 cycled through those 64 stages, all 384 different analog signals (one for each subpixel) were sampled. In this way, after cycling through all 64 stages, three different red, green, and blue analog signals for each of the 128 pixels were completely sampled by each column driver. The sample and hold circuit preferably uses a dual capacitor arrangement in which analog signals for each of the two pixels can be stored and sampled in each of the capacitors in different ways.

Figure 7 shows a schematic diagram showing the operation of a preferred embodiment for a column driver employing a display driver system according to the invention. Each column driver includes 64 stages with six analog signals output from each stage. Because of simplicity of understanding and spatial constraints, only the first three stages 702a through 702c are shown in FIG. 7. However, as shown in FIG. 7 and described below, stages 702b and 702c are identical in structure and performance. In addition, the other 61 stages not depicted in FIG. 7 also share the same structure and performance as shown in stages 702b and 702c of FIG. 7. Therefore, it is not necessary to show all 64 stages in order to understand the operation of the heat driver designed according to the present invention.

Referring to FIG. 7, each stage 702a through 702c includes a flip-flop 710 having a data input D and two outputs Q and QN. Flip-flop 710 is used as a latch with a clock signal input that activates the latch each time the clock signal is active. As shown in FIG. 6, the clock signal is actually a sampling clock signal 660 that is the output of the frequency divider 610 of the column driver. In the preferred embodiment, each flip-flop 710 is activated when the sampling clock signal 660 transitions from low to high. The flip-flop 710 activates the corresponding stages 702a to 702c in such a manner that the first flip-flop 710a activates the stage 702a and the second flip-flop 710b activates the stage 702b. Used. The operation of flip-flop 710 is described in detail below.

Each stage further includes a first set of six switches 780 (indicated as 780a to 780c surrounded by dashed lines in FIG. 7) and six pairs of analog samples and hold capacitors. Each of the six pairs of analog sample and hold capacitors consists of a first capacitor and a second capacitor, the anode of each pair of first capacitors is coupled to each switch terminal A, and the anode of each pair of second capacitors is each It is coupled to switch terminal B. In six pairs of analog sample and hold capacitors, the cathode of each pair of capacitors is connected to the ground signal.

Flip-flop 710 is all connected to sampling clock signal 660 that is the output of frequency divider 610 (FIG. 6). Data input D from each column driver to first flip-flop 710a is connected to an enable signal from timing controller 200 (FIG. 5). The data input D of each subsequent flip-flop in the other 63 stages is connected to the output Q from the previous flip-flop. This configuration implements the shift register 630 of the column driver.

Referring to FIG. 7, it is easy to see how the shift register 630 operates and cycles through 64 stages. When both the enable signal and the sampling clock signal are active, the first stage flip-flop 710a latches the enable signal through its output Q. Since the output Q from the first stage flip-flop 710a is connected to the data input D of the second stage flip-flop 710b, both the sampling clock signal and the enable signal are activated next, and the second stage flip-flop 710b. ) Latches the enable signal to its output Q. Again, since the output Q from the second stage flip-flop 710b is connected to the data input D of the third stage flip-flop 710c, next, both the sampling clock signal and the enable signal are activated, and the enable signal is zero. It is latched to its output Q via a three stage flip-flop. This process is repeated over 64 stages until the enable signal is latched through all 64 flip-flops.

The output Q of each of the 64 flip-flops is also coupled to the first input A of the pair of AND gates 750a and 750b. Input B of AND gates 750a and 750b is coupled to a load signal, one of input B of AND gate 750b being inverted. Referring to FIG. 7, according to the above configuration, the outputs from the AND gates 750a and 750b are opposite to each other so that the outputs of the other AND gates 750b are low when the output of the AND gate 750a is high. The outputs of the AND gates 750a and 750b are coupled to each of the six switches of the first set of switches 780a through 780c and are used to alternately activate the switches. For example, when the output of the AND gate 750a goes high, the switches are activated to the first position, and when the output of the other AND gate 750b goes high, the switches are activated to the second position, which results in a first set. All six switches of the switches 780a to 780c of s alternate back and forth between the first and second positions as the outputs of the two AND gates 750a and 750b alternate.

8 is a detailed view of the first stage 702a and shows the operation of the first set of switches 780a and the second set of switches 790a. The first set of switches 780a and the second set of switches 790a have the same configuration at each stage, so the switches operate in the same way at each stage. In each stage, the first set of switches 780a only operate when the output Q of the flip-flop is valid for that stage.

As shown in FIG. 8, each stage includes six switches in the first set of switches 780a and six switches in the second set of switches. In the first set of switches 780a, the end terminal C of each switch is connected to one of six analog signal lines a0 to a5 which are outputs of the analog-to-digital converter 625 (FIG. 6). Analog signals a0 through a5 represent the analog voltages for each of the subpixels in two separate pixels. In the first set of switches 780a each switch has a first terminal A and a second terminal B, the end terminal C is connected to the first terminal A when the switch is in the first position, and the switch is in the second position When is at, end terminal C is connected to a second terminal B. The first terminal A is connected to the anode of the first capacitor of the corresponding capacitor pair of the six pairs of capacitors. Terminal B of each switch is connected to the anode of the second capacitor of the corresponding capacitor pair of the six pairs of capacitors.

In order to store the analog voltage level from the analog signal lines a0-a5 for the subpixel on one of the capacitors, the first set of switches 780a is adapted to one of the analog signal lines a0-a5. One of the capacitors of the corresponding capacitor pair of the six pairs of capacitors is connected. The voltages are stored alternately for each subsequent row, with each capacitor pair in the first set of switches 780a having a voltage level of six capacitor pairs for corresponding subpixels in a particular row. Stored in first capacitors in each, and when each switch in the first set of switches 780a is in the second position, the voltage level for the corresponding subpixels in the subsequent row is equal to the first in the six capacitor pairs. Stored in two capacitors.

In addition, as shown in FIG. 8, a second set of six switches 790a are present in each of the 64 stages and are used to alternately transfer the voltages output from each of the sample and hold capacitor pairs, one row at a time. The voltage stored in each of the capacitors in the six capacitor pairs is alternately sent to the buffer 650 through the output of the analog sample and hold module 640. Each switch of the six sets of six switches 790a is connected to a load signal, which activates the switch. The load signal alternates polarity when each new row of digital pixel data is displayed to trigger the operation of the six switches of the second set of switches 790a. Again, each switch in the second set of switches 790a alternates between switch terminals A and B. Additionally, each switch of the second set of switches 790a includes an end terminal G connected to one of the 384 outputs of the analog sample and hold module 640. Each stage outputs six analog voltages to the column electrodes of the display. Since there are 64 stages, there are 384 output signals accordingly.

In operation, the second set of switches 790a is arranged to switch in a direction opposite to the first set of switches 780a, such that each switch of the second set of switches 790a is in a first position. When present, switch terminal B is connected to end terminal G, and switch terminal A is connected to end terminal G when each switch is in the second position. The second set of switches 790a through 790c are alternately switched between terminals A and B to alternately transfer the voltages stored in each of the capacitors to the column electrodes row by row.

Thus, summarizing the operation of the first and second sets of switches 780a and 790a, the first set of switches (if each stage is activated by a Q output from its corresponding flip-flop 710), Each switch of 780a transitions from one position to another to alternately store analog signals a0-a5 in each of the capacitors in the six capacitor pairs. Accordingly, when each switch of the first set of switches 780a transitions to the first position, the first capacitor in each capacitor pair is connected to one of the analog voltage signal lines a0-a5 through terminal C. Connected, the corresponding voltage is stored on the first capacitor via switch terminals C and A. FIG. At the same time, each switch in the second set of switches 790a also transitions to alternately transfer the stored voltages to the buffer 650 to drive the column electrodes. Therefore, using an example as set forth above that describes the operation of the first set of switches 780a, when the first set of switches 780a is in the first position, the second set of switches 790a Each switch of is also in the first position such that the second capacitor of each capacitor pair is connected to the buffer 650 via terminal G such that the voltage previously stored at the second capacitor is applied to switch terminals B and G. Is passed through to the buffer. Therefore, analog voltages from the voltage signal lines a0 to a5 are alternately stored and transmitted so that one capacitor in the pair stores the appropriate voltage level for the next or next row of subpixels while the other The capacitor provides the buffer with the previously stored voltage level for the subpixels of the current row to drive the column electrodes.

Finally, the 384 outputs from each of the six capacitor pairs in the 64 stages of the analog sample and hold module 640 are connected to individual buffers in the buffer module 650. Individual buffers receive analog voltage levels from capacitors through a second set of switches to generate current levels sufficient to drive the column electrodes of the display.

Although the present invention has been described with respect to 6 and 8 bit pixel lengths, it is to be understood that the present invention is not limited to the above, but may be modified to designs having larger or smaller pixel lengths. In addition, although the present invention has been described with respect to a resolution of 1024 pixels by 768 pixels, the present invention is not limited to this display resolution, but is intended to realize future larger scale displays. In this case, additional thermal drivers designed in accordance with the specific details and embodiments described herein can be used. Since all column drivers receive segments of the digital pixel data of the row to be displayed, the number of column drivers and the size of the display can be increased more easily than was possible with prior art drive system designs.

Claims (23)

In a display drive system, A plurality of column drivers; A plurality of dedicated serial buses each coupled to one of the column drivers; And A timing controller coupled to each column driver of the plurality of column drivers, for providing one row of digital pixel data to the plurality of column drivers Including, The digital pixel data is divided into segments and each segment is provided in series to one of the column drivers of the plurality of column drivers via the dedicated serial bus coupled between the timing controller and the column driver. The entire digital pixel data of the is provided to the plurality of column drivers simultaneously, each segment comprising data of two adjacent pixels Display driving system. The device of claim 1, wherein each column driver of the plurality of column drivers receives the serially provided segment of digital pixel data and stores the segment in parallel pixel data until all the pixels in the segment have been received and arranged in parallel. Display drive system comprising a serial-to-parallel converter for rearranging. 3. The digital-to-analog converter of claim 2, wherein each column driver of the plurality of column drivers is coupled to the series-parallel converter, and converts each pixel in the parallel pixel data into analog red, green and blue signals. Display drive system further comprising a module. 4. The digital-to-analog converter module of claim 3, wherein the digital-to-analog converter module converts the parallel pixel data into analog red, green, and blue signals two pixels at a time, so that within the digital-analog converter module, an analog red for a first pixel. A first digital-to-analog converter for generating a signal, a second digital-to-analog converter for generating an analog green signal for the first pixel, a third digital-to-analog converter for generating an analog blue signal for the first pixel, and a first A fourth digital-to-analog converter that generates an analog red signal for two pixels, a fifth digital-to-analog converter that generates an analog green signal for the second pixel, and a sixth for generating an analog blue signal for the second pixel Display drive with six digital-to-analog converters system. 4. The group of pixels of claim 3, wherein each column driver of the plurality of column drivers is coupled to the digital-to-analog converter module to generate the analog red, green, and blue signals for each pixel in the parallel pixel data at one group. A display drive system further comprising an analog sample and hold module for sampling each other. 6. The display drive system of claim 5, wherein the analog sample and hold module samples the analog red, green, and blue signals of each pixel in the parallel pixel data two pixels at a time such that all six analog signals are sampled simultaneously. 6. The display drive system of claim 5, wherein the analog sample and hold module comprises a plurality of first capacitors, wherein one first capacitor samples each red, green and blue signal for each pixel in the pixel group. 6. The method of claim 5, wherein the analog sample and hold circuit comprises a plurality of first and second capacitor pairs, each first capacitor for each pixel in a group of pixels from parallel pixel data for a first display row. And sample the red, green, and blue signals, each second capacitor sampling the analog red, green, and blue signals for each pixel in a group of pixels from parallel pixel data in a next display row. 9. The method of claim 8, wherein each first capacitor provides the sampled analog red, green, and blue signals to a plurality of column electrodes, each second capacitor being within a group of pixels from parallel pixel data in the next display row. A display drive system that samples the analog red, green, and blue signals for each pixel. In a system for driving a display, A plurality of separate bus lines; Coupled to each of the plurality of separate bus lines to receive digital pixel data, divide the digital pixel data into a plurality of segments of digital pixel data, and simultaneously provide the plurality of segments in series to a plurality of column drivers. A timing controller for; And A plurality of column drivers each coupled to the timing controller via one bus line of the separate bus lines Including, Each segment contains data of two adjacent pixels, each column driver receiving a particular segment in the plurality of segments via the separate bus lines, and each column driver being in series with the digital pixel data. Converts the provided segment into parallel digital pixel data, converts the parallel digital pixel data into analog signals, and provides the analog signals to a plurality of column electrodes for driving the display.  Display driving system. The method of claim 10, wherein the timing controller, A first and second pair of memory modules for receiving and storing the digital pixel data, wherein a first row of digital pixel data is stored in the first memory module and a second row of digital pixel data is stored in the second memory module. First and second memory module pairs stored; Coupled to the first and second memory module pairs to route the first row of digital pixel data to the first memory module and to route the second row of digital pixel data to the second memory module. Data path control circuitry; And Coupled to the first and second memory module pairs, retrieving the first row of digital pixel data from the first memory module in a parallel format, dividing the digital pixel data into a plurality of segments, and parallelizing each segment A parallel-to-serial converter for converting from a format to a serial format and providing each segment of the plurality of segments to a corresponding column driver of the plurality of column drivers via the separate bus line. Display driving system comprising a. 12. The device of claim 11, wherein an enable signal is coupled between the timing controller and each column driver of the plurality of column drivers to activate each column driver such that the plurality of column drivers are in their respective segments. Display drive system to allow simultaneous reception. The method of claim 10, wherein each column driver of the plurality of column drivers, A serial-to-parallel converter for receiving said segment of serially formatted digital pixel data over said separate bus line and converting said segment into a parallel format one pixel at a time; A digital-to-analog converter coupled to the serial-to-parallel converter for converting each pixel in the parallel formatted segment of digital pixel data into analog red, green and blue signals; And Coupled between the digital-to-analog converter and the plurality of column electrodes to sample the analog red, green, and blue signals of each pixel, store the sampled analog red, green, and blue signals, and drive the display. An analog sample and hold module for releasing said samples of said analog red, green and blue signals to said plurality of column electrodes Display driving system comprising a. The digital-to-analog converter module of claim 13, wherein the digital-to-analog converter module converts each pixel in the parallel formatted segment of digital pixel data into analog red, green, and blue signals, two pixels at a time, into the digital-to-analog converter module. A first digital-to-analog converter for generating an analog red signal for the first pixel, a second digital-to-analog converter for generating an analog green signal for the first pixel, and a second for generating an analog blue signal for the first pixel 3 digital-to-analog converter, fourth digital-to-analog converter for generating an analog red signal for a second pixel, fifth digital-to-analog converter for generating an analog green signal for the second pixel, and analog for the second pixel At least six digital, sixth digital-to-analog converters that generate a blue signal Display drive system with analogue transducer. The display drive system of claim 13, wherein the analog sample and hold module samples the analog red, green, and blue signals of each pixel two pixels at a time such that all six analog signals are sampled simultaneously. 14. The method of claim 13, wherein the analog sample and hold module comprises a plurality of sample and hold capacitor pairs having a first capacitor and a second capacitor, wherein the first capacitor and the second capacitor in each analog sample and hold module. And alternately store and emit the samples of the analog red, green and blue signals. As a timing controller for controlling the display through a plurality of separate bus lines, a plurality of column drivers, each coupled to a timing controller, via a corresponding separate bus line of the plurality of separate bus lines, for driving the display. , A first and second pair of memory modules for receiving and storing digital pixel data, wherein a first row of digital pixel data is stored in the first memory module and a second row of digital pixel data is stored in the second memory module. First and second memory module pairs stored; And Retrieve the first row of digital pixel data from the first memory module in parallel format, divide the digital pixel data into segments, convert each segment from parallel format to serial format, and convert the serially formatted Parallel-to-serial converter for simultaneously providing each segment of the first row of digital pixel data to a corresponding column driver of the plurality of column drivers via the corresponding separate bus line Including, A timing controller in which each segment is data of two adjacent pixels. In the column driver for driving a plurality of column electrodes of the display, A serial-to-parallel converter for serially receiving digital pixel data representing segments of a display row and converting the digital pixel data into a parallel format; A digital-to-analog converter coupled to the serial-to-parallel converter for receiving the parallel formatted digital pixel data and converting the parallel formatted digital pixel data into analog signals; And Analog sample and hold circuit for sampling the analog signals, storing the samples, and providing the samples of the analog signals to a plurality of column electrodes to drive the display Including, The analog sample and hold circuit includes a column driver having a plurality of capacitor pairs having a first capacitor and a second capacitor such that each capacitor alternately stores the analog signal samples and provides the samples to the column electrodes. . delete In a method for driving a display, Receiving a current row of digital pixel data and storing the current row of digital pixel data in a first memory module; Retrieve the current row of digital pixel data from the first memory module in a parallel format, divide the current row of digital pixel data into a plurality of current row segments, and each current row segment into a current row Converting to a serial data stream; Providing each current row serial data stream to a corresponding column driver of the plurality of column drivers; Receiving each current row serial data stream at the corresponding column driver and converting the current row serial data stream one pixel at a time into current row parallel digital data; Converting the current row parallel digital data into current row analog red, green, and blue signals, two adjacent pixels at a time; And Sampling the current row analog red, green, and blue signals to hold the samples; And Providing the samples to a plurality of column electrodes to drive a display Including, Wherein each current row serial data stream is provided to a corresponding column driver via a dedicated bus line. 21. The method of claim 20, further comprising: receiving a next row of digital pixel data and storing the next row of digital pixel data in a second memory module and performing the step of retrieving the current row of digital pixel data from the first memory module. Performing while retrieving and providing each current row serial data stream; Retrieving the next row of digital pixel data in parallel from the second memory module, dividing the next row of digital pixel data into a plurality of next row segments, and converting each next row segment into a next row serial data stream. step; And Providing each next row serial data stream to a corresponding column driver of the plurality of column drivers. More, Wherein each next row serial data stream is provided to a corresponding column driver via a dedicated bus line. 23. The method of claim 21, further comprising: receiving each next row serial data stream at the corresponding column driver and converting the next row serial data stream one pixel at a time into parallel digital data; Converting the parallel digital data into analog red, green and blue signals two adjacent pixels at a time; Sampling the analog red, green, and blue signals and holding the samples; And Providing the samples to the plurality of column electrodes to drive the display Display driving method further comprising. delete

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