KR100606408B1 - Apparatus for Taking Image - Google Patents

Abstract

SUMMARY OF THE INVENTION The present invention relates to an image photographing apparatus suitable for suppressing generation of EMI and suppressing degradation of a video signal.

The imaging apparatus includes at least two sensing array panels in which a plurality of photo sensing cells are arranged in a matrix, a digitizer for formatting pixel signals from at least two sensing array panels in the form of a video signal, and at least two sensing array panels. And at least two read drivers for sequentially transmitting at least two pixel signals to the digitizer sequentially.

Description

Apparatus for Taking Image

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an image photographing apparatus for photographing an image of a subject and providing an electrical video signal, and more particularly, to an image photographing apparatus for generating a video signal for an image of a subject using non-visible light.

In general, an image photographing apparatus using infrared rays and / or X-rays, etc., rather than visible light is used in the medical, scientific, and industrial fields. Examples of the image photographing apparatus include an X-ray photographing apparatus and a fingerprint body. Such an image photographing apparatus uses a photo-sensing array panel that converts X-rays or infrared rays that pass through or are reflected by the subject into electrical signals. Photo-sensing array panels tend to have as many pixels as possible to meet the needs of users for large size and high resolution. In addition, an image capturing apparatus employs a data collection circuit that collects electrical signals from a photo-sensitive array panel and formats them into a video signal. The data acquisition circuit must input electrical signals from the photo-sensing array panel within a certain time to prevent degradation of the video signal. Furthermore, data collection circuits are required to provide video signals for moving images as well as still images. Accordingly, data acquisition circuitry is required to input electrical signals from photo-sensing array panels at higher speeds. Accordingly, the data acquisition circuit must input electrical signals from the photo-sensitive array substrate at a faster rate. To this end, the data acquisition circuit is forced to operate at a high speed. High speed operation of such data collection circuits causes severe electromagnetic-electromagnetic interference. In addition, in the data acquisition circuit, the wiring becomes long, resulting in inconsistent timing.

In practice, the image pickup device has a gate driver 12 and a read driver 14 connected to the sensing array panel 10 as in FIG. In the sensing array panel 10, a plurality of sensing cells SC are arranged in a matrix form. Each of the plurality of sensing cells includes a photo sensor PS and a charging capacitor CC connected between the panel voltage line PVL and the base voltage line GVL, and a voltage signal charged in the charging capacitor CC. It consists of a thin film transistor (TMT) for selectively transferring to the (ABL) side. At this time, the gate terminal of the TFT (TMC) is connected to the gate driver 12 through the gate bus line GBL. The gate driver 12 sequentially drives the gate bus lines GBL on the sensing array panel 10 so that the pixel signals sensed by the plurality of sensing cells SC on the sensing array panel 10 are read out one line at a time. To the driver 14. The read driver 14 inputs one line of correlation pixel signals in parallel from the analog bus lines ABL on the sensing array panel 10 and supplies them in series to the digitizer 16. The correlation pixel signal includes a sensing pixel signal SPS and a reference pixel signal RPS. The sensing pixel signal SPS has a voltage charged to the charging capacitor CC by the photosensor PS, while the reference pixel signal RPS is an analog bus line ABL when the charging capacitor CC is initialized. Has a voltage on The digitizer 16 generates a pixel signal by differentially amplifying each of the correlated pixel signals inputted from the read driver 14 in series and generates a video signal by formatting the pixel signals. At this time, the gate driver 12, the read driver 14 and the digitizer 16 are controlled by the timing control signal from the timing controller 18.

The read driver 14 also has a switch cell array 24 connected between the correlated double sampling cell array 20 and the shift register 22 as shown in FIG. The correlated double sampling cell array 20 is composed of n correlated double sampling cells CDSC1 to CDSCn connected to the n analog bus lines ABL1 to ABLn on the sense array panel 10 of FIG. Each of these correlated double sampling cells CDSC1 to CDSCn samples the sensing pixel signal SPS by sampling / holding the voltage Vd on the analog bus line ABL by the first sampling clock SHC1. In addition, each of the correlated double sampling cells CDSC1 to CDSCn samples the reference pixel signal RPS by sampling / holding the voltage Vd on the analog bus line ABL by the second sampling clock SHC2. In addition, the sensed pixel signals SPS and the reference pixel signal RPS sampled by the correlated double sampling cells CDSC1 to CDSCn are supplied to the switch cell array 24. The shift register 22 has n shift cells SR1 to SRn connected in series. Each of these shift cells SR1 to SRn sequentially moves the carry signal CCS toward the right shift cell SR in response to the shift clock DSHC and the inverted shift clock DSHCB as shown in FIG. 3. Let's go. By the operation of these shift cells SR1 to SRn, the shift register 22 generates n switch control signals having a high level or a low level sequentially. The switch cell array 24 includes n switch cells STC1 to STCn respectively corresponding to n switch control signals. Each of these n switch cells STC1 to STCn has a sensing pixel signal SPS and a reference pixel signal from the correlated double sampling cell CDSC when the switch control signal from the shift cell SR has a high level or a low level. (RPS) is sent to the digitizer 16 of FIG. To this end, each of the n switch cells STC1 to STCn is composed of first and second switch transistors MN1 and MN2 that commonly respond to a switch control signal from the shift cell SR. The first switch transistor MN1 transmits the sensed pixel signal SPS from the correlated double sampling cell CSC and the second switch transistor MN2 transmits the reference pixel signal RPS toward the digitizer 16 of FIG. do.

In the image capturing apparatus configured as described above, as the sensing cells SC on the sensing array panel 10 are increased, the frequency of the shift clock DSHC is increased and the switching cycle of the switch cells is faster. For this reason, in the conventional image pickup device, EMI was inevitably severe. In addition, in the conventional image photographing apparatus, since the wires for transmitting the shift clock DSHC and the pixel signal are lengthened, the shift clocks DSHC and DSHCB are degraded as shown in FIG. 3. For this reason, the switching point of the correlated pixel signal is delayed from the left analog bus line to the right analog bus line. As a result, the video signal generated by the digitizer 16 deteriorates.

Accordingly, an object of the present invention is to provide an image photographing apparatus suitable for suppressing generation of EMI and suppressing degradation of a video signal.

In order to achieve the above object, the image photographing apparatus according to the present invention comprises at least two or more sensing array panels in which a plurality of light sensing cells are arranged in a matrix form, and pixel signals from at least two or more sensing array panels in the form of video signals. Formatting means for formatting and at least two reading means for sequentially transferring pixel signals from at least two sensing array panels to the formatting means one by two or more.

An image capturing apparatus according to the present invention includes at least two or more sensing array panels in which a plurality of photo sensing cells are arranged in a matrix form, and at least two or more formatting means for formatting pixel signals from at least two or more sensing array panels in the form of a video signal. And at least two or more reading means for sequentially transmitting at least two or more pixel signals from at least two or more sensing array panels toward at least two or more formatting means.

Other objects and advantages of the present invention other than the above objects will become apparent from the detailed description of the embodiments with reference to the accompanying drawings.

Hereinafter, an embodiment of the present invention will be described in detail with reference to FIGS. 4 to 11.

4 schematically shows an image photographing apparatus according to an embodiment of the present invention. 4 includes a first gate driver 12A and a first read driver 30A connected to the first sensing array panel 10A, and a second gate driver connected to the second sensing array panel 10B. 12B and the second read driver 30B. Each of the first and second sensing array panels 10A and 10B has a plurality of sensing cells SC arranged in a matrix. Each of the plurality of sensing cells includes a photo sensor PS and a charging capacitor CC connected between the panel voltage line PVL and the base voltage line GVL, and a voltage signal charged in the charging capacitor CC. It consists of a TFT (TMC) for selectively transferring towards (ABL). The gate terminal of the TFT (TMC) is connected to the gate driver 12A or 12B through the gate bus line GBL. The first gate driver 12A sequentially drives the gate bus lines GBL on the first sensing array panel 10A so that the pixels sensed by the plurality of sensing cells SC on the first sensing array panel 10A. The signals are supplied to the first read driver 30A line by line. The pixel sensed by the plurality of sensing cells SC on the second sensing array panel 10B by sequentially driving the gate bus lines GBL on the second sensing array panel 10B is also the second gate driver 12B. The signals are supplied to the second read driver 30B line by line. The first read driver 30A inputs one line of correlated pixel signals in parallel from the analog bus lines ABL on the first sensing array panel 10A and supplies them to the digitizer 16 in series of three. Done. The second read driver 30B also inputs one line of correlated pixel signals in parallel from the analog bus lines ABL on the second sensing array panel 10B and supplies them to the digitizer 16 in series of three. Done. These first and second read drivers 30A and 30B are driven sequentially in each horizontal read period. In other words, after the first read driver 30A completes the transfer operation of the correlation pixel signal, the second read driver 30B starts the transfer operation of the correlation pixel signal. Further, the correlated pixel signals output from these first and second read drivers 30A and 30B include the sensed pixel signal SPS and the reference pixel signal RPS. The sensing pixel signal SPS has a voltage charged to the charging capacitor CC by the photosensor PS, while the reference pixel signal RPS is an analog bus line ABL when the charging capacitor CC is initialized. Has a voltage on The digitizer 16 generates a pixel signal by differentially amplifying each of the correlated pixel signals inputted in series from the first and second read drivers 30A and 30B, and generates a pixel signal, and formats the video signals. Will occur. The first and second gate drivers 12A and 12B, the first and second read drivers 30A and 30B and the digitizer 16 are controlled by timing control signals from a timing controller 18.

Thus, the pixel signals from the sensing array panels 10A and 10B are transmitted in series of three to three times by the read drivers 30A and 30B toward the digitizer 16. In addition to being transmitted, the read drivers 30A and 30B are driven at a low speed. As a result, in the image photographing apparatus according to the embodiment of the present invention, generation of EMI is suppressed. In addition, in the image capturing apparatus according to an exemplary embodiment of the present invention, the screen is divided by the sensing array panels 10A and 10B, the read drivers 30A and 30B, and the gate drivers 12A and 12B so that the wiring is shortened. do. Accordingly, in the image capturing apparatus according to the embodiment of the present invention, deterioration of the video signal is suppressed.

FIG. 5 is a detailed block diagram showing in detail the first and second read drivers 30A, 30B of FIG. In Fig. 5, the read drivers 30A and 30B have a switch cell array 44 connected between the correlated double sampling cell array 40 and the first to third shift registers 42A to 42C. The correlated double sampling cell array 40 is composed of n correlated double sampling cells CDSC1 to CDSCn respectively connected to the n analog bus lines ABL1 to ABLn on the sense array panel 10A or 10B of FIG. . Each of these correlated double sampling cells CDSC1 to CDSCn samples the sensing pixel signal SPS by sampling / holding the voltage Vd on the analog bus line ABL by the first sampling clock SHC1. In addition, each of the correlated double sampling cells CDSC1 to CDSCn samples the reference pixel signal RPS by sampling / holding the voltage Vd on the analog bus line ABL by the second sampling clock SHC2. In addition, the sensed pixel signals SPS and the reference pixel signal RPS sampled by the correlated double sampling cells CDSC1 to CDSCn are supplied to the switch cell array 44. The first shift register 42A has n / 3 shift cells SR1 to SRn / 3 connected in series. Each of these shift cells SR1 to SRn / 3 sequentially carries a carry signal CSS in response to the shift clock DSHC and the inverted shift clock DSHCB as shown in FIG. 6. Will be moved to the side. By the operation of these shift cells SR1 to SRn / 3, n / 3 switch control signals having a high level or a low level are sequentially generated in the first shift register 42A. The n / 3 switch control signals generated in the first shift register 42A are the 3i + 1 th (i is 0 to n / 3-1) switch cells included in the switch cell array 44. STC1, STC4,... And SCTn-2). The second and third shift registers 42B and 42C are also configured in the same manner as the first shift register 42A, and the shift clock DSHC and the inverted shift clock DSHCB are the same as the first shift register 42A. Will respond. As a result, each of the second and third shift registers 42B and 42C generates n / 3 switch control signals having the same waveform as the n / 3 switch control signals output from the first shift register 42A. . The n / 3 switch control signals generated in the second shift register 42B are included in the switch cell array 44 and the 3i + 2 th (i is 0 to n / 3-1) switch cells STC2, STC5,... N / 3 switch control signals generated from the third shift register 42C are supplied to the SCTn-1, respectively, and the 3i th (i is 1 to n / 3) switches included in the switch cell array 44. Cells STC3, STC6, ..., STCn are respectively supplied. The n switch cells STC1 to STCn included in the switch cell array 44 are connected to the first to third shift registers 42A, 42B, and 42C in a divided manner so that the three correlation pixel signals are sequentially directed toward the digitizer 16. Will be sent. In detail, the first to third switch cells transmit the correlated pixel signals from the first to third correlated double sampling cells CDSC1 to CDSC3 through the first to sixth data bus lines DBL1 to DBL6. 16) will be sent to. Subsequently, the fourth to sixth switch cells STC4 to STC6 receive the correlated pixel signals from the fourth to sixth correlated double sampling cells CDSC4 to CDSC6 to the first to sixth data bus lines DBL1 to DBL6. To the digitizer 16. In addition, each of the n switch cells STC1 to STCn has a sensing pixel signal SPS and a reference pixel signal RPS from the correlated double sampling cell CDSC when the switch control signal from the shift cell has a high level or a low level. To the digitizer 16 of FIG. To this end, each of the n switch cells STC1 to STCn is composed of first and second switch transistors MN1 and MN2 that commonly respond to a switch control signal from the shift cell SR. The first switch transistor MN1 transmits the sensed pixel signal SPS from the correlated double sampling cell CDSC and the second switch transistor MN2 transmits the reference pixel signal RPS toward the digitizer 16 of FIG. do. In this way, the n switch cells STC1 to STCn included in the switch cell array 44 sequentially perform the transmission of the correlated pixel signals by three, so that each of the odd data bus lines DBL1, DBL3, and DBL5 is provided. The first to third sensing pixel signal sequences SP1 to SP3 as shown in FIG. 6 and each of the even-numbered data bus lines DBL2, DBL4 and DBL6 have first to third reference pixel signal sequences as shown in FIG. (RPS1, RPS2, RPS3) will appear respectively.

7 schematically illustrates an image capturing apparatus according to another embodiment of the present invention. The image capturing apparatus of FIG. 7 includes a gate driver 12 connected to the first and second sensing array panels 10A and 10B, and a first connection connected to each of the first and second sensing array panels 10A and 10B. And first and second read drivers 30A, 30B. Each of the first and second sensing array panels 10A and 10B has a plurality of sensing cells SC arranged in a matrix. Each of the plurality of sensing cells includes a photo sensor PS and a charging capacitor CC connected between the panel voltage line PVL and the base voltage line GVL, and a voltage signal charged in the charging capacitor CC. It consists of a TFT (TMC) for selectively transferring towards the line ABL. The gate terminal of the TFT TMC is connected to the gate driver 12 through the gate bus line GBL. The gate driver 12 sequentially drives the gate bus lines GBL on the first sensing array panel 10A so that the pixel signals sensed by the plurality of sensing cells SC on the first sensing array panel 10A may be driven. Line by line is supplied to the first read driver 30A. At the same time, the gate driver 12 sequentially drives the gate bus lines GBL on the second sensing array panel 10B to be sensed by the plurality of sensing cells SC on the second sensing array panel 10B. The pixel signals are supplied to the second read driver 30B one line at a time. The first read driver 30A inputs one line of correlated pixel signals in parallel from the analog bus lines ABL on the first sensing array panel 10A and supplies them in series three to the first digitizer 16A. do. The second read driver 30B also inputs one line of correlated pixel signals in parallel from the analog bus lines ABL on the second sense array panel 10B to the second digitizer 16B in series of three. do. Further, the correlated pixel signals output from these first and second read drivers 30A and 30B include the sensed pixel signal SPS and the reference pixel signal RPS. The sensing pixel signal SPS has a voltage charged to the charging capacitor CC by the photosensor PS, while the reference pixel signal RPS is an analog bus line ABL when the charging capacitor CC is initialized. Has a voltage on The first digitizer 16A differentially and amplifies each of the correlated pixel signals inputted in series from the first read driver 30A three by three to generate a pixel signal and to format the pixel signals to generate the first video signal. Done. Similarly, the second digitizer 16B also differentially and amplifies each of the correlated pixel signals inputted in series from the second read driver 30B three by three to generate a pixel signal and format the pixel signals so as to form the second video. Will generate a signal. The gate driver 12, the first and second read drivers 30A and 30B, and the first and second digitizers 16A and 16B are controlled by timing control signals from the timing controller 18.

In addition, the image photographing apparatus of FIG. 7 has a first and second delayers for delaying the signals such that the timing control signals to be supplied from the timing controller 18 toward the first and second read drivers 30A, 30B are synchronized with each other. 32A, 32B) is further provided. The periods in which each of these first and second delayers 32A and 32B delay the timing control signal are set differently. The difference in the delay time is determined by the length of the wiring connecting the timing controller 18 and the first read driver 30A and the length and the difference in the wiring connecting the timing controller 18 and the second read driver 30B. do. In addition, the timing control signals supplied to these first and second delayers 32A and 32B include a shift clock DSHC, an inverted shift clock DSHCB, and first and second sampling clocks. In order to delay these timing control signals, each of the first and second delayers 32A and 32B includes delay cells corresponding to the number of timing control signals.

FIG. 8 illustrates an embodiment of a delay cell included in the first and second delayers 32A and 32B of FIG. The delay cell of FIG. 8 is composed of an R-C integrator 50 and an AND gate 52 that are cascaded to the input line IL. The R-C integrator 50 is composed of one resistor R1 and one capacitor C1. The R-C integrator 50 integrates the timing control signal IT as shown in FIG. 9 input to the input line IL and supplies the integrated timing control signal IGS to the AND gate 52. The AND gate 52 performs a delayed timing as shown in FIG. 9, which is delayed by an RC time constant than the timing control signal IT on the input line IL by ANDing the integrated timing control signal IGS with the supply voltage VCC. The control signal OT is supplied to the first or second read drivers 30A and 30B through the output line OL.

FIG. 10 illustrates in detail another embodiment of the delay cells included in the first and second delayers 32A and 32B of FIG. The delay cell of FIG. 10 is composed of an R-C integrator 50 and an OR gate 54 which are cascaded to the input line IL. The R-C integrator 50 is composed of one resistor R1 and one capacitor C1. The R-C integrator 50 integrates the timing control signal IT as shown in FIG. 9 input to the input line IL and supplies the integrated timing control signal IGS to the OR gate 54. The OR gate 54 performs a delayed timing as shown in FIG. 9, which is delayed by an RC time constant than the timing control signal IT on the input line IL by ORing the integrated timing control signal IGS with the base voltage GND. The control signal OT is supplied to the first or second read drivers 30A and 30B through the output line OL.

11 schematically illustrates an image capturing apparatus according to another embodiment of the present invention. The image capturing apparatus of FIG. 11 is connected to the first gate driver 12A connected to the first and third sensing array panels 10A and 10C, and to the second and fourth sensing array panels 10B and 10D. The second gate driver 12B is provided. In addition, the image photographing apparatus of FIG. 11 includes first to fourth read drivers 30A to 30D connected to each of the first to fourth sensing array panels 10A to 10D. In each of the first to fourth sensing array panels 10A to 10D, a plurality of sensing cells SC are arranged in a matrix form. Each of the plurality of sensing cells SC receives a photo sensor PS and a charging capacitor CC connected between the panel voltage line PVL and the base voltage line GVL, and a voltage signal charged in the charging capacitor CC. It consists of a TFT (TMC) for selectively transferring toward the analog bus line ABL. The gate terminal of the TFT (TMC) is connected to the gate driver 12A or 12B through the gate bus line GBL. The first gate driver 12A sequentially drives the gate bus lines GBL on the first sensing array panel 10A so that the pixels sensed by the plurality of sensing cells SC on the first sensing array panel 10A. The signals are supplied to the first read driver 30A line by line. At the same time, the first gate driver 12A is driven by the plurality of sense cells SC on the third sensing array panel 10C by sequentially driving the gate bus lines GBL on the third sensing array panel 10C. The sensed pixel signals are supplied to the third read driver 30C line by line. Meanwhile, the second gate driver 12B is also sensed by the plurality of sensing cells SC on the second sensing array panel 10B by sequentially driving the gate bus lines GBL on the second sensing array panel 10B. Pixel signals are supplied to the second read driver 30B line by line. At the same time, the second gate driver 12B is driven by the plurality of sensing cells SC on the fourth sensing array panel 10D by sequentially driving the gate bus lines GBL on the fourth sensing array panel 10D. The sensed pixel signals are supplied to the fourth read driver 30D line by line. The first read driver 30A inputs one line of correlated pixel signals in parallel from the analog bus lines ABL on the first sensing array panel 10A and supplies them in series three to the first digitizer 16A. do. The second read driver 30B also inputs one line of correlated pixel signals in parallel from the analog bus lines ABL on the second sense array panel 10B and supplies them in series three to the first digitizer 16A. do. These first and second read drivers 30A and 30B are driven sequentially in each horizontal read period. In other words, after the first read driver 30A completes the transfer operation of the correlation pixel signal, the second read driver 30B starts the transfer operation of the correlation pixel signal. Similarly, the third read driver 30C inputs one line of correlated pixel signals in parallel from the analog bus lines ABL on the third sensing array panel 10C to the second digitizer 16B in series of three. Will be supplied. The fourth read driver 30D also inputs one line of correlated pixel signals from the analog bus lines ABL on the fourth sensing array panel 10D in parallel and supplies them in series three to the second digitizer 16B. do. These third and fourth read drivers 30C and 30D are driven sequentially in each horizontal read period. In other words, after the third read driver 30C completes the transfer operation of the correlation pixel signal, the fourth read driver 30D starts the transfer operation of the correlation pixel signal. In addition, the correlated pixel signals output from the first to fourth read drivers 30A to 30D include the sensed pixel signal SPS and the reference pixel signal RPS. The sensing pixel signal SPS has a voltage charged to the charging capacitor CC by the photosensor PS, while the reference pixel signal RPS is an analog bus line ABL when the charging capacitor CC is initialized. Has a voltage on The first digitizer 16A differentially and amplifies each of the correlated pixel signals inputted in series from each of the first and second read drivers 30A and 30B to generate a pixel signal and to format the pixel signals. 1 Video signal is generated. Similarly, the second digitizer 16B differentially amplifies each of the correlated pixel signals inputted in series from the third and fourth read drivers 30C and 30D to generate pixel signals and formats the pixel signals. As a result, a second video signal is generated. The first and second gate drivers 12A and 12B, the first to fourth read drivers 30A to 30D, and the first and second digitizers 16A and 16B are timing from a timing controller 18. Controlled by a control signal.

In addition, the image capturing apparatus of FIG. 11 includes a first delayer 32A for delaying timing control signals to be supplied from the timing controller 18 toward the first and second read drivers 30A, 30B, and the timing controller 18. And a second delay 32B for delaying timing control signals to be supplied to the third and fourth read drivers 30C, 30D. These first and second delayers 32A and 32B are the timing control signals to be supplied from the timing controller 18 to the first and second read drivers 30A and 30B and the third and the third from the timing controller 18. The timing control signals to be supplied to the four read drivers 30C and 30D are delayed so that they are synchronized with each other. The periods in which each of these first and second delayers 32A and 32B delay the timing control signal are set differently. The difference in the delay time is the length of the wiring connecting the timing controller 18 and the first and second read drivers 30A and 30B, and the timing controller 18 and the third and fourth read drivers 30C and 30D. It depends on the length and difference of wiring. In addition, the timing control signals supplied to these first and second delayers 32A and 32B include a shift clock DSHC, an inverted shift clock DSHCB, and first and second sampling clocks. In order to delay these timing control signals, each of the first and second delayers 32A and 32B includes delay cells corresponding to the number of timing control signals.

As such, the pixel signals from the sensing array panels 10A to 10D are transmitted in series to the digitizers 16A and 16B three by three by the read drivers 30A to 30D. The read driver 30A, 30B is driven at a low speed while being transmitted in a shortened period of time. As a result, in the image photographing apparatus according to the embodiment of the present invention, generation of EMI is suppressed. In addition, in the image capturing apparatus according to the embodiment of the present invention, the screen is divided by the sensing array panels 10A to 10D, the read drivers 30A to 30D, and the gate drivers 12A and 12B so that the wiring is shortened. do. Accordingly, in the image capturing apparatus according to the embodiment of the present invention, deterioration of the video signal is suppressed.

As described above, in the image photographing apparatus according to the present invention, the pixel signals from the sensing array panel are transmitted in 1/3 of the periods in the conventional image photographing apparatus by transmitting the pixel signals three by three toward the digitizer in series. In addition, the read driver is driven at a low speed. As a result, in the image photographing apparatus according to the embodiment of the present invention, generation of EMI is suppressed. In addition, in the image capturing apparatus according to an exemplary embodiment of the present invention, the screen is divided by the sensing array panels, the read drivers, and the gate drivers, thereby shortening the wiring. Accordingly, in the image capturing apparatus according to the embodiment of the present invention, deterioration of the video signal is suppressed.

As described above, although the image photographing apparatus has been described as an embodiment of the present invention, those skilled in the art can implement the present invention in other forms by changing and modifying it without departing from the technical spirit of the present invention. You can see that. Therefore, the technical scope of the present invention should not be limited to the contents described in the embodiments, but should be defined by the claims.

1 is a diagram schematically showing a conventional image photographing apparatus.

Fig. 2 shows details of the read driver of Fig. 1;

3 is an operation timing diagram for each part of the read driver shown in FIG.

4 is a diagram schematically showing an image photographing apparatus according to an embodiment of the present invention;

FIG. 5 shows details of the read driver of FIG. 4; FIG.

Fig. 6 is an operation timing diagram for each part of the read driver shown in Fig. 5;

7 is a view schematically showing an image pickup device according to another embodiment of the present invention.

FIG. 8 illustrates an embodiment of a delay cell included in the delay unit of FIG. 7 in detail. FIG.

Fig. 9 is an operation timing diagram for each part of the delay cell shown in Fig. 8;

FIG. 10 illustrates in detail another embodiment of a delay cell included in the delay unit of FIG.

Fig. 11 is a view schematically showing an image pickup device according to another embodiment of the present invention.

<Description of Symbols for Major Parts of Drawings>

10,10A to 10D: Detection Array Panel 12,12A, 12B: Gate Driver

14,30A to 30D: Read driver 16,16A, 16B: Digitizer

18: timing controller

20,40: Correlated Double Sampling Cell Array

22,42A, 42B, 42C: Shift Register

24,44: switch cell array 32A, 32B: delay

Claims (4)

At least two sensing array panels in which a plurality of photosensitive cells are arranged in a matrix; Formatting means for formatting the pixel signals from the at least two sensing array panels in the form of a video signal; At least two reading means for receiving one line of pixel signals in parallel from the two or more sensing array panels and sequentially transmitting the pixel signals to the formatting means in series of at least three or more; , Each of the plurality of sensing cells arranged on the plurality of lines of the sensing array panel, A photo sensor (PS) connected between the panel voltage line (PVL) and the ground voltage line (GVL), for detecting infrared rays or X-rays and converting them into electrical signals; A charging capacitor (CC) connected in parallel with the photo sensor (PS); A thin film transistor for receiving a voltage signal charged in the charging capacitor as a source signal by a gate terminal connected to a gate driver through a gate bus line (GBL), and selectively transferring the voltage signal to the reading means, The gate driver sequentially drives gate bus lines connected to a plurality of sensing cells arranged on one line by one line, and transmits pixel signals sensed by the sensing cells to the reading unit by one line. Image taking device. The method of claim 1, And at least two reading means each sequentially perform a pixel signal transfer operation. At least two sensing array panels in which a plurality of photosensitive cells are arranged in a matrix; At least two formatting means for formatting the pixel signals from the at least two sensing array panels in the form of a video signal; At least two reading means for receiving one line of pixel signals in parallel from the two or more sensing array panels and transmitting the pixel signals to the at least two formatting means in series at least three or more in series; Characterized in that the image photographing apparatus. The method of claim 3, wherein And the at least two or more reading means each perform a pixel signal transfer operation at the same time.