KR100606362B1 - Apparatus and method for reset control of processor - Google Patents

Abstract

The present invention is to provide a reset control device and a method of the processor, a first processor; A second processor for outputting a BR signal to the first processor; A controller configured to control the first processor and the second processor by using a software watchdog reset signal output from the first processor; The controller receives LED signals from the controller and emits the LEDs, and the monitoring signals are referred to by the controller for the normal operation of the processor used in the mobile communication system. The internal software watchdog reset signal can be used to control the reset operation for abnormal conditions of the processor.

Description

Apparatus and method for reset control of processor

1 is a block diagram of a reset control apparatus of a conventional processor,

2 is a flowchart illustrating a reset control method of a conventional processor.

3 is a monitoring timing diagram in FIG. 1,

4 is a block diagram of a reset control device of a processor according to the present invention;

5 is a flowchart illustrating a reset control method of a processor according to the present invention;

6 is a monitoring timing diagram of FIG. 4.

Explanation of symbols on the main parts of the drawings

10: first processor (MPC8260) 20: second processor (MPC750)

30: PLD 40: LED

50: FPGA 50: EEPROM

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a reset control device of a processor and a method thereof, and more particularly, to a configuration of a field programmable gate array (FPGA) as a monitoring signal referred to by a controller for normal operation of a processor used in a mobile communication system. A reset control device of a processor suitable for controlling a reset operation for an abnormal state of a processor by using a Done signal indicating completion and an internal software watchdog reset signal generated by the processor itself, and It is about a method.

In general, a mobile communication system is a communication system that targets mobile devices such as people, cars, ships, trains, and airplanes, which includes key phone systems, mobile phones (mobile phones, vehicle phones), port phones, aircraft phones, and mobile phones. Trains, cruise ships, express buses), radio calling, radiotelephony, satellite mobile communication, amateur radio, and fishing service ships.

The mobile communication system includes an AMPS (Advanced Mobile Phone Service) system using an analog method, a Code Division Multiple Access (CDMA) system using a digital method, a Wideband Code Division Multiple Access (WCDMA), and a TDMA (Time). Division Multiple Access, Time Division Multiple Access (FDMA) system, Frequency Division Multiple Access (FDMA) system, Wireless Local Loop (WLL), CDMA2000-1x, IMT-2000 (International Mobile Telecommunication in the year 2000 , Global mobile communication (GSM) systems, and GSM (Global System for Mobile communication) systems.

In such a mobile communication system, a processor is used to perform various functions. The processor uses a main processor controller (MPC) 8260 and an MPC760.

1 is a block diagram of a reset control apparatus of a conventional processor.

As shown therein, a first processor (MPC8260) 1; A second processor (MPC750) (2) for outputting a BR (Bus Request) signal to the first processor (1); A controller configured to control the reset operation of the first processor 1 and the second processor 2 by outputting the reset signals RESET_8260 and RESET_750 to the first processor 1 and the second processor 2; 3) and; The control unit 3 is configured to receive a light emitting diode (LED) signal and to emit light.

The MPC8260 is a processor developed by Motorola for high-speed networking technologies such as Asynchronous Transfer Mode (ATM), Fast Ethernet, and Digital Subscriber Line (DSL). Includes features

155 Mbps ATM SAR (up to 2)

10/100 Mbps Ethernet (up to 3)

-45 Mbps HDLC / Transparent (up to 3)

-256 HDLC channels over 1-8 TDM lines

The MPC750 is also a high performance Reduced Instruction Set Computer (RISC) processor developed by Motorola.

2 is a flowchart illustrating a reset control method of a conventional processor.

As shown therein, steps of determining whether a state transition occurs during a Ta time while performing BR monitoring (ST1) (ST2); Continuing to perform BR monitoring when a state transition occurs during the Ta time, and performing a reset assertion if no state transition occurs during the Ta time (ST3); Performing the BR monitoring if the reset state is maintained for a Tb time after the reset assertion, and performing the reset assertion if the reset state is not maintained for the Tb time (ST4); When the reset assertion is performed, the LED 4 is emitted to notify the processor that an abnormality has occurred (ST5).

The operation of the prior art configured as described above will be described in detail with reference to the accompanying drawings.

First, the control unit 3, which is a PLD (Programmable Logic Device) in which a reset logic is conventionally monitored, monitors a BR (Bus Request) signal, which is an address arbitration signal, for a predetermined time, and restarts the system when there is an error. At this time, the external LED (4) to indicate the state.

Thus, the first processor 1 and the second processor 2 use the companion mode of the MPC8260 and the MPC750 of Motorola, which allows the MPC750 to assert the BR signal in order to occupy the bus. The MPC8260 allows bus use by asserting a bus grant (BG) signal.

The MPC750 receives the BG signal and deasserts the BR signal. The BR signal is typically held for two clocks of the system clock.

If the process is running normally, this signal will continue to repeat the assert / deassert operation. In the prior art, the BR signal of the MPC750, which is a core processor, is used.

Thus, the controller 3 monitors the BR signal as an external input for a predetermined time, and when the signal maintains a high potential or a low potential for a predetermined time, it determines that the processor is in an abnormal state and asserts a reset signal to the processor.

At this time, the timer for measuring the timeout while keeping the high potential or the low potential constant may change the setting value to be variable.

The controller 3, which determines the processor abnormality, asserts a reset signal to each processor 1 and 2 for a predetermined time, and deasserts the reset signal to determine whether the processor 1 and 2 are operating normally. The BR signal will continue to be monitored.

The rising edge (low-potential to high-potential) and falling edge (high-potential to low-potential) of the BR signal are used to prevent the system clock from rising to high or low potential. Is designed to recount the timeout.

In addition, since monitoring is performed using the BR signal of the MPC750, which is a core processor, when the MPC750 is in an abnormal state, unlike the case in which the abnormal state of the core processor is not detected, such as when the MPC8260 transmits an address transmission signal by itself, the controller 3 It is possible to recognize the abnormal state of the processor.

In addition, a logic is implemented in the control unit 3 made of PLD so that an abnormal state can be confirmed by an external LED 4. The BR signal is monitored and a clock is divided during a reset due to a processor error. The OR operation is performed with the LED activate signal so that the LED 4 is toggled from the outside.

At this time, the signal toggled through a single LED device and the signal by simple on / off enables a trace of the reset reason.

3 is a monitoring timing diagram in FIG. 1.

Thus, referring to the timing diagram of FIG. 3, when the BR signal maintains the timeout value Ta above the low potential or the high potential, the controller 3 determines that the abnormal state is an abnormal state and applies a reset signal to the processor 1, 2. After the reset is maintained for a predetermined time Tb, the reset signal is returned to normal, and the repetition routine for monitoring the BR signal is started again.

At this time, during the Tb time, the LED 4 operates in the toggle mode through the OR operation and the division value of the reset signal and the clock.

Ta and Tb follow the processor specification time, and the LED toggle time (Tc) is such that the human perception outside the board is on the order of several hundred ms on average.

When the BR signal operates normally, the controller 3 checks the falling edge and the rising edge of the BR signal within Ta to recount the timeout.

However, this conventional technology has the following problems.

First, the conventional technology monitors the BR signal and restarts the system when there is an error.However, when the Software Watchdog Reset is applied from the MPC8260 itself, the BR signal is initialized to a high impedance state. In this case, since the state transition of the BR signal occurs, the conventional control unit 3 recognizes that the board is operating normally and restarts the counter, thereby causing a watchdog reset not to operate.

Second, the conventional structure allows the change of Ta and Tb, the watchdog timing window, but in the case of the software watchdog time of the MPC8260 chip itself, it is entirely the specification of the chip manufacturer. The current method was not suitable for the board of the process entering the commercial system.

Third, in the prior art, the FPGA inside the board receives data from the EEPROM (Electrically Erasable and Programmable Read Only Memory), and then completes the configuration. If the reset signal was released, there was a problem that the board did not operate normally.

Accordingly, the present invention has been proposed to solve the above-described general problems, and an object of the present invention is to implement completion of the configuration of the FPGA as a monitoring signal referenced by the controller for the normal operation of a processor used in a mobile communication system. The present invention provides a reset control apparatus and a method of a processor capable of controlling a reset operation for an abnormal state of a processor using a signal and an internal software watchdog reset signal generated by the processor itself.

In order to achieve the above object, the reset control apparatus of a processor according to an embodiment of the present invention,
A first processor; A second processor for outputting a BR (Bus Request) signal to the first processor; An FPGA for outputting a DONE signal to a controller and an EEPROM when a specific function is executed; An EEPROM for storing a DONE signal output from the FPGA; A controller configured to control the first processor and the second processor by using a software watchdog reset signal output from the first processor and the DONE signal output from the FPGA; The technical configuration is characterized by including the LED to receive the LED signal from the control unit to emit light.
In order to achieve the above object, a reset control method of a processor according to an embodiment of the present invention,

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A first step of controlling a reset signal of the first processor and the second processor during initialization of the FPGA after power-on by monitoring the execution signal of the FPGA in the controller; and performing a monitor of a BR (Bus Request) signal in the controller And determining whether a software watchdog reset is asserted in the first processor; if a software watchdog reset is asserted in the first processor, asserting a reset for the first processor and the second processor; A third step of initializing a counter, a fourth step of determining whether a state transition occurs during a timeout value abnormal time Ta when the software watchdog reset is not asserted in the first processor, and in the second step If a state transition occurs during the timeout value abnormal time Ta, the process returns to the first step, and the timeout value in the second step. A fifth step of performing a reset assertion if the state transition does not occur during the abnormal time Ta; and returning to the second step if the reset state is maintained for a predetermined time Tb after the third step; If the reset state is not maintained during (Tb), the sixth step of returning to the fourth step is performed.

Hereinafter, an embodiment according to the present invention, a reset control apparatus for a processor, and a method thereof will be described with reference to the accompanying drawings.

4 is a block diagram of an apparatus for controlling reset of a processor according to the present invention.

As shown therein, a first processor (MPC8260) 10; A second processor (MPC750) 20 for outputting a BR (Bus Request) signal to the first processor (10); A controller (30) for controlling the first processor (10) and the second processor (20) by using a software watchdog reset signal output from the first processor (10); The control unit 30 is configured to include an LED 40 which receives the LED signal and emits light.

The reset control device of the processor includes: an FPGA 50 for outputting an FPGA_DONE signal to the controller 30 and the EEPROM 60 when a specific function is executed; It further comprises an EEPROM (60) for storing the FPGA_DONE signal output from the FPGA (50).

In this case, the controller 30 monitors the FPGA_DONE signal output from the FPGA 50 to monitor the first processor 10 and the second processor 20 during initialization of the FPGA 50 after power is applied. It is characterized by controlling the reset.

5 is a flowchart illustrating a reset control method of a processor according to the present invention.

As shown therein, a first step (ST16) of performing BR monitoring and determining whether a software watchdog reset is asserted in the first processor 10; When a software watchdog reset is asserted in the first processor 10, a second step of asserting a reset for the first processor 10 and the second processor 20 and initializing a counter (ST18) Wow; A second step (ST19) of determining whether a state transition occurs during Ta time if the software watchdog reset is not asserted in the first processor (10); A third step of returning to the first step if a state transition occurs during the Ta time in the second step, and performing a reset assertion if no state transition occurs during the Ta time in the second step (ST20) )Wow; After the third step, if the reset state is maintained for the time Tb, the method returns to the first step, and if the reset state is not maintained for the time Tb, the method returns to the third step ST21.

The reset control method of the processor may include monitoring the execution (FPGA_DONE) signal of the FPGA 50 and then applying power to the first processor 10 and the second processor 20 during initialization of the FPGA 50. And controlling the reset and then returning to the first step (ST11 to ST15).

Operation of the reset control apparatus and method of the processor according to the present invention configured as described above will be described in detail with reference to the accompanying drawings.

First of all, the present invention provides an abnormal state of a processor using an execution signal indicating completion of configuration of an FPGA and an internal software watchdog reset signal generated by the processor itself as a monitoring signal referenced by a controller for normal operation of a processor used in a mobile communication system. This is to control the reset operation for.

Therefore, in the present invention, a programmable logic is implemented using reset logic, which is a configuration signal of the FPGA 50, and an internal software watchdog reset signal generated by the processor itself. The controller 30 may be monitored for a predetermined time to restart the system if there is an error.

Here, the FPGA 50 inside the board starts up after receiving data from the auxiliary EEPROM 60 during initialization. If the entire board is released before the operation is completed, the board does not operate normally. Certain modules associated with the FPGA 50 will not operate.

In order to prevent this phenomenon, the present invention monitors a run signal that is driven by the FPGA 50 after being initialized.

Thus, when the initialization of the FPGA 50 is not finished, the Done signal is continuously maintained at a low potential state, and when the initialization is completed, the FPGA 50 signals the high potential state to inform the EEPROM 60. Asserted with.

Then, the controller 30 monitors the run signal and releases the reset after being asserted to the high potential so that the board can be stably initialized.

6 is a monitoring timing diagram of FIG. 4.

Thus, as shown in FIG. 6, the controller 30 continuously monitors the FPGA_DONE signal in a power on reset state (ie, when power is applied). In the meantime, when the configuration is completed in the FPGA 50 and a Done signal informing the EEPROM 60 that the configuration is finished is asserted at high potential, the controller 30 in the FPGA 30 Recognizing that the configuration is over, Deassert Power on Reset, and the board comes to life.

In addition, in the related art, when the control unit monitors the BR signal as an external input for a predetermined time and maintains the high potential or the low potential for a predetermined time, the controller determines that the processor is in an abnormal state and asserts a reset signal to the processor. However, if a software watchdog reset occurs in the MPC8260, the BR signal becomes high potential as it is initialized internally in the MPC8260 itself. At this time, since the state transition of the BR signal occurs, the control unit determines that the operation is normal and does not generate a watchdog reset. In the Companion Mode of the MPC750 and MPC8260, the MPC8260 is used as an Input Output (IO) processor after disabling the core, while the MPC750 itself is not reset. If only the MPC8260 resets itself, the board will not function properly.

Therefore, the present invention monitors an internal reset signal (Software Watchdog Reset) generated when the MPC8260 does not operate normally for a predetermined time, thereby generating a reset of the entire board.

Thus, as shown in FIG. 6, the MPC8260 Software Watchdog Reset is monitored to convert the internally generated reset of the MPC8260 into a board-wide reset signal so that the MPC750 and MPC8260 receive the same reset signal and assert a board full reset. .

In addition, in the related art, the reset count is driven using the BR signal, whereas in the present invention, when the MPC8260 software watchdog reset signal is generated, the watchdog window is reset by initializing the counter value and restarting the watchdog window. Ensure the watchdog reset scheme is maintained.

As such, the present invention controls the reset operation for the abnormal state of the processor.

Although the preferred embodiment of the present invention has been described above, the present invention may use various changes, modifications, and equivalents. It is clear that the present invention can be applied in the same manner by appropriately modifying the above embodiments. Accordingly, the above description does not limit the scope of the invention as defined by the limitations of the following claims.

As described above, the reset control apparatus and method of the processor according to the present invention checks whether the FPGA is initialized inside the board by using a run signal, which is an FPGA configuration signal, and then starts a board to start a normal board. By monitoring the software watchdog resets occurring in the actual core process while monitoring the BR signal, the watchdog logic can be guaranteed to operate normally in any abnormal process state.

Claims (5)

delete A first processor; A second processor for outputting a BR (Bus Request) signal to the first processor; An FPGA for outputting a DONE signal to a controller and an EEPROM when a specific function is executed; An EEPROM for storing a DONE signal output from the FPGA; A controller configured to control the first processor and the second processor by using a software watchdog reset signal output from the first processor and the DONE signal output from the FPGA; Resetting control device of the processor, characterized in that configured to include a light emitting LED receiving the LED signal from the control unit. The method of claim 2, wherein the control unit, And monitoring a DONE signal output from the FPGA to control reset of the first processor and the second processor during initialization of the FPGA after power is applied. delete A first step of controlling a reset of the first processor and the second processor during initialization of the FPGA after powering on by monitoring an execution signal of the FPGA by the controller; A second step of determining whether a software watchdog reset is asserted in a first processor while monitoring a BR (Bus Request) signal in the controller; A third step of asserting a reset for the first processor and a second processor and initializing a counter when a software watchdog reset is asserted in the first processor; A fourth step of determining whether a state transition occurs during a timeout value abnormal time Ta when a software watchdog reset is not asserted in the first processor; In the second step, if the state transition occurs during the timeout value abnormal time Ta, the process returns to the first step.In the second step, if the state transition does not occur during the timeout value abnormal time Ta, the reset assertion occurs. Performing a fifth step; And a sixth step of returning to the second step if the reset state is maintained for a predetermined time Tb after the third step, and returning to the fourth step if the reset state is not maintained for the predetermined time Tb. Reset control method of the processor, characterized in that performing.

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