TWI794303B - Programmable hardware sleep cycle controller for 802.11 wireless devices supporting low-power - Google Patents

Abstract

A wireless device includes a sleep mode controller circuit (SMC), an RF circuit, and a processor. The SMC is configured to identify from a message that there is no impending data traffic to be received from another wireless device, put the wireless device into a power down mode powering down the processor and the RF circuit, and periodically checking for a another received message. Checking the RF message includes powering on the RF circuit on a periodic basis, determining whether another received message indicates that there is impending data traffic to be received from another wireless device, and, based on a determination that that there is impending data traffic to be received from another wireless device, powering up the processor.

Description

Programmable hardware sleep cycle controller for 802.11 wireless devices supporting low power

The present disclosure relates to sleep cycle control for wireless communication systems, and more particularly, to a highly programmable hardware sleep cycle controller for supporting low power IEEE 802.11 wireless devices.

The IEEE 802.11 standard defines the operation of Wi-Fi and wide local area network (WLAN) systems and applications. A wireless station (STA), access point (AP), or other wireless device according to the 802.11 standard for Wi-Fi may have a power save mode (PSM). The PSM can be configured to turn off Wi-Fi during expected periods when it is not in use. A wireless device can manage its PSM by using a signal called a traffic indication map (TIM). TIMs are used to identify wireless devices whose traffic is on hold and buffered. Periodically, at the appropriate time for the TIM to be sent to the wireless device by, for example, the AP, the wireless device will briefly wake up and look at the TIM. The wireless device will wake up, poll the received TIM (if available), and if the TIM includes a designation (eg, bit) that the particular wireless device has data to send, the wireless device will begin to fully transmit and receive data. When communication is initially set up, the interval or period at which the wireless device enters the PSM and waits for the TIM can be negotiated between the AP and the wireless device. PSM can be implemented by simply not emitting or listening to RF signals.

100‧‧‧system

102‧‧‧Wireless device

104‧‧‧Wireless device

106‧‧‧Sleep Mode Controller (SMC)

108‧‧‧antenna

110‧‧‧Radio Frequency (RF) Circuit

112‧‧‧Baseband modem

114‧‧‧Baseband Processor

116‧‧‧Media Access Control (MAC) Controller

118‧‧‧Central Processing Unit (CPU)

120‧‧‧Oscillator Controller

122‧‧‧Oscillator

124‧‧‧Frame Analyzer

200‧‧‧Finite State Machine (FSM)

202‧‧‧Status

204‧‧‧Status

206‧‧‧Status

208‧‧‧Status

210‧‧‧Status

212‧‧‧Status

214‧‧‧Status

216‧‧‧Status

218‧‧‧Status

220‧‧‧Status

222‧‧‧Status

224‧‧‧Status

226‧‧‧Status

228‧‧‧Status

300‧‧‧frame parser

302‧‧‧Measurement Instruction Table (TIM)

304‧‧‧Filter

306‧‧‧Trigger 1

308‧‧‧Trigger 2

310‧‧‧trigger 3

312‧‧‧Trigger 4

314‧‧‧Control logic

316‧‧‧Wake-up signal

[FIG. 1] is an illustration of an example system utilizing a highly programmable hardware sleep cycle controller for supporting low power wireless devices according to an embodiment of the present disclosure.

[FIG. 2] is a drawing of an example finite state machine showing example operations for putting the transmitting portion of a wireless device into a sleep mode and state, according to an embodiment of the disclosure.

[ FIG. 3 ] is a more detailed illustration of a frame parser according to an embodiment of the disclosure.

Embodiments of the disclosure include a sleep mode controller circuit (SMC). The SMC can be included in a wireless device. In combination with any of the above embodiments, the wireless device may include a processor that executes user-level or application-level software, wherein the SMC does not operate at such user-level or application-level, but instead operates at a Separate hardware configuration operations. The wireless device can include a radio frequency (RF) circuit and an oscillator communicatively coupled to the processor and the RF circuit. In combination with any of the above embodiments, the SMC can be configured to identify from a first received message through the RF circuit that there is no impending data traffic to be received from another wireless device. In combination with any of the above embodiments, the SMC can be configured to put the wireless device into a power down mode based on the received message. In combination with any of the above embodiments, the power down mode can include powering down the processor and powering down the RF circuit. In combination with any of the above embodiments, the SMC can be configured to periodically check for a second received message, including: energizing the RF circuit on a periodic basis, determining whether the second received message indicates the presence of An impending data traffic to be received from another wireless device, and based on determining that there is an impending data traffic to be received from another wireless device, powering on the processor. In combination with any of the above embodiments, the SMC can be configured to maintain the processor in a powered-down state based on a determination that there is no impending data traffic to be received from another wireless device. In combination with any of the above embodiments, the SMC can be configured to power down the RF circuit by disabling one of the phase locked loop circuits of the RF circuit. In combination with any of the above embodiments, the SMC can be configured to power down the RF circuit by disabling a clock signal from the oscillator to the RF circuit. In combination with any of the above embodiments, the SMC can be configured to maintain operation of the oscillator while powering down the RF circuitry and the processor. In combination with any of the above embodiments, the SMC can be configured to shut down the oscillator when powering down the RF circuitry and the processor. In combination with any of the above embodiments, the SMC can be configured to save and update a timer value recorded by a modem of the wireless device and configured to save and update the RF circuit when the RF circuit is powered down. state to identify when the second message is to be received by the wireless device.

In combination with any of the above embodiments, the wireless device may include a frame parser circuit configured to periodically checking the second received message, and during checking the second received message, identifying whether the second received message identifies a type of the wireless device, and based on whether the second received message identifies the wireless device the Type, and continue to parse the second received message. In combination with any of the above embodiments, the frame parser circuit can be configured to periodically check the second received message when activated by the SMC, check the during a second received message, identifying a field in the second received message upon which pattern matching is performed, and determining the second received message based on the field matching a pattern in the second received message Indicates that there is an impending data traffic to be received from another wireless device. In combination with any of the above embodiments, the frame parser circuit can be configured to periodically check for the second received message when activated by the SMC while the processor is powered down. During examination of the second received message, identifying a field in the second received message upon which the discrepancy analysis is performed, and a correspondence based on the field of the second received message being different from a previously received message field, determining that the second received message indicates that there is an impending data traffic to be received from another wireless device.

Embodiments of the present disclosure may include a medium having instructions for execution that, when executed, configure the SMC or the frame parser circuit to perform the operations of any of the above embodiments.

Embodiments of the present disclosure may include a wireless device. The wireless device may include any of the frame parser or SMC of any of the above embodiments.

Embodiments of the present disclosure may include a communication system. The communication system may include two or more wireless devices of any of the above embodiments.

Embodiments of the present disclosure may include methods performed by the instructions, when executed, by the SMC, frame parser circuit, wireless device, or communication system of any of the above embodiments.

[Cross-reference to related applications]

This application claims priority to U.S. Provisional Patent Application No. 62/572,975 filed on October 16, 2017, the entire disclosure of which is hereby incorporated herein.

1 is a diagram of an example system 100 utilizing a highly programmable hardware sleep cycle controller for supporting low power wireless devices according to an embodiment of the disclosure. Wireless devices may communicate via IEEE 802.11 standards such as Wi-Fi or other suitable standards. System 100 may include any suitable number and kinds of wireless devices. For example, system 100 may include a wireless device 104 and a wireless device 102 . The wireless device 104 can be, for example, an access point, a repeater, a base station, a router, a bridge, a server, or a gateway. The wireless device 102 may be, for example, a consumer device, a watch, a laptop, a tablet, an Internet of Things device or appliance, or a smartphone. These examples are non-limiting. The wireless device 102 and other wireless devices not shown can communicate with the wireless device 104 . In addition to data communications with wireless device 102, wireless device 104 may also be configured to send various control signals. With respect to a wireless device 104 designated as a master device, a wireless device 102 may be referred to as a slave device. Wireless device 102 may communicate through wireless device 104 to communicate with elements of a larger network.

A programmable hardware sleep cycle controller may be implemented on any suitable wireless device of system 100 . For example, wireless device 102 may include a sleep mode controller (SMC) 106 . SMC 106 may be implemented in any suitable manner, such as by analog circuitry, digital circuitry, instructions for execution by a processor, or any suitable combination thereof. SMC 106 may be configured to control sleep modes of various elements of wireless device 102 . For example, SMC 106 may be configured to set elements of wireless device 102 into a reduced power usage mode, remove clock signals from such elements, or turn off such elements. SMC 106 may be configured to allow wireless device 102 to remain connected to wireless device 104 while maintaining elements of wireless device 102 in such sleep modes. SMC 106 can be configured to allow such connections and sleep modes while waiting for data from wireless device 104 . Additionally, the SMC 106 can be configured to allow such connections and sleep modes while waiting until a programmable wake-up packet from the wireless device 104 is received. In an embodiment, SMC 106 may be configured to perform such tasks without waking up central processing unit (CPU) 118 for these tasks.

Wireless device 102 may include any suitable number and kinds of elements. For example, wireless device 102 may include antenna 108 coupled to radio frequency (RF) circuitry 110 or module. RF circuitry 110 may include transmit and receive subcircuits configured to propagate or receive signals from antenna 108 . The RF circuit 110 may include physical layers to modulate electromagnetic signals transmitted or received through the antenna 108 . RF circuitry 110 may include one or more phase-locked loops (PLLs) for receiving or transmitting signals. The RF circuit 110 may be implemented by analog circuitry, digital circuitry, or any suitable combination thereof.

The wireless device 102 may include a baseband modem 112 . The modem 112 may include transmit and receive subcircuits configured to control signal modulation in the RF circuit 110 . The modem 112 may include a baseband processor 114 . The baseband processor 104 can be configured to issue control signals to the transmit and receive sub-circuits to control signal modulation in the RF circuit 110 . The baseband processor 104 may be implemented using any suitable chip, microcontroller, processor, or other electronic device. Baseband processor 104 may be configured to perform encoding and decoding or modulation and demodulation of signals to be issued or received from RF circuitry 110 . The baseband modem 112 may perform an interface between physical layer operations on the RF circuit 110 and MAC layer operations on the MAC controller 116 .

The wireless device 1032 may include a media access control (MAC) controller 116 . MAC controller 116 may be implemented with any suitable combination of digital or analog circuitry. MAC controller 116 may be configured to interface data and commands between CPU 118 and baseband modem 112 .

A wireless device may include one or more clock sources, such as oscillator 122 . Oscillator 122 may be implemented in any suitable manner, such as by an RC oscillator or a crystal oscillator. The oscillator 122 is operable when a voltage is applied to it. The oscillator 122 can be controlled and powered by the oscillator controller 120 . Oscillator controller 120 may be implemented by any suitable combination of analog and digital circuitry. Oscillator controller 120 may be configured to modify the clock signal from oscillator 122 and to route such signals to each of the other elements of wireless device 102, such as RF circuitry 110, baseband modem 112, MAC controller 116, and CPU 118.

In one embodiment, the SMC 106 can be configured to implement a number of different sleep modes, reduced power modes, or shutdown modes. Furthermore, SMC 106 may be configured to selectively apply any such modes to one or more elements of wireless device 102 . For example, SMC 106 may apply a given mode to one element of wireless device 102 while maintaining operation of other elements of wireless device 102, or placing another element of wireless device 102 in a different mode. In another embodiment, the SMC 106 may be configured to control the application of clock signals to components of the wireless device 102 . The application of the clock signal may fully or partially implement the mode of operation of other elements of the wireless device 102 . SMC 106 can be configured to power on or off such elements. SMC 106 may be configured to control such power-on or power-off based on or in response to expected received signals.

For example, SMC 106 may issue an enable or disable signal to baseband modem 112 . Such enable or disable signals may also have the effect of enabling or disabling the operation of the RF circuit 110 . In another example, SMC 106 may issue an enable or disable signal to MAC controller 116 . The connections between the SMC 106 and respective other elements of the wireless device 102 may be separate and distinct. Accordingly, SMC 106 may be configured to separately and selectively disable or enable other elements of wireless device 102 .

In another example, SMC 106 may enable or disable oscillator 122 or oscillator controller 120 . This may have the effect of enabling or disabling the clock signal issued from the oscillator 122 to various other elements of the wireless device 102 . SMC 106 can similarly enable or disable other oscillators (not shown). Components of wireless device 102 such as RF circuitry 110, baseband modem 112, MAC controller 116, or CPU 118 may receive a clock signal (whether modified or original) from oscillator 122. Such elements of the wireless device 102 may be effectively powered down when the clock signal to such elements is not enabled.

At various times, CPU 118 may have no other pending tasks to perform. Upon identifying that there are no other pending tasks to execute, the SMC 106 may be enabled to shut down portions of the wireless device 102 upon notification by the CPU 118 through a sleep mode request. CPU 118 may then be woken up by SMC 106 through an interrupt or re-enablement of clock operations. Additionally, the CPU 118 may be woken up by other events from other components not shown, such as a user actuating a button, or another subsystem (not shown) generating an interrupt. Additionally, the CPU 118 can enable WIFI operation and then wake up by issuing a WIFI_EN signal to the SMC 106 . Following such a signal, the SMC 106 may be configured to wake up or reconnect the clocks of other components of the wireless device 102 . For example, if the CPU 118 is preparing to send data to the wireless device 104, the CPU may issue such an enable.

In one embodiment, the SMC 106 may be configured to control the power-on and power-off cycles of the CPU 118 when no data is received from any other source, such as the wireless device 104 . For example, CPU 118 may be shut down by SMC 106 in sleep mode if data is not sent from wireless device 102 and data is not received at wireless device 102 from wireless device 104 . CPU 118 may have no other pending tasks to execute. Upon identifying no other pending tasks to execute, SMC 106 may be enabled to shut down portions of wireless device 102 when notified by CPU 118 through sleep mode.

In one embodiment, in sleep mode, SMC 106 may disable CPU 118 activity while periodically allowing operation of RF circuitry 110 and baseband modem 112 to check for indications received from wireless device 104 to send more The TIM or other message of the data. Upon receipt of such a TIM or other message, SMC 106 may be configured to wake up or enable CPU 118 or MAC controller 116 . Such a sleep mode may be performed when active data transfer over the wireless connection between the wireless devices 102, 104 is inactive. The TIM message may indicate resumption of such active data transmission.

In one embodiment, SMC 106 may be configured to stop clocking MAC controller 116 or CPU 118 during such sleep modes. In another embodiment, SMC 106 can be configured to stop clocking baseband modem 112 and RF circuit 110 in sleep mode, except when scheduled to receive TIM, frame, or other similar messages outside of a specific time period in the loop. In another embodiment, the SMC 106 can be configured to shut down or disable the clock operation of the PLL of the RF circuit 110 during sleep mode. In another embodiment, SMC 106 may be configured to power down RF circuit 110 during such sleep periods. SMC 106 may be configured to power on RF circuit 110 during specific times in a cycle when it is scheduled to receive a TIM, frame, or other similar message.

In order to place elements of the wireless device 102 in sleep or power down mode, and to appropriately and selectively wake up the wireless device 102, the SMC 106 can be configured to implement an 802.11 Timing Synchronization Function (TSF) counter. Such TSF counters may have counterparts in the MAC controller 116 . The value of the TSF counter in the MAC controller 116 may be copied to the counter in the SMC 106 when the RF component is powered down, and restored after the MAC controller 116 is powered up. During a power outage, the TSF counter in SMC 106 may be updated. To perform such timing while powering down other components and inhibiting the oscillator output to other components, SMC 106 may include a separate clock from oscillator 122 . For example, SMC 106 may include a low power clock operating at 32MHz. Such a clock may be sufficient for the SMC 106 to determine a time window of when to receive a TIM, frame, or other message.

When the RF circuitry 110 (or other portion of the wireless device 102 configured to listen for received messages) is powered down or clocked out, the SMC 106 can use such clocks to schedule operations. When the radio silence period passes and a time window is reached when a TIM, frame, or other message is to be received, the SMC 106 can be configured to power up portions of the RF circuitry 110 or baseband modem 112 to Listen for incoming TIMs, frames or other messages. If no such message is received, or if the received message indicates that there is no additional data to be received, the RF circuit 110 and baseband modem 112 may be powered down again until the next such time window. If such a message is received and indicates additional data to be received, RF circuit 110 and baseband modem 112 may be powered on to receive the additional data after receiving the message. Additionally, SMC 106 may power up CPU 118 due to such messages expecting to process data to be received.

Wireless device 102 may include any suitable mechanism for listening for TIMs, frames, or other messages to be received. For example, the wireless device 102 may include a frame parser 124 . Frame parser 124 may be implemented by analog circuitry, digital circuitry, combinational logic, instructions for execution by a processor, or any suitable combination thereof. Frame parser 124 may be configured to operate independently of CPU 118 . Thus, frame parser 124 can nevertheless be configured to operate when CPU 118 is powered down or clocked out. The frame parser 124 may also be called a beacon parser. Frame parser 124 may be configured to listen for TIMs, frames, or other messages to be received by wireless device 102 at specified times. Frame parser 124 may be implemented in any suitable component of wireless device 102 . For example, frame parser 124 may be implemented in MAC controller 116 . In other examples, frame parser 124 may be implemented in SMC 106 or independently. Frame parser 124 may be powered on or off, or clocked or not, along with other circuitry in which frame parser 124 is implemented. Frame parser 124 may be powered on or clocked when a TIM, frame, or other message is to be received at wireless device 102 . Frame parser 124 may be powered down or unclocked at other times during appropriate sleep or rest modes.

In one embodiment, during power down or sleep mode, when components such as RF circuitry 110, baseband modem 112, MAC controller 116, frame parser 124, or CPU 118 are powered down, oscillator 122 Can remain operational. This may reflect a distinct power mode separate from other power modes, where oscillator 122 is also powered down in addition to one or more such elements. Such an embodiment may exist, for example, if a separate clock for the operation of the SMC 106 is not available. Furthermore, such an embodiment may be used when the excitation and phase locking of the oscillator 122 and its clock signal requires a significant amount of time to initialize. Furthermore, such embodiments may be used when the CPU 118 is to perform other processing tasks and the oscillator 122 needs to be used, but RF communication is suspended.

Accordingly, in one embodiment, the SMC 106 may be configured to provide a sleep mode in which the oscillator 122 is turned off or inhibited from elements of the wireless device 102 . Furthermore, in another embodiment, the SMC 106 may be configured to provide a sleep mode in which the oscillator 122 is still operating. While the oscillator 122 is still operating, it may be provided to one or more elements of the wireless device 102 . In further embodiments, such elements may themselves include the SMC 106 . In another further embodiment, such elements may include CPU 118 . The choice of sleep mode may depend on whether some components require the oscillator 122 while other components are sleeping. While the oscillator 122 is still in the operating mode, the SMC 106 may disable elements of the wireless device 102 with enable or disable signals to place these elements in a sleep mode. Placing a device in sleep mode by depriving the device of a clock signal may be a synchronous sleep mode. Putting a component into sleep mode by providing a separate enable or disable signal may be an asynchronous sleep mode.

The SMC 106 can be configured to properly time or sequence the elements of the wireless device 102 to resume operation from sleep mode. For example, some components of the wireless device 102 may require specific startup sequences to function properly. These elements may themselves include power conditioning or receive power from a power conditioner with an initialization phase. The SMC 106 may start powering up in a manner that supports, for example, a staged startup of a low dropout (LDO) power converter, or an oscillator initialization sequence with applying voltage to the oscillator and then waiting for the frequency to settle. Furthermore, SMC 106 may be configured to store the state of one or more of various elements of wireless device 102 when such elements are powered down, and then restore such elements after operation resumes. For example, modulation parameters, last used values, or other configuration data of the RF circuit 110 or the baseband modem 112 may be saved by the SMC 106 to a register or flip-flop when power is turned off.

The SMC 106 is operable to cycle power on and off without firmware or user intervention. The SMC 106 can perform cycling into and out of low power modes or states entirely in hardware without any intervention from the host controller or software.

SMC 106 may be configured to initiate a sleep mode on any suitable basis, and specific ones of available sleep modes. For example, the SMC 106 may receive an instruction to enter sleep mode via a register value set by software, an internal bus or signal line, or enter by itself if the SMC detects no data activity on the RF portion of the wireless device 102. sleep mode.

Components of wireless device 102 may operate in different power domains or subsystems. The RF circuit 110 can operate on a separate power domain of 1.5V. OSC controller 120 may operate in its own power domain. Baseband modem 112 and MAC controller 116 may operate in separate power domains, or may operate in power domains together with the remaining elements.

2 is a drawing of an example finite state machine (FSM) 200 showing example operation of the SMC 106 to put the transmitting portion of the wireless device 104 into sleep modes and states, according to an embodiment of the disclosure. FSM 200 may represent the operation of digital circuitry, combinational logic, firmware operating below the level of the operating system of the processor of system 100, or other suitable implementation.

The run mode may be shown in state 202, where no sleep mode or power down operation is active. One or more sleep modes, such as in states 224, 218, may be used. FSM 200 illustrates additional operations that may be performed to enter or exit these run states or sleep states.

Power-off Wi-Fi operation may include various sleep modes and states. In some cases, modes may be characterized by portions of wireless device 102 transitioning to different power states in such modes. Each mode may have a different sleep state hierarchy achieved within it. For example, wireless deep sleep mode (WDS) mode also uses the lowest power state for RF communication by completely shutting down the RF circuit 110 in addition to turning off the oscillator 122 of the RF circuit 110 . A WDS sleep mode may be shown in state 224 . In another example, a wireless sleep mode (WSM) may keep the oscillator 122 active when the RF circuit 110 is turned off, so that the wireless device 102 may be able to wake up faster, resulting in flexible operation. WSM sleep mode may be shown in state 218 .

In addition, each sleep mode may also have the ability to enter a sleep state or a rest state (in addition to a fully operational state). In one embodiment, the rest state may be a transient state in which a portion of the wireless device 104 transitions into or out of WSM or WDS mode. A sleep state may be a state in which the wireless device 104 has fully transitioned into WSM or WDS mode. The rest state can be entered upon exiting the sleep state or immediately asserting entry into the sleep state. SMC 106 may be configured to cause a portion of wireless device 104 to move into a rest state or sleep state. The WDS rest state can be implemented by state 204 . The WSM rest state can be implemented by state 214 .

In the rest state and sleep state, the transmitter and receiver chains of the RF circuit 110 may be turned off. In the sleep state, the transmitter and receiver chains of RF circuitry 110 may be turned off, and modem 112 and MAC controller 114 may have no clock signal received from oscillator 122 (i.e., no clock or gated) . The rest state may be entered periodically or upon a wakeup event, such as the wireless device 104 periodically waking up to check for a TIM message, the wireless device 104 waking up on demand, or the wireless device 104 periodically entering after a timeout or checking for a TIM message sleep. Rest state behavior can be the same or similar to WSM and WDS modes.

Once in WDS or WSM mode, SMC 106 may be configured to control power or clock signals to RF circuitry 110 , modem 112 , MAC controller 116 , and CPU 118 . The SMC 106 can be configured to automatically and periodically switch between the run state, the sleep state, and the rest state in designated sleep modes. The waiting time for the duration of sleep state and rest state can be programmed. Furthermore, more specific features such as the PLL of the RF circuit 110 may be programmable. For example, SMC 106 may be configured to recalibrate such PLLs every sleep cycle or every N sleep cycles. Additionally, the rest state can be completely deactivated. In such cases, SMC 106 may generate a wakeup interrupt after each sleep cycle.

In one embodiment, in WSM and WDS sleep modes, modem 112 and MAC controller 116 may be powered on, but their isoclock signals may be suppressed. Therefore, the register and finite state machine state of such elements can be preserved. WSM and WDS modes can only be entered for traffic that is not on hold. In addition, interrupts other than those that are wake-up sources can be masked.

By default, the components of the electronic device 102 can be in the operating mode in the state 202 . In state 202 , the element may be powered on and receive a normal, expected clock signal from oscillator 122 . The run mode in state 202 can be terminated by a transmission in first terminate state 206 . In one embodiment, each of the WDS or WSM sleep modes may be entered by a hardware sleep mode request. These can be driven by the SMC 106 determining that there is no data to transmit or receive (based on turning off the TIM or other messages), or by software or user demand by setting bits. Entry of a specific one of WDS or WSM can be determined by control bits or by the requesting entity. WDS and WSM sleep modes may include state 224 and state 218, respectively. Similarly, state 224 or state 218 may be exited based on a hardware determination that a TIM or other message has been received from SMC 106, or by system software or user requirements. In one embodiment, a combination of SMC 106 determinations using hardware and user or application level input from software may be used to determine whether to enter or exit sleep mode.

In state 206, the FSM 200 will proceed to a different branch of operation depending on whether WDS or WSM is used. To use WSM, FSM 200 may proceed to state 212 where a WSM sleep state is initiated.

State 212 may include operations similar to WSM rest. Upon entering the WSM sleep state, the SMC 106 may place the MAC controller 116 in a low power mode. SMC 106 may copy the value of the TSF timer to SMC 106 . The SMC may place the modem 112 in a low power mode. SMC 106 may then suppress clock signals to MAC controller 116 and modem 112 . The SMC 106 may then place the RF circuit 110 in sleep mode by turning off the power. SMC 106 may be in state 218 .

SMC 106 may enter state 220 after a certain amount of time or when a wake-up is requested. If the rest state is enabled, the SMC 106 may enter the run mode state 202 directly. A wakeup interrupt may be raised for CPU 118 . If rest is enabled, the SMC 106 may enter state 214 . Once in state 214, a rest duration may be experienced, or SMC 106 may wait for frame parser 124 to trigger. If a trigger is encountered, an interrupt will be issued to the CPU 118 to wake up the system. If no data is received and the rest duration expires, the FSM 200 may return to state 212.

Transitioning from state 214 to state 202 may include requesting a clock signal from the PLL of oscillator controller 120 . SMC 106 may wait for a clock to arrive. TSF values and other timers may be restored to MAC controller 116 . MAC controller 116 may be released from sleep mode. The modem 112 and the RF circuit 110 can be released from the power saving mode. The FSM is operable in state 202 .

In state 206, if WDS is to be used, FSM 200 may proceed to state 210 to initiate WDS sleep. State 210 may include operations similar to WDS Rest. To transition to WDS, RF circuit 110 may be powered down along with oscillator 122, and power converters, transmitter and receiver chains within RF circuit 110, and PLLs. SMC 106 may continue and place MAC controller 116 in a lower power mode, transmit the MAC TSF timer or value, place modem 112 in low power mode, and stop clocking to modem 112 and MAC controller 116 . FSM 200 may be in state 224 .

SMC 106 may exit state 224 once the timer expires or a wake-up is requested. If rest mode is not enabled, the SMC 106 may go to state 202 . If rest is enabled, the SMC 106 may go to state 204 . However, going to state 204 may include several intermediate states or steps. SMC 106 may go to state 228 assuming RF circuit 110 is disabled. Otherwise, SMC 106 may go to state 226 . In state 228, RF circuitry 110 may be placed in a standby mode. At 226, the oscillator 122 may be restarted. SMC 106 may wait for oscillator 122 to settle. At 222 , other portions of the RC circuit 110 may be enabled by applying a clock signal from the oscillator 122 . At 216, a request for PLL operation may be made. Clocks can be applied to the modem 112 and the MAC controller 116 . After waiting, at 208, modem 112 may restore its scratchpad value. To proceed to 204, MAC controller 116 may restore its TSF value and other timers. MAC controller 116 and modem 112 may be enabled. FSM 200 may be in state 204 .

Once in state 204 , a rest duration may be experienced, or SMC 106 may wait for frame parser 124 . If a trigger is encountered, an interrupt will be issued to the CPU 118 to wake up the system. If no data is received and the rest duration expires, FSM 200 may return to state 204 .

FIG. 3 is a more detailed illustration of a frame parser 300 according to an embodiment of the disclosure. The frame parser 300 can be implemented as the frame parser 124 . Frame parser 300 may include frame filter 304 , a plurality of triggers (such as trigger 1 306 , trigger 2 308 , trigger 3 310 , and trigger 4 312 ), and control logic 314 . These elements may be implemented by analog circuitry, digital circuitry, combinational logic, or any suitable combination thereof.

When powered on, or clocked, or otherwise enabled, frame parser 300 may wait for TIM 302 or other frames or messages to arrive. TIM 302 may include header information identifying the target wireless device. Frame filter 304 may be configured to determine whether the 802.11 type or subtype identifier of a received frame such as TIM 302 matches, for example, the 802.11 type or subtype of a frame to be monitored in the SMC. If the type or subtype device identifier or other identification in TIM 302 matches the expected frame type and subtype, frame parser 300 may continue processing TIM 302 . Otherwise, the frame parser 300 may discard or drop the frame.

Each of flip-flops 306-312 can process TIM 302 in parallel or in series. Triggers 306 - 314 may each include matching criteria against which TIM 302 is evaluated. Although four flip-flops are shown in FIG. 3, frame parser 300 may include any suitable number of flip-flops. Each of flip-flops 306-312 may evaluate a header portion or other information of a frame in TIM 302. Each of the triggers 306-312 can be enabled or disabled separately. Furthermore, control logic 314 may evaluate any suitable logical combination of results from flip-flops 306-312.

Each of triggers 306-312 may evaluate separate fields with the same criteria, evaluate the same field with different criteria, or a combination thereof. The particular triggers used and the criteria used with such triggers may depend on the protocol used by the wireless device and how much of the TIM 302 needs to be matched to determine whether the TIM 302 indicates that the wireless device is ready to receive additional information.

If control logic 314 finds that the identified logical combination of matching results from flip-flops 306-312 exists, control logic 314 may issue a wake-up signal 316 to the rest of the wireless device. Selected ones and logical combinations of flip-flops 306-312 matching fields may instruct TIM 302 to signal additional information to be received to the wireless device. As a result, other components of the wireless device can be powered on or woken up. Otherwise, control logic 314 may discard TIM 302 or take no action. The wireless device may return to a deeper sleep state, as shown in FIG. 2 .

The actions of the frame parser 300 can be made independent of the operation of other components of the wireless device, such as the CPU. Thus, the framer profiler 300 can inspect the TIM 302 without waking up, powering up, or supplying clocks to such other elements of the wireless device. For example, the configuration of the operation of the frame parser 300 can be generated through suitable registers.

Frame parser 300 may be activated at any suitable stage of operation of the wireless device. As discussed above in the context of FIG. 2, frame parser 300 may be activated, for example, in the Wsnooze state upon receipt of a TIM or other message or frame.

Each of the enabled triggers 306-312 may perform a logic check on the specified field. Designated fields can be within TIM 302 or in any suitable portion of any frame. The field may be, for example, eight bits wide. Each trigger (as defined by the register) may include a designation of the fields that the trigger is to check. This field can be defined by an octet number. The octet can be defined from the start of the frame. The frame control field can be octet 0 and 1.

Each trigger (as defined by a register) may include a designation (such as a bit) whether to perform a type lookup or change evaluation on a field. Logic checks may include additional logic checks beyond pattern hunting or change evaluation.

In a pattern search, another register value may specify the pattern to be used when parsing the fields of the TIM 302 . Patterns may be specified by bitmap filters, defined patterns, or a combination thereof. The bitmap filter identifies which bits in the field to parse. For example, a value of "1" set in a bit position identifies the bit to be parsed and evaluated. A value of "FF" selects all bits in the field for parsing and analysis, while a value of "00" selects none. The defined pattern may be an 8-bit pattern to match the TIM 302 in the identified field. A trigger is fired when the selected bits indicated by the bitmap filter match the defined pattern.

In change detection, another register value may specify an octet pattern matching the identified field of the TIM 302 of the previous frame. In one embodiment, the pattern defines the bits that must match for the trigger to not activate. For example, any deviation between the current TIM 302 and the previous frame at a specified bit position (specified by the pattern) in the identified field may activate a trigger. In another embodiment, the pattern defines the bits that must match for the trigger to activate.

Additionally, a given flip-flop register may include a bit indicating whether the flip-flop is enabled or disabled for use. As discussed above, any suitable number of available triggers may be enabled. Additionally, triggers can be combined to produce more complex wake-up trigger criteria. Flip-flops can be combined with logical operations such as OR, AND, NOT, or XOR. The sequence of operations and logical operations can be programmed through yet another register.

The operation of frame parser 300 may itself be enabled in any suitable manner. The frame parser 300 can be enabled or disabled by register value, enable signal, power, or clock. If the frame parser 300 is enabled and the frame does not match the trigger condition, the frame may be discarded. Otherwise, the frame may not be discarded if the frame parser 300 is disabled or if the frame matches the trigger condition.

An instance register for a given trigger may include fields such as the following

Trig Enable may define whether a given trigger will check the TIM 302 type or changed bits. Trig Mode can be a bit that defines whether a given trigger will perform pattern matching or perform change detection. Trig Filter can be eight bits (or otherwise, the size of the field) and a mask that is applied to the on the TIM 302 for the identified field. Trig Filter defines the bits for which changes are evaluated in change detection mode. Trig Pattern can be eight bits (or otherwise, the size of the field) and the value that frame parser 300 looks for in the identified field. The search can be overlaid with a mask from the Trig Filter. The Trig Octet may define the field of the TIM 302 on which the search and comparison will be performed. Trig Octets can be eight bits wide, or any other suitable length.

The instance registers of frame dissection 300 may include fields such as the following

Type Enable can be a bit that enables the frame filter 304 to filter the frame type according to 802.11. Sub Type Enable may be a bit that enables the frame filter 304 to filter frame subtypes according to 802.11. Type may be a field used when Type Enable is enabled. Type defines the received packet or pattern of 802.11 types that must be matched in the TIM 302 for additional analysis. Similarly, Sub Type defines the pattern of 802.11 subtypes that must be matched in received packets or TIM 302 for additional analysis.

Function0, Function1, and Function2 may each define a combination of flip-flops 306-312 to be executed. Function0 Priority, Function1 Priority, and Function2 Priority can define the order of operations between Function0 to Function2.

For example, Function0 may specify a combination of trigger 1 306 and trigger 2 308 . "1" may specify that flip-flop 1 306 and flip-flop 2 308 are to be ANDed together (if the two flip-flops are enabled). "0" may specify that flip-flop 1 306 and flip-flop 2 308 are to be ORed together (if the two flip-flops are enabled).

Function1 may specify a combination of Trigger 1 306 , Trigger 2 308 , and Trigger 3 310 . "1" may specify that the flip-flops are to be ANDed together (if all flip-flops are enabled). "0" may specify that the flip-flops are to be ORed together (if all flip-flops are enabled).

Function2 may specify a combination of Trigger 1 306 , Trigger 2 308 , Trigger 3 310 , and Trigger 4 312 . "1" may specify that the flip-flops are to be ANDed together (if all flip-flops are enabled). "0" may specify that the flip-flops are to be ORed together (if all flip-flops are enabled).

Therefore, Function0, Function1, and Function2 can be implemented by specifying whether to use AND or OR for a particular combination of bits. Function0 Priority, Function1 Priority, and Function2 Priority can be implemented with two bits to show the order or priority relative to other functions. "00" may define the first or highest priority, "01" may define the second or next lowest priority, and "10" may define the third or lowest priority.

Among them, trigger 1 is given as t1, trigger 2 is given as t2, trigger 3 is given as t3, trigger 4 is given as t4, function0 is given as f0, and function1 is given as f1 , and Function2 is given as f2, the set of possible combinations of trigger conditions can be given as

Although specific ways of implementing register designations for logical combinations of flip-flops 306-312 to be used by frame parser 300 have been described above, any suitable way of specifying such combinations of flip-flops may be used.

Thus, the SMC 106 can enable very low power architectures. Such architectures are applicable, for example, to battery-powered 802.11 IoT network applications. The SMC 106 enables the system to avoid the CPU activity required to maintain 802.11 connections with other wireless devices when data communication is inactive.

The disclosure has been described in terms of one or more embodiments, and it should be understood that many equivalents, alternatives, variations, and modifications, other than those expressly stated, are possible and within the scope of the disclosure. While the disclosure is susceptible to various modifications and alternative forms, specific illustrative embodiments thereof have been shown in the drawings and described in detail herein. It should be understood, however, that the specific example embodiments described herein are not intended to limit the disclosure to the precise forms disclosed herein.

100‧‧‧system

102‧‧‧Wireless device

104‧‧‧Wireless device

106‧‧‧Sleep Mode Controller (SMC)

108‧‧‧antenna

110‧‧‧Radio Frequency (RF) Circuit

112‧‧‧Baseband modem

114‧‧‧Baseband Processor

116‧‧‧Media Access Control (MAC) Controller

118‧‧‧Central Processing Unit (CPU)

120‧‧‧Oscillator Controller

122‧‧‧Oscillator

124‧‧‧Frame Analyzer

Claims (18)

A wireless device comprising: a sleep mode controller circuit (sleep mode controller circuit, SMC); a processor; a radio-frequency (radio-frequency, RF) circuit; and an oscillator communicatively coupled to the processor and the RF circuit; wherein the SMC is configured to: identify from a first received message through the RF circuit that there is no impending data traffic to be received from another wireless device; based on The first received message places the wireless device in a power down mode, wherein the power down mode includes powering down the processor and powering down the RF circuit; periodically checking a second a received message comprising: energizing the RF circuit on a periodic basis; determining whether the second received message indicates an impending data traffic to be received from another wireless device; based on pending reception from another wireless device A determination of the impending data traffic of the wireless device causes the processor to be powered on; and the wireless device further includes a frame parser (frame parser) circuit configured to operate when the processor is turned off Power-on: periodically check the second received message when activated by the SMC; During the checking of the second received message, identifying whether the second received message identifies a type of the wireless device; and based on whether the second received message identifies the type of wireless device, continuing to parse the second received message Receive messages. The wireless device of claim 1, wherein the SMC is further configured to maintain the processor in a powered-off state based on a determination that there are no impending data traffic to be received from another wireless device. The wireless device of claim 1, wherein powering down the RF circuit includes disabling a phase-locked loop circuit of the RF circuit. The wireless device of claim 1, wherein powering down the RF circuit includes disabling a clock signal from the oscillator to the RF circuit. The wireless device of claim 1, wherein the SMC is further configured to maintain operation of the oscillator when the RF circuit and the processor are powered down. The wireless device of claim 1, wherein the SMC is further configured to turn off the oscillator when the RF circuit and the processor are powered off. The wireless device as claimed in claim 1, wherein the SMC is further configured to save and update a timer value when the RF circuit is powered off, the timer value is recorded by a modem of the wireless device and is configured to identify when the second message is to be received by the wireless device. A wireless device comprising: a sleep mode controller circuit (SMC); a processor; a radio frequency (RF) circuit; and an oscillator communicatively coupled to the processor and the RF circuit; wherein the SMC is configured to: identify from a first received message through one of the RF circuits that there is no pending message from another Imminent data traffic received by a wireless device; placing the wireless device in a power down mode based on the first received message, wherein the power down mode includes powering down the processor and powering down the RF circuit power; periodically checking a second received message, comprising the steps of: energizing the RF circuit on a periodic basis; determining whether the second received message indicates impending data to be received from another wireless device traffic; powering the processor based on a determination of impending data traffic to be received from another wireless device; and the wireless device further comprising a frame parser circuit configured to To when the processor is powered off: periodically check the second received message when activated by the SMC; during the checking of the second received message, identify the type to execute in the second received message a field for pattern matching; and performing pattern matching on the second received message using a pattern specified for the frame parser circuit that matches the first received message message. The wireless device as claimed in claim 1, wherein the frame analyzer circuit is further configured to when the processor is powered off: periodically check the second received message when activated by the SMC; during a second received message, identifying a field in the second received message upon which a discrepancy analysis is performed; and based on the field of the second received message being different from a corresponding field of a previous received message, It is determined that the second received message indicates an impending data traffic to be received from another wireless device. A method for sleep cycle control comprising: identifying from a first received message at a first wireless device through a radio frequency (RF) circuit that there are no impending data traffic to be received from another wireless device ; based on the first received message, placing the wireless device in a power down mode, wherein the power down mode includes powering down a processor of the wireless device and powering down the RF circuit; periodically checking a A second received message comprising: energizing the RF circuit on a periodic basis; determining whether the second received message indicates an impending data traffic to be received from another wireless device; a determination of impending data traffic received by the device, powering up the processor; and while the processor is powered down: periodically checking for the second received message; During the checking of the second received message, identifying whether the second received message identifies a type of the wireless device; and based on whether the second received message identifies the type of wireless device, continuing to parse the second received message Receive messages. The method of claim 10, further comprising maintaining the processor in a powered-off state based on a determination that there are no impending data traffic to be received from another wireless device. The method of claim 10, wherein powering down the RF circuit includes disabling a phase locked loop circuit of the RF circuit. The method of claim 10, wherein powering down the RF circuit comprises disabling a clock signal from an oscillator to the RF circuit. The method of claim 10, further comprising maintaining operation of an oscillator while powering down the RF circuit and the processor. The method of claim 10, further comprising shutting down an oscillator when powering down the RF circuit and the processor. The method of claim 10, further comprising saving and updating a timer value when the RF circuit is powered down, the timer value being recorded by a modem of the wireless device and configured to identify when to be powered by the RF circuit The wireless device receives the second message. A method for sleep cycle control comprising: identifying from a first received message at a first wireless device through a radio frequency (RF) circuit that there are no impending data traffic to be received from another wireless device ; placing the wireless device in a power down mode based on the first received message, wherein the power down mode includes powering down a processor of the wireless device and powering down the RF circuit; periodically checking a first Two received messages comprising: energizing the RF circuit on a periodic basis; determining whether the second received message indicates an impending data traffic to be received from another wireless device; based on pending reception from another wireless device A determination of an impending data traffic, powers up the processor; and when the processor is powered off: periodically checks the second received message; during the checking of the second received message, identifies a field in the second received message upon which pattern matching is performed; and pattern matching is performed on the second received message using a pattern designated for the field of the second received message, the The pattern matches the first received message. The method of claim 10, further comprising when the processor is powered off: periodically checking the second received message; during the checking of the second received message, identifying data in the second received message a field for performing discrepancy analysis; and based on the field of the second received message being different from a corresponding field of a previously received message, determining that the second received message indicates to be received from another wireless device Upcoming data traffic.

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