KR100597061B1 - Tft lcd gate driver circuit with two-transistion output level shifter - Google Patents

Abstract

The present invention provides a signal comprising a first state of a first voltage level and a second state of a second voltage level, a first power supply providing a first voltage level, a gate electrode connected to the first power supply, a signal A first high voltage transistor comprising a first electrode receiving a second electrode and a second electrode connected to the node, a second power supply providing a third voltage level, a first electrode connected to the second power supply and a first connected to the node; A circuit for converting a voltage level in a liquid crystal display panel, comprising a second high voltage transistor comprising a second electrode, wherein the voltage level of the node is at approximately a third voltage level in response to the first state of the signal. Is pulled to approximately a second voltage level in response to the second state of the signal.

Description

TFT LCD gate driver with two-transition output level shifter {TFT LCD GATE DRIVER CIRCUIT WITH TWO-TRANSISTION OUTPUT LEVEL SHIFTER}             

1A is a block diagram showing a gate driver of the prior art;

1B is a diagram showing different voltage levels used in the prior art gate driver,

2 is a circuit diagram showing a circuit for converting a voltage level according to an embodiment of the present invention;

3 is a circuit diagram showing a circuit for converting a voltage level according to another embodiment of the present invention;

4 is a circuit diagram showing a circuit for converting a voltage level according to another embodiment of the present invention;

5 is a circuit diagram showing a circuit for converting a voltage level according to another embodiment of the present invention.

TECHNICAL FIELD The present invention generally relates to liquid crystal display ("TFT LCD") elements of thin film transistors, and more particularly to an output level shifter of a TFT LCD gate driver.

Active matrix liquid crystal display ("LCD") elements generally comprise a display panel and a drive circuit for driving the display panel. The driving circuit may further include a gate driver for selecting one row of the gate lines, and a source driver for providing a pixel signal through the source line to a pixel corresponding to the selected gate line. Gate drivers typically operating in mixed voltage environments require circuitry to convert the different voltage levels they use.

1A is a block diagram of a gate driver 10 of the prior art. In the XGA / SXGA display system, the gate driver 10 may include 256 output channels OUT1-OUT256. The gate driver 10 includes an input level shifter 12, a shift register 14, a control device 16, an output level shifter 18, and an output buffer 20. The input level shifter 12 converts the voltage level of the input signal from the LCD controlled application semiconductor ("ASIC"). The input signal is a control signal such as a left / right shift control signal LR, an output enable signal OE and a global-on control signal XON, a clock signal SCLK, and a right data input / output. Data signals such as (DIOR) and left data input / output (DIOL). The shift register 14 shifts the start pulse of the signal DIOR or DIOL in accordance with the signal LR at the rising edge of the signal SCLK. The control device 16 decodes the signal from the shift register 14 and controls the operation mode of the gate driver 10 through the signals OE and XON. The output level shifter 18 converts the voltage level of the signal from the control device 16. The level converted signal is stored in the output buffer 20 to drive the display panel.

FIG. 1B is a diagram illustrating different voltage levels used for the gate driver 10. The input signal from the LCD control ASIC has a first voltage level in the range of V _SS to V _DD (eg, 0 V and 3.6 V, respectively). The input level shifter 12 converts the first voltage level to a second voltage level in the range of V _EE to V _AA (eg, -10 V, (-10 + (3.6 to 5)) V, respectively). The second voltage level is used for the input level shifter 12, the shift register 14, and the control device 16. The output level shifter 18 converts the second voltage level to a third voltage level in the range of V _EE to V _COM (eg, -10V and 25V, respectively). The third voltage level is used for the output level shifter 18 and the output buffer 20.

An example of a prior art output level shifter is described in US Patent Application Publication No. 2002-0135555 (hereinafter referred to as the '555 patent application) of "Single-Ended High-Voltage Level Shifter for a TFT-LCD Gate Driver". . In particular, in FIG. 5 of the '555 patent application, a two level output level shifter 51 is disclosed. The level shifter 51 includes two high voltage transistors M1 and M2 for converting the voltage level of the input signal. The level shifter 51 reduces the chip area by incorporating the partial circuit 511. However, the partial circuit 511 has two different high voltage transistors M11 and M12 that operate in response to the global on control signals XON2 and XON3 to prevent the level shifter 51 from consuming a lot of static power. ). In addition, an additional level shifter is required to generate voltage levels for the signals XON2 and XON3. As a result, the level shifter 51 will be undesirably complicated and still occupy a large chip area.

Accordingly, the present invention is directed to circuits and methods that overcome one or more problems due to the limitations and disadvantages of the prior art.

A signal comprising a first state of a first voltage level and a second state of a second voltage level, in order to achieve these and other advantages, and in accordance with the object of the invention as implemented and broadly described, A first high voltage transistor comprising a first power supply providing a voltage level, a gate electrode connected to the first power supply, a first electrode receiving a signal, and a second electrode connected to the node, and a third voltage level A circuit for converting a voltage level in a liquid crystal display panel is provided, comprising: a second power supply; and a second high voltage transistor comprising a first electrode connected to the second power supply and a second electrode connected to the node. Here, the voltage level of the node is pulled to approximately the third voltage level in response to the first state of the signal, and pulled to approximately the second voltage level in response to the second state of the signal.

Furthermore, according to the present invention, a current source for providing a reference voltage and a plurality of circuits for converting voltage levels in the liquid crystal display panel, each circuit comprising a first state of the first voltage level and a second voltage level of the second voltage level. A first comprising a signal comprising a two state, a first power supply providing a first voltage level, a gate electrode connected to the first power supply, a first electrode receiving a signal, and a second electrode connected to the node A second transistor comprising a transistor, a second power supply providing a third voltage level, a gate electrode biased at a reference voltage, a first electrode connected to the second power supply, and a second electrode connected to the node; A driving circuit for a liquid crystal display panel is provided, wherein the voltage level at the node is pulled to approximately a third voltage level in response to the first state of the signal and in response to the second state of the signal. In response to approximately the second voltage level.

According to the present invention, there is also provided a first power supply for providing a first voltage level, a second power supply for providing a second voltage level, a third power supply for providing a third voltage level, and a first power supply. A first transistor comprising an electrode connected to the second transistor; a second transistor comprising an electrode connected to the second power supply; a third transistor comprising an electrode connected to the third power supply; and a first state and a second state. Turning on and turning the first transistor in response to a first input signal, a second input signal including a first state and a second state, an output signal, and first and second states of the first input signal, respectively. A first device to turn off, a second device to turn on and off a second transistor in response to the first and second states of the second input signal, respectively, and a first state to decode the first and second input signals. And a deco including a second state A circuit for converting a voltage level in a liquid crystal display panel comprising a decoder for providing a signal and a third device for turning on and off a third transistor in response to first and second states of the decoded signal, respectively. Is provided.

Further, according to the present invention, there is provided a method of providing a current source that provides a reference voltage, providing a signal comprising a first state of a first voltage level and a second state of a second voltage level; Providing a first power supply comprising: a first transistor comprising a gate electrode connected to the first power supply, a first electrode receiving a signal, and a second electrode connected to the node; Providing a second power supply providing a third voltage level, a second transistor comprising a gate electrode biased at a reference voltage, a first electrode connected to a second power supply, and a second electrode connected to a node And pulling the voltage level of the node to approximately a third voltage level in response to the first state of the signal, and bringing the node's voltage level to approximately a second voltage level in response to the second state of the signal. A method of converting a voltage level in a liquid crystal display panel is provided, which includes pulling up.

Further, according to the present invention, there is provided a method of providing a first power supply that provides a first voltage level, providing a second power supply that provides a second voltage level, and a third providing a third voltage level. Providing a power supply, providing a first transistor comprising an electrode coupled to the first power supply, providing a second transistor comprising an electrode coupled to the second power supply, and providing a third power supply; Providing a third transistor comprising an electrode coupled to the second transistor; providing a first input signal comprising a first state and a second state; and providing a second input signal comprising a first state and a second state. Providing an output signal, providing a first device for turning on and turning off a first transistor in response to first and second states of a first input signal, and a second input Providing a second device for turning on and off a second transistor in response to a first state and a second state of the signal, respectively, and decoding the first and second input signals to determine the first state and the second state. Providing a decoder for providing a decoded signal comprising: providing a third device for turning on and off a third transistor in response to first and second states of the decoded signal, respectively; A method of converting voltage levels in a panel is provided.

Additional objects and advantages of the invention will be set forth in part in the description which follows, and in part will be obvious from the description, and will be learned by practice of the invention. The objects and advantages of the invention will be realized and attained by means of the elements and combinations particularly pointed out in the appended claims.

As claimed, both the foregoing general description and the following detailed description are exemplary only and are not intended to limit the invention.

The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate one embodiment of the invention and, together with the description, serve to explain the theory of the invention.

Hereinafter, embodiments of the present invention will be described in detail, examples of which are illustrated in the accompanying drawings. Wherever possible, the same reference numerals will be used throughout the drawings to refer to the same or similar components.

2 is a circuit diagram showing a circuit 10 for converting a voltage level according to an embodiment of the present invention. The circuit 10 provides the two level output signal V _OUT to one of the 256 output channels of a gate driver (not shown), for example, in response to the two level input signal V _IN . The circuit 10 includes a shift register 12, a level shifter 14, and an output buffer 16. The shift register 12 further includes, for example, a latch element 12-2 of the D flip flop and an inverter 12-4. The input signal V _IN comprises a first state of a first voltage level, for example V _AA , and a second state of a second voltage level, for example V _EE . Inverter 12-4 provides an inverted signal of the input signal V _IN at the output terminal, node A.

The level shifter 14 further includes a first transistor 14-2 and a second transistor 14-4. The first transistor 14-2 has a gate electrode (no reference number) connected to the first power supply 18 providing a first voltage level (V _AA ), a first electrode (no reference number) connected to the node A, And a second electrode (no reference number) connected to Node B. The second transistor 14-4 is a first electrode connected to a second power supply 20 which provides a third voltage level which is a gate electrode (no reference number) connected to the reference voltage V _R , for example V _COM . An electrode (no reference number), and a second electrode (no reference number) connected to node B. The reference voltage (V _R ) generated by the current source is provided globally to each of the 256 output channels of the gate driver. The voltage level of the reference voltage V _R is predetermined so that the second transistor 14-4 is turned on.

In one embodiment according to the present invention, the first transistor 14-2 is a high voltage n-channel metal oxide semiconductor (NMOS) transistor, and the second transistor 14-4 is a high voltage p-channel metal oxide semiconductor (PMOS). Transistor. Since the first and second transistors 14-2 and 14-4 respectively function as switches and pull-up elements, these transistors can preferably be designed to be smaller.

The output buffer 16 further includes a PMOS transistor 16-2 and an NMOS transistor 16-4, which together form one complementary inverter. The PMOS transistor 16-2 has a gate electrode (no reference number) connected to the node B, a first electrode (no reference number) connected to the second power supply device 20, and a node serving as an output terminal of the circuit 10. A second electrode connected to C (no reference number). The NMOS transistor 16-4 is a third power supply providing a gate electrode (no reference number) connected to node B, a first electrode (no reference number) connected to node C, and a second voltage level (V _EE ). A second electrode (without reference number) connected to 22;

In response to the first state of the input signal V _IN or the second state of the inverted signal present at node A, the first transistor 14-2 is turned on. The voltage level at node B is pulled to approximately the second voltage level V _EE , which then turns on the PMOS transistor 16-2 and turns off the NMOS transistor 16-4. The voltage level at node C, ie V _OUT, is approximately the third voltage level V _COM .

In response to the second state of the input signal V _IN or the first state of the inverted signal present at node A, the first transistor 14-2 is turned off. The voltage level at node B is pulled to approximately the third voltage level V _COM , and then turns off PMOS transistor 16-2 and turns on NMOS transistor 16-4. The voltage level V _OUT at node C is approximately the second voltage level V _EE . As a result, the input voltage levels V _AA , V _EE are converted to output voltage levels V _COM , V _EE , respectively.

3 is a circuit diagram showing a circuit 30 for converting a voltage level according to another embodiment of the present invention. The circuit 30 includes a voltage generator 32, a shift register and control device 34, a level shifter 14, and an output buffer 16. The voltage generator 32, which provides a reference voltage V _{R for} both output channels of the gate driver, includes a high voltage transistor 32-2 and a current source 32-4. The transistor 32-2 is a gate electrode (no reference number) connected to the gate electrode of the second transistor 14-4 of the level shifter 14, and a first electrode (reference number) connected to the second power supply V _COM . None), and a second electrode (no reference number) connected to the current source 32-4. The shift register and control device 34 includes a latch element 12-2, an AND gate 34-2, and a NOR gate 34-4. The circuit 30 provides the two level output signal V _OUT to, for example, one of the 256 output channels of the gate driver in response to the two level input signal V _IN .

The gate driver will operate in one of three modes: normal mode, OFF mode, and ON mode. The first and second control signals XON, OE, both including a first state of the first voltage level V _AA and a second state of the second voltage level V _EE , select one of three modes. When provided. The gate driver operates in the normal mode when the first control signal XON of the second state V _EE and the second control signal OE of the first state V _AA are provided. In the normal mode, in response to the first state V _AA of the input signal V _IN , the output voltage level V _OUT is pulled to approximately the third voltage level V _COM . In response to the second state V _EE of the input signal V _IN , the output voltage level V _OUT is pulled to approximately the second voltage level V _EE .

A gate driver, a second state (V _EE) of claim 1 when provided with a second control signal (OE) of the control signal (XON) and a second state (V _EE) of, and operates in OFF mode. In the OFF mode, the output of the AND gate 34-2 is a logic value of 0 or V _EE , regardless of the state of the input signal V _IN . In response to the control signals XON and OE at the V _EE level present at the input terminal, the NOR gate 34-4 provides a logic value of 1 or V _AA at the output terminal. Subsequently, the output voltage level V _OUT is pulled to approximately the second voltage level V _EE .

The gate driver operates in the ON mode regardless of the state of the second control signal OE and the input signal V _IN when the first control signal XON of the first state V _AA is provided. . In the ON mode, the output of the NOR gate 34-4 is logical 0 or V _EE . Subsequently, the output voltage level V _OUT is pulled to approximately the third voltage level V _COM . The first control signal XON as a global signal will turn on all of the output channels of the gate driver when the first state V _AA is asserted, and as a result, the gate driver is undesirably subjected to large static currents. Will flow. In order to protect the gate driver from unwanted static current, in particular, in the embodiment shown in FIG. 3, the current source 32-4 is cut off in response to the first state of the first control signal XON.

4 is a circuit diagram showing a circuit 50 for converting a voltage level according to another embodiment of the present invention. The circuit 50 includes a voltage generator 32, a shift register and control device 52, a level shifter 14, and an output buffer 16. The shift register and control device 52 further includes a latch element 12-2 and low voltage transistors M1-M6. The circuit 50 provides the two level output signal V _OUT to one of the 256 output channels of the gate driver, for example in response to the two level input signal V _IN . The gate driver operates in the normal mode when the first control signal XON of the second state V _EE and the second control signal OE of the first state V _AA are provided. In the normal mode, transistors M1 and M6 are turned on and transistors M3 and M5 are turned off. In response to the first state V _AA of the input signal V _IN , the transistor M4 is turned on and the transistor M2 is turned off. The output voltage level of node D is pulled to approximately the second voltage level V _EE , and the output voltage level V _OUT is pulled to approximately the third voltage level V _COM . In response to the second state V _EE of the input signal V _IN , the transistor M4 is turned off and the transistor M2 is turned on. The output voltage level at node D is pulled to approximately the first voltage level V _AA , and the output voltage level V _OUT is pulled to approximately the second voltage level V _EE .

A gate driver, a second state (V _EE) of claim 1 when provided with a second control signal (OE) of the control signal (XON) and a second state (V _EE) of, and operates in OFF mode. In the OFF mode, transistors M1 and M3 are turned on and transistors M5 and M6 are turned off. Regardless of the state of the input signal V _IN , the voltage level at node E is pulled to approximately the first voltage level V _AA , and the output voltage level VOUT is pulled to approximately the second voltage level V _EE . do.

The gate driver operates in the ON mode regardless of the state of the second control signal OE of the input signal V _IN when the first control signal XON of the first state V _AA is provided. . In the ON mode, transistor M1 is turned off and transistor M5 is turned on. The voltage level at node E is pulled to approximately the second voltage level V _EE , and the output voltage level V _OUT is pulled to approximately the third voltage level V _COM . In order to protect the gate driver from large scale static current, current source 32-4 is cut off in response to the first state of first control signal XON.

5 is a circuit diagram showing a circuit 70 for converting a voltage level according to another embodiment of the present invention. The circuit 70 provides a three level output signal V _OUT to, for example, one of the 256 output channels of the gate driver in response to the two level input signals V _IN1 , V _IN2 . Both input signals V _IN1 , V _IN2 include a first state of a first voltage level, eg, V _AA , and a second state of second voltage level V _EE . The circuit 70 includes a shift register and decoder 72, a level shifter 74, and an output buffer 76. The shift register and decoder 72 further includes a latch element 72-2, a first inverter 72-4, a second inverter 72-6, and a decoder 72-8. In a particular embodiment, decoder 72-8 includes a NOR gate.

The level shifter 74 further includes first, second, and third sets of shifter devices (without reference numerals). The first set of shifter devices includes transistors M1A and M1B, each of which functions as a switch and a pull-up device. Similarly, the second set of shifter devices includes transistors M2A and M2B, and the third set of shifter devices includes transistors M3A and M3B. The second set of shifter devices further includes an inverter 74-2 that blocks static current from flowing through the transistor M2B. In a particular embodiment, inverter 74-2 includes a NOT gate. Each of the transistors M1A, M2A, M3A has a gate electrode (without reference number) connected to a first power supply providing a first voltage level V _AA , a first inverter 72-4, and a second inverter 72. -6) or an electrode (no reference number) connected to one of the decoders 72-8. Each of the transistors M1B, M2B, M3B includes a gate electrode (without reference numeral) connected to a reference voltage V _R provided by a current source (not shown).

The output buffer 76 further includes first, second, and third transistors M1C, M2C, M3C corresponding to the first, second, and third sets of shifter devices, respectively. The first transistor M1C includes an electrode (no reference number) connected to a second power supply providing a third voltage level V _COM . The second transistor M2C includes an electrode (without reference number) connected to a third power supply providing a second voltage level V _EE . The third transistor M3C includes an electrode (no reference number) connected to a fourth power supply providing a fourth voltage level V _L. The fourth voltage V _L acts as an off control voltage of the LCD element. In one embodiment according to the invention, V _L is approximately in the range of V _EE to (V _EE + 10V).

In response to V _IN1 at V _AA level and V _IN2 at V _EE level, transistor M1C is turned on and transistors M2C and M3C are turned off. The output voltage V _OUT is pulled to approximately V _COM . In response to V _IN1 at the V _EE level and V _IN2 at the V _AA level, the transistors M2C are turned on and the transistors M1C, M3C are turned off. The output voltage V _OUT is _pulled to approximately V _EE . To V _EE level of V _IN1 and V _EE levels in response to the V _IN2, transistors (M3C) is turned on, are turned off transistor (M1C, M2C). The output voltage V _OUT is pulled to approximately V _L. In response to the level of V _AA V _IN1 and V _{IN2 AA} level of the V, the transistor (M1C, M2C) is turned on and the transistors (M3C) is turned off. The output voltage V _OUT is pulled to approximately V _L.

The present invention also provides a method of converting a voltage level in a liquid crystal display panel. A current source 32-4 is provided that provides a reference voltage V _R. A signal is provided that includes a first state of a first voltage level V _AA and a second state of a second voltage level V _EE . A first power supply 18 is provided that provides a first voltage level V _AA . A first transistor 14-2 is provided that includes a gate electrode connected to the first power supply 18, a first electrode receiving a signal, and a second electrode connected to the node B. A second power supply 20 is provided that provides a third voltage level V _COM . A second transistor 14-4 is provided that includes a gate electrode biased at a reference voltage V _R , a first electrode connected to the second power supply 20, and a second electrode connected to the node B. The voltage level at node B is pulled to approximately the third voltage level V _COM in response to the first state of the signal. The voltage level at node B is pulled to approximately the second voltage level V _EE in response to the second state of the signal.

In one embodiment according to the invention, a first control signal XON is provided comprising a first state of a first voltage level V _AA and a second state of a second voltage level V _EE . A second control signal OE is provided that includes a first state of the first voltage level V _AA and a second state of the second voltage level V _EE . The current source 32-4 is turned off in response to the first state V _AA of the first control signal XON.

Moreover, this invention provides the method of converting the voltage level in a liquid crystal display panel. A first power supply V _COM , a second power supply V _EE , and a third power supply V _L are provided. A first transistor M1C is provided that includes an electrode connected to a first power supply V _COM . A second transistor M2C is provided that includes an electrode connected to a second power supply V _EE . A third transistor M3C is provided that includes an electrode connected to a third power supply V _L. A first input signal V _IN1 is provided that includes a first state and a second state. A second input signal V _IN2 is provided that includes a first state and a second state. The output signal V _OUT is provided. In response to the first and second states of the first input signal V _IN1 , respectively, a first device is provided for turning on and off the first transistor M1C. In response to the first and second states of the second input signal V _IN2 , a second device is provided for turning on and off the second transistor M2C. A decoder 72-8 is provided that decodes the first and second input signals V _IN1 , V _IN2 , and provides a decoded signal comprising a first state and a second state. In response to the first and second states of the decoded signal, respectively, a third apparatus for turning on and off the third transistor M3C is provided.

In one embodiment according to the invention, each of the first, second and third devices comprises a first transistor 14-14 comprising a gate electrode connected to a fourth power supply providing a fourth voltage level V _AA . 2) and a second transistor 14-4 including an electrode connected to the first power supply device V _COM .

The voltage level V _OUT of the output signal is approximately at the first voltage level V _COM in response to the first state of the first input signal V _IN1 and the second state of the second input signal V _IN2 . Unpacked The voltage level V _OUT of the output signal is approximately at the second voltage level V _EE in response to the second state of the first input signal V _IN1 and the second state of the second input signal V _IN2 . Unpacked The voltage level V _OUT of the output signal is _pulled to approximately the third voltage level V _L in response to the first and second input signals V _IN1 and V _IN2 in the same state.

Those skilled in the art will recognize other embodiments of the invention in view of the description and practice of the invention described herein. In the spirit and scope of the invention as indicated in the following claims, these descriptions and examples are to be considered merely illustrative.

According to the present invention, it is possible to provide a voltage level converting circuit and a method in an improved liquid crystal display panel.

Claims (27)

A circuit for converting a voltage level in a liquid crystal display panel, A current source providing a reference voltage, A signal comprising a first state of a first voltage level and a second state of a second voltage level; A first power supply providing the first voltage level; A first high voltage transistor comprising a gate electrode connected to the first power supply device, a first electrode receiving the signal, and a second electrode connected to a node; A second power supply providing a third voltage level; A second high voltage transistor including a gate electrode biased at the reference voltage, a first electrode connected to the second power supply device, and a second electrode connected to the node; The voltage level of the node is pulled to approximately the third voltage level in response to the first state of the signal and to approximately the second voltage level in response to the second state of the signal Circuit. 2. The voltage level converting circuit of claim 1, further comprising a complementary inverter coupled between the second power supply and a third power supply providing the second voltage level. The method of claim 2, wherein the complementary inverter, A first transistor comprising a gate electrode connected to the node, an electrode connected to the second power supply device, And a second transistor comprising a gate electrode connected to the node and an electrode connected to the third power supply. delete 2. The voltage level converting circuit of claim 1, further comprising a control signal comprising a first state of the first voltage level and a second state of the second voltage level. 6. The voltage level converting circuit as claimed in claim 5, wherein the current source is turned off in response to the first state of the control signal. As a drive circuit in a liquid crystal display panel, A current source providing a reference voltage, A plurality of circuits for converting a voltage level in the liquid crystal display panel; Each of the plurality of circuits, A signal comprising a first state of a first voltage level and a second state of a second voltage level; A first power supply providing the first voltage level; A first transistor comprising a gate electrode connected to the first power supply device, a first electrode receiving the signal, and a second electrode connected to a node; A second power supply providing a third voltage level; A second transistor including a gate electrode biased at the reference voltage, a first electrode connected to the second power supply device, and a second electrode connected to the node, Wherein the voltage level of the node is pulled to approximately the third voltage level in response to the first state of the signal, and pulled to approximately a second voltage level in response to the second state of the signal. Circuit. 8. The apparatus of claim 7, further comprising: a first control signal comprising a first state of a first voltage level and a second state of a second voltage level; And a second control signal comprising a first state of the first voltage level and a second state of the second voltage level. 9. The driving circuit of claim 8, wherein the current source is turned off in response to the first state of the first control signal. 9. The driving circuit of claim 8, further comprising an AND gate to receive the second control signal. The driving circuit of claim 8, further comprising a NOR gate to receive the first control signal. 9. The driving circuit according to claim 8, wherein said signal is brought into said first state in response to said second state of said first and second control signals. 9. The drive circuit according to claim 8, wherein said signal is brought into said second state in response to said first state of said first control signal. A circuit for converting a voltage level in a liquid crystal display panel, A first power supply providing a first voltage level; A second power supply providing a second voltage level; A third power supply providing a third voltage level; A first transistor comprising an electrode connected to the first power supply; A second transistor including an electrode connected to the second power supply device; A third transistor comprising an electrode connected to the third power supply device; A first input signal comprising a first state and a second state; A second input signal comprising a first state and a second state; Output signal, A first device for turning on and off the first transistor in response to the first and second states of the first input signal, respectively; A second device for turning on and off the second transistor in response to the first and second states of the second input signal, respectively; A decoder which decodes the first and second input signals and provides a decoded signal comprising a first state and a second state; And a third device for turning on and off the third transistor in response to the first and second states of the decoded signal, respectively. The method of claim 14, wherein each of the first, second, and third devices, A first transistor comprising a gate electrode connected to a fourth power supply providing a fourth voltage level; And a second transistor comprising an electrode coupled to the first power supply. 15. The method of claim 14, wherein the voltage level of the output signal is pulled to approximately the first voltage level in response to the first state of the first input signal and the second state of the second input signal. Voltage level conversion circuit. 15. The method of claim 14, wherein the voltage level of the output signal is pulled to approximately the second voltage level in response to the second state of the first input signal and the first state of the second input signal. Voltage level conversion circuit. 15. The voltage level converting circuit as claimed in claim 14, wherein the voltage level of the output signal is pulled to approximately the third voltage level in response to the first and second signals in the same state. 15. The voltage level converting circuit of claim 14, wherein the decoder further comprises a logic NOR gate. As a method of converting a voltage level in a liquid crystal display panel, Providing a current source providing a reference voltage; Providing a signal comprising a first state of a first voltage level and a second state of a second voltage level; Providing a first power supply providing the first voltage level; Providing a first transistor comprising a gate electrode connected to the first power supply device, a first electrode receiving the signal, and a second electrode connected to a node; Providing a second power supply providing a third voltage level; Providing a second transistor comprising a gate electrode biased at a reference voltage, a first electrode coupled to the second power supply, and a second electrode coupled to the node; Pooling the voltage level of the node to an approximately third voltage level in response to the first state of the signal; Pooling the voltage level of the node to an approximately second voltage level in response to the second state of the signal. 21. The method of claim 20, further comprising: providing a first control signal comprising a first state of a first voltage level and a second state of a second voltage level; And providing a second control signal comprising a first state of the first voltage level and a second state of the second voltage level. 22. The method of claim 21, further comprising turning off the current source in response to the first state of the first control signal. As a method of converting a voltage level in a liquid crystal display panel, Providing a first power supply providing a first voltage level; Providing a second power supply providing a second voltage level; Providing a third power supply providing a third voltage level; Providing a first transistor comprising an electrode coupled to the first power supply; Providing a second transistor comprising an electrode coupled to the second power supply; Providing a third transistor comprising an electrode coupled to the third power supply; Providing a first input signal comprising a first state and a second state; Providing a second input signal comprising a first state and a second state; Providing an output signal, Providing a first device for turning on and off the first transistor in response to the first and second states of the first input signal, respectively; Providing a second device for turning on and off the second transistor in response to the first and second states of the second input signal, respectively; Providing a decoder which decodes the first and second input signals and provides a decoded signal comprising a first state and a second state; And providing a third device to turn on and turn off the third transistor in response to the first and second states of the decoded signal, respectively. 24. The method of claim 23, further comprising: a first transistor comprising a gate electrode connected to a fourth power supply providing a fourth voltage level, and a second transistor comprising an electrode connected to the first power supply. And providing each of the second and third devices. 24. The method of claim 23, further comprising: pulling a voltage level of the output signal to approximately the first voltage level in response to the first state of the first input signal and the second state of the second input signal. The voltage level conversion method further comprising. 24. The method of claim 23, further comprising: pulling a voltage level of the output signal to approximately the second voltage level in response to the second state of the first input signal and the first state of the second input signal. The voltage level conversion method further comprising. 24. The method of claim 23, further comprising pulling the voltage level of the output signal to approximately the third voltage level in response to the first and second signals in the same state.

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