KR100594231B1 - External Input/Output data control apparatus improving system performance using automatically set control parameters and method thereof - Google Patents

Abstract

Disclosed are an external input / output data control apparatus and a method for automatically improving system performance by setting control parameters. The external I / O data control device includes a logic for automatically finding and setting control parameter information necessary for accessing the external I / O device when the external I / O device is accessed for the first time after the system is powered on. To improve. In other words, the user does not need to directly find and input the control parameter information for smoothly operating the external input / output device every time the system is designed. Accordingly, the human error can be eliminated, and the control parameter information is Since it is set to an appropriate value for the input / output device, the system can be operated efficiently.

Description

External input / output data control apparatus improving system performance using automatically set control parameters and method

BRIEF DESCRIPTION OF THE DRAWINGS In order to better understand the drawings cited in the detailed description of the invention, a brief description of each drawing is provided.

1 is a block diagram illustrating a conventional external input / output data control apparatus.

2 is a block diagram illustrating an external input / output data control apparatus according to an embodiment of the present invention.

3A and 3B are flowcharts for describing an operation of an external input / output data control apparatus.

The present invention relates to an apparatus for relaying transmission of external input / output data, and more particularly, to an input / output data control apparatus and a method for efficiently relaying data transmission and reception between a system and an external device.

1 is a block diagram illustrating a conventional external input / output data control apparatus. Referring to FIG. 1, a conventional external input / output data control device provided between a system bus and an external bus includes a system bus interface logic 110, a timing and control register unit 120, and an input / output control logic 130. do. Here, the input / output control logic 130 includes a main state machine logic 131, a control signal generation logic 133, and a signal input / output logic 135. In such a conventional external input / output data control device, control parameter information CP necessary for accessing an external I / O device such as a memory is stored in the timing and control register unit 120. The control parameter information CP is default parameter values required for accessing an external input / output device or parameters set by a user in register settings. Such parameter values are digital information about the size of data to be transmitted, an access cycle time, etc. in order to access the external I / O device according to the size of the external I / O device such as a memory.

In the external I / O data control device as described above, when external I / O device access is required, the main state machine logic 131 may generate the control signal generation logic in response to the control signal CON received from the system bus interface logic 110. 133 is operated. Accordingly, the control signal generation logic 133 loads the control parameter information CP from the timing and control register unit 120 to drive the signal input / output logic 135. In response to the address EXTADDR, data EXTDATA, and control signal EXTCON output from the signal input / output logic 135, the external input / output device reads or writes the corresponding data. That is, when a predetermined processor requests access to an external input / output device connected to an external bus by transmitting an internal control signal INTCON through a system bus, the external input / output device reads or writes the corresponding data. write).

In many digital systems having an external input / output device such as a memory to store data or operating using the data, management of the external input / output device is important. There may be one such external input / output device, but many complex digital systems have several external input / output devices composed of multiple banks. As described above, the external I / O data control device managing the plurality of external I / O devices includes a timing and control register unit 120 storing the control parameter information CP, as illustrated in FIG. 1. Support access to However, in the conventional external input / output data control apparatus, in order to smoothly operate each of the external input / output devices, the user must find the appropriate control parameter information CP and input the input directly to the timing and control register unit 120. Therefore, a lot of errors can be generated in this process, the user has a problem that a lot of time and effort should be taken.

Accordingly, the technical problem to be achieved by the present invention is to add a logic for automatically finding and setting the control parameter information required to access the external I / O device for the first time after the system is powered on. The present invention provides an external input / output data control device and method for improving system performance.

An external input / output data control apparatus according to the present invention for achieving the above technical problem is characterized by comprising a system bus interface logic, a timing and control register unit, and an input and output control logic.

The system bus interface logic receives and latches and outputs system bus interface signals. The timing and control register unit stores default control parameter information and stores final control parameter information extracted by an initial setting process. The input / output control logic performs the initial setting process by using the default control parameter information, extracts the last control parameter information to be used when accessing an external input / output device, and stores the final control parameter information in the timing and control register. Control the steady state access to the external input / output device according to information and the system bus interface signals output from the system bus interface logic.

The input / output control logic includes main state machine logic, temporary parameter register, search logic, write operation generation logic, write data buffer, read operation generation logic, read data buffer, comparison logic, control signal generation logic, and signal input / output logic. Characterized in that.

The main state machine logic generates and outputs a main control signal for controlling the initial setting process upon initial access to the external input / output device after power-on, and on the system bus interface signals when the external state approaches the external input / output device. In response, a main control signal for controlling the steady state access is generated and output. The temporary parameter register first stores the default control parameter information in response to initial control information, updates and stores the temporary search buffer value generated during the initial setting process, and stores the final control stored after completion of the initial setting process. Parameter information is transmitted to the timing and control register unit. The search logic receives the default control parameter information in response to the initial control information, searches for and stores each of a maximum value and a minimum value of a predetermined parameter belonging to the default control information, and the temporary output output from the temporary parameter register during the initial setting process. The search buffer value is searched and the maximum value or the minimum value is updated and stored. The write operation generation logic generates and outputs a write operation signal in response to the initial control information. The write data buffer outputs default write data in response to the write operation signal. The read operation generation logic generates and outputs a read operation signal in response to the initial control information. The read data buffer stores read data in response to the read operation signal. The comparison logic outputs comparison information having different logic states depending on whether the default write data and the read data are the same or not. The control signal generation logic generates the initial control information in the initial setting process in response to the main control signal, updates the temporary search buffer value in response to the logic state of the comparison information, and, upon approaching the steady state, Outputs steady state I / O control information. The signal input / output logic receives the default write data and outputs the read data received from the external input / output device in response to the initial control information, and outputs the read data input from the external input / output device in response thereto. The controller outputs a control signal, an address, and data for controlling the external input / output device.

The temporary search buffer value is, when the comparison information is a first logical state, the equation,

Temporary search buffer value = (temporary parameter register value + parameter maximum value) / 2

It is characterized by being updated by. In addition, the temporary search buffer value, when the comparison information is a second logic state, the equation,

Temporary search buffer value = (temporary parameter register value + parameter minimum value) / 2

It is characterized by being updated by.

In accordance with another aspect of the present invention, there is provided a method for controlling external input / output data, the method including a first register for storing default control parameter information. It is characterized by including.

That is, the method for controlling external input / output data according to the present invention comprises the steps of: receiving and latching and outputting system bus interface signals; Extracting final control parameter information to be used when accessing an external input / output device by performing an initial setting process using the default control parameter information; Storing the final control parameter information extracted by the initial setting process in the first register; And controlling a steady state access to the external input / output device according to the last control parameter information and the system bus interface signals.

In order to fully understand the present invention, the operational advantages of the present invention, and the objects achieved by the practice of the present invention, reference should be made to the accompanying drawings which illustrate preferred embodiments of the present invention and the contents described in the accompanying drawings.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. Like reference numerals in the drawings denote like elements.

2 is a block diagram illustrating an external input / output data control apparatus according to an embodiment of the present invention. Referring to FIG. 2, the external input / output data control device includes a system bus interface logic 210, a timing and control register 220, and an input / output control logic. output control logic 230.

The system bus interface logic 210 receives and latches and outputs system bus interface signals INTADDR, INTDATA, and INTCON. The system bus interface signals INTADDR, INTDATA, and INTCON are composed of an internal address INTADDR, internal data INTDATA, and an internal control signal INTCON, which are external I / O devices in which a predetermined processor is connected to an external bus. These are the signals received through the system bus when requesting access. The predetermined processor is connected to a system bus, and the external input / output device is connected to an external bus. As described above, a predetermined processor requests access to an external input / output device to read or write corresponding data required from the external input / output device.

The timing and control register unit 220 stores default control parameter information DCP and stores final control parameter information FCP extracted by an initial setting process. The default control parameter information DCP may be stored using the system bus interface signals INTADDR, INTDATA, and INTCON, or may be stored according to a user's setting.

When a predetermined processor approaches the external input / output device for the first time after power-on, the input / output control logic 230 performs the initial setting process, and after performing the initial setting process, access to the second and subsequent external input / output devices after the execution of the initial setting process. Controls steady state access. That is, the input / output control logic 230 performs the initial setting process by using the default control parameter information DCP, extracts the final control parameter information FCP to be used when accessing an external input / output device, and generates the timing and It is stored in the control register unit 220. In addition, the input / output control logic 230 may control the external input / output device according to the final control parameter information FCP and the system bus interface signals INTADDR, INTDATA, and INTCON output from the system bus interface logic 210. Controls steady state access to

As illustrated in FIG. 2, the input / output control logic 230 may include a main state machine logic 231, a temporary parameter register 232, and a value searching logic. 233, write operation generation logic 234, write data buffer 235, read operation generation logic 236, read data buffer a buffer 237, comparison logic 238, control signal generation logic 239, and signal input / output logic 240.

The main state machine logic 231 generates and outputs a main control signal MAINCON for controlling the initial setting process upon initial access to the external input / output device after power on, and when the normal state approaches the external input / output device. In response to system bus interface signals INTADDR, INTDATA, INTCON, a main control signal MAINCON for controlling the steady state access is generated and output. The internal control signal INTCON, which initially accesses the external input / output device after power-on may be determined by the control signal CON which is output after being latched by the system interface logic. In addition, the main state machine logic 231 outputs a wait signal WATE to a system bus when generating the main control signal MAINCON for controlling the initial setup process, and when the initial setup process is completed, waits. Output a signal to the system bus to release the signal (WATE).

The temporary parameter register 232 stores the default control parameter information DCC for the first time in response to the initial control information PECON, updates the temporary search buffer value generated during the initial setting process, and stores the initial search buffer value. The final control parameter information FCP stored after completion of the setting process is transferred to the timing and control register unit 220. The temporary search buffer may be provided in the control signal generation logic 239 or the like.

The search logic 233 receives the default control parameter information DCP in response to the initial control information, searches for and stores each of a maximum value MAX and a minimum value MIN of a predetermined parameter belonging to the initial control information, and stores the initial value. In the setting process, the temporary search buffer value output from the temporary parameter register 232 is searched and the maximum value MAX or the minimum value MIN is updated and stored.

The write operation generation logic 234 generates and outputs a write operation signal WOP in response to the initial control information PECON.

The write data buffer 235 outputs default write data DWD in response to the write operation signal WOP.

The read operation generation logic 236 generates and outputs a read operation signal ROP in response to the initial control information PECON.

The read data buffer 237 stores read data RD in response to the read operation signal ROP.

The comparison logic 238 outputs comparison information having different logic states depending on whether the default write data DWD and the read data RD are the same or not. When the default write data DWD and the read data RD are different from each other, the comparison information is in a first logic state (logical low state), and the default write data DWD and the read data RD are different from each other. In the same case, the comparison information is a second logic state (logical high state).

The control signal generation logic 239 generates the initial control information PECON in the initial setting process in response to the main control signal MAINCON and sets the temporary search buffer value in response to a logic state of the comparison information. And outputs steady state input / output control information (DSCON) when the steady state approaches. By the initial control information PECON, the temporary search buffer value is updated as shown in [Equation 1] when the comparison information is in the first logical state. Further, by the initial control information PECON, the temporary search buffer value is updated as shown in [Equation 2] when the comparison information is in the second logical state.

[Equation 1]

Temporary search buffer value = (temporary parameter register value + parameter maximum value) / 2

[Equation 2]

Temporary search buffer value = (temporary parameter register value + parameter minimum value) / 2

The signal input / output logic 240 receives the default write data DWD in response to the initial control information PECON and outputs the read data RD to the outside and correspondingly outputs the read data RD input from the external input / output device. The controller outputs the control signal EXTCON, the address EXTADDR, and the data EXTDATA that control the external input / output device in response to the steady state input / output control information DSCON.

Hereinafter, an operation of performing an initial setting process of the external input / output data control apparatus according to an embodiment of the present invention will be described in detail.

3A and 3B are flowcharts for describing an operation of the external input / output data control device of FIG. 2. 3A and 3B, a process of performing an initial setting process after powering on the external input / output data control device of FIG. 2 is shown. First, when a predetermined processor attempts to access an external input / output device after power is turned on (S311), the main state machine logic 231 generates a main control signal MAINCON for controlling an initial setting process, and at this time, the standby The signal WATE is output to the system bus (S313). Accordingly, the temporary parameter register 232 first stores the default control parameter information DCP in response to the initial control information PECON, and the search logic 233 stores the decode control in response to the initial control information PECON. The pulse control parameter information DCP is received, and each of the maximum value MAX and the minimum value MIN of a predetermined parameter belonging thereto is searched for and stored (S315 to S317). Each of the maximum value MAX and the minimum value MIN may have a different value depending on the parameter. In response to the main control signal MAINCON, generating the initial control information PECON in the initial setting process is performed by the control signal generation logic 239. The process of searching for the maximum value MAX and the minimum value MIN corresponding to a predetermined parameter is common to all parameters, and they are updated with new values in repeat blocks S319 to S333. Parameters belonging to the default control parameter information (DCP) include the access cycle time parameter (TACC), the chip selection hold time parameter (TCOH), and the chip selection setup time parameter (chip). selection set up time parameter (TCOS), address set up time parameter (TACS), page address access time parameter (TPA), and more. There may be.

In the repetition period (S319 to S333), first, in order to set the access cycle time parameter (TACC) among the default control parameter information (DCP), by the initial control information (PECON) generated in the control signal generation logic (239). The parameter value of the temporary parameter register 232 is set as a temporary search buffer value (S319). However, the initial temporary search buffer values are, for example, when the maximum value MAX is 31 and the minimum value MIN is 0, their intermediate values, that is, 15 or 16. The temporary search buffer may be provided in the control signal generation logic 239. Again, the control signal generation logic 239 updates the temporary parameter register 232 with the temporary search buffer value generated in the initial setting process by the initial control information PECON, and accordingly the updated temporary parameter register ( In operation S321, the write operation generation logic 234 is driven with the value. The write operation generating logic 234 generates a write operation signal WOP in response to the initial control information PECON, and the write data buffer 235 responds to the default write data WOP in response to the write operation signal WOP. DWD) is output (S321). In this case, the signal input / output logic 240 receives the default write data DWD and outputs the output to the outside in response to the initial control information PECON, and receives the read data RD input from the external input / output device correspondingly. Output (S321). The read operation generation logic 236 generates and outputs a read operation signal ROP in response to the initial control information PECON, and the read data buffer 237 outputs signal input / output logic in response to the read operation signal ROP. The read data RD output from the 240 is stored (S323).

Meanwhile, according to the operations of the write operation generation logic 234 and the read operation generation logic 236, the comparison logic 238 determines whether the default write data DWD and the read data RD are the same or not. The comparison information having different logic states is output (S325). When the comparison information is in the first logic state, the control signal generation logic 239 determines whether the first access is after power-on, stores the temporary search buffer value as the minimum value when the first access occurs, and sets a predetermined flag indicating the first time. , Update the temporary search buffer value as shown in [Equation 1] (S335 ~ S339). When the comparison information is in the second logic state, the control signal generation logic 239 determines whether the first access is after power-on, stores the temporary search buffer value as the maximum value when the first access is made, and sets a predetermined flag indicating the first time. The temporary search buffer value is updated as shown in [Equation 2] (S327 to S331). However, when the comparison information is in the first logical state, since the external input / output device corresponds to a case in which the minimum value MIN of the access cycle time parameter TACC is to be larger, the temporary search buffer value is updated in a larger direction. The current temporary parameter register 232 value is updated to the minimum value MIN (S337). In addition, when the comparison information is in the second logic state, the external input / output device corresponds to a case in which the maximum value MAX of the access cycle time parameter TACC is to be smaller, so that the temporary search buffer value is smaller. The current temporary parameter register 232 is updated to the maximum value MAX (S329).

The temporary parameter register 232 value updated as described above is also stored in the predetermined temporary comparison register, and when the predetermined temporary comparison register value is equal to the temporary search buffer value, the access cycle time parameter (TACC) is used as the value of the temporary parameter register 232. ) Is completed, and setting of other parameters is continued (S329, S333). The predetermined temporary comparison register may be provided in the control signal generation logic 239.

For example, even when the chip select hold time parameter TCOH is set, the search logic 233 receives the default control parameter information DCP in response to the initial control information PECON, and determines that the predetermined parameter belonging to it is received. Each of the maximum value MAX and the minimum value MIN is searched for and stored (S341). Accordingly, when the repetition periods S319 to S333 as described above are performed, setting of the chip select hold time parameter TCOH to the value of the temporary parameter register 232 is completed (S343). Similarly, the chip selection setup time parameter (TCOS), the address setup time parameter (TACS), and the page address access time parameter (TPA) are set in the same manner (S345 to S355).

As such, when the initial setting process is completed, all parameters corresponding to the default control parameter information DCP are stored in the corresponding temporary parameter register 232, and the control signal generation logic 239 is stored in the initial control information PECON. Accordingly, the values stored in the temporary parameter register 232 are transferred to the timing and control register 220 as the final control parameter information FCP (S357). As such, when the initial setting process is completed, the main state machine logic 231 outputs a signal for releasing the wait signal WATE to the system bus (S359). Accordingly, the final control parameter information (FCP) becomes the parameter information at the steady state approach, and when the steady state access occurs from the processor, the control signal generation logic 239 outputs the steady state input / output control information (DSCON). The signal input / output logic 240 outputs a control signal EXTCON, an address EXTADDR, and data EXTDATA for controlling the external input / output device in response to the steady state input / output control information DSCON.

As described above, the external input / output data control apparatus according to an embodiment of the present invention, the input and output control logic 230 has logic for performing the initial setting process using the default control parameter information (DCP). The final control parameter information FCP to be used when accessing an external input / output device may be extracted and stored in the timing and control register unit 220.

As described above, optimal embodiments have been disclosed in the drawings and the specification. Although specific terms have been used herein, they are used only for the purpose of describing the present invention and are not intended to limit the scope of the invention as defined in the claims or the claims. Therefore, those skilled in the art will understand that various modifications and equivalent other embodiments are possible from this. Therefore, the true technical protection scope of the present invention will be defined by the technical spirit of the appended claims.

As described above, the external I / O data control device according to the present invention automatically finds control parameter information necessary for accessing the external I / O device when the external I / O device is accessed for the first time after the system is powered on. Logic setting is added to improve system performance. In other words, the user does not need to directly find and input the control parameter information for smoothly operating the external input / output device every time the system is designed. Accordingly, the human error can be eliminated. Since it is set to an appropriate value for the input / output device, the system can be operated efficiently.

Claims (8)

System bus interface logic for receiving and latching and outputting system bus interface signals; A timing and control register unit for storing default control parameter information and storing final control parameter information extracted by an initial setting process; And The initial control process is performed using the default control parameter information to extract the last control parameter information to be used when accessing an external input / output device, and store the final control parameter information in the timing and control register, and the final control parameter information and the system. And an input / output control logic for controlling a steady state access to the external input / output device according to the system bus interface signals output from the bus interface logic. The method of claim 1, wherein the input and output control logic, When the external access to the external input and output device for the first time after power-on generates and outputs a main control signal for controlling the initial setting process, and the normal state approach in response to the system bus interface signals when the normal state approaches the external input and output device Main state machine logic for generating and outputting a main control signal for controlling the controller; The default control parameter information is first stored in response to initial control information, updated and stored with a temporary search buffer value generated during the initial setting process, and the timing of the final control parameter information stored after completion of the initial setting process. And a temporary parameter register transferred to the control register unit. Receives the default control parameter information in response to the initial control information, searches for and stores each of the maximum and minimum values of predetermined parameters belonging to the default control information, and stores the temporary search buffer value output from the temporary parameter register during the initial setting process. Search logic for searching and updating and storing the maximum value or the minimum value; A write operation generation logic configured to generate and output a write operation signal in response to the initial control information; A write data buffer configured to output default write data in response to the write operation signal; Read operation generation logic for generating and outputting a read operation signal in response to the initial control information; A read data buffer configured to store read data in response to the read operation signal; Comparison logic for outputting comparison information having different logic states depending on whether the default write data and the read data are the same or not; In response to the main control signal, the initial control information is generated in the initial setting process, and the temporary search buffer value is updated in response to the logical state of the comparison information. A control signal generation logic to output; And In response to the initial control information, the default write data is received and output to the outside, and correspondingly, the read data input from the external input / output device is received and output, and in response to the steady state input / output control information, the external input / output And an input / output logic for outputting a control signal, an address, and data for controlling the device. The method of claim 2, wherein the temporary search buffer value, When the comparison information is in the first logic state, equation, Temporary search buffer value = (temporary parameter register value + parameter maximum value) / 2 External input and output data control device, characterized in that for updating. The method of claim 2, wherein the temporary search buffer value, When the comparison information is in the second logical state, Temporary search buffer value = (temporary parameter register value + parameter minimum value) / 2 External input and output data control device, characterized in that for updating. A method for controlling external input / output data, comprising: a first register for storing default control parameter information; Receiving and latching and outputting system bus interface signals; Extracting final control parameter information to be used when accessing an external input / output device by performing an initial setting process using the default control parameter information; Storing the final control parameter information extracted by the initial setting process in the first register; And And controlling a steady state access to the external input / output device according to the final control parameter information and the system bus interface signals. The method of claim 5, wherein the extracting of the last control parameter information comprises: Generating a main control signal for controlling the initial setting process upon initial access to the external input / output device after power on; The default control parameter information is first stored in a second register in response to initial control information, updated and stored with a temporary search buffer value generated in the initial setting process, and the final control parameter stored after completion of the initial setting process. Passing information to the first register; Receives the default control parameter information in response to the initial control information, searches for and stores each of the maximum and minimum values of a predetermined parameter belonging to the default control information, and stores the temporary search buffer value output from the second register during the initial setting process. Searching and updating and storing the maximum value or the minimum value; Generating and outputting a write operation signal in response to the initial control information; Outputting default write data in response to the write operation signal; Generating and outputting a read operation signal in response to the initial control information; Storing read data in response to the read operation signal; Outputting comparison information having different logic states depending on whether the default write data and the read data are the same or not; In response to the main control signal, generating the initial control information in the initial setting process and updating the temporary search buffer value in response to a logic state of the comparison information; And And receiving the default write data and outputting the read data to the outside in response to the initial control information, and receiving and outputting the read data input from the external input / output device in response thereto. The method of claim 6, wherein the temporary search buffer value, When the comparison information is in the first logic state, equation, Temporary search buffer value = (temporary parameter register value + parameter maximum value) / 2 External input and output data control method, characterized in that for updating. The method of claim 6, wherein the temporary search buffer value, When the comparison information is in the second logical state, Temporary search buffer value = (temporary parameter register value + parameter minimum value) / 2 External input and output data control method, characterized in that for updating.

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