KR100593146B1 - Method of forming a gate in a semiconductor device - Google Patents

Method of forming a gate in a semiconductor device Download PDF

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KR100593146B1
KR100593146B1 KR1020000033973A KR20000033973A KR100593146B1 KR 100593146 B1 KR100593146 B1 KR 100593146B1 KR 1020000033973 A KR1020000033973 A KR 1020000033973A KR 20000033973 A KR20000033973 A KR 20000033973A KR 100593146 B1 KR100593146 B1 KR 100593146B1
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oxide film
forming
gate
film
tantalum oxide
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KR20020000905A (en
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이주완
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주식회사 하이닉스반도체
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008—Making conductor-insulator-semiconductor electrodes
    • H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
    • H01L21/28035—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities
    • H01L21/28044—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities the conductor comprising at least another non-silicon conductive layer
    • H01L21/28052—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities the conductor comprising at least another non-silicon conductive layer the conductor comprising a silicide layer formed by the silicidation reaction of silicon with a metal layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02172—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides
    • H01L21/02175—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides characterised by the metal
    • H01L21/02183—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides characterised by the metal the material containing tantalum, e.g. Ta2O5
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/02227—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process
    • H01L21/02255—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by thermal treatment

Abstract

본 발명은 반도체 소자의 게이트 형성 방법에 관한 것으로, 탄탈륨 산화막(Ta2O5)으로 게이트 산화막을 형성하고 확산 장벽층 또는 전극으로 텅스텐 질화막(WNx)을 형성한 후 열처리 공정을 실시하여 텅스텐 질화막의 질소 원자가 탄탈륨 산화막으로 확산되도록 함으로써 소자의 전류 누설 특성과 항복 특성을 향상시킬 수 있는 반도체 소자의 게이트 형성 방법이 제시된다.
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for forming a gate of a semiconductor device, wherein a gate oxide film is formed of a tantalum oxide film (Ta 2 O 5 ), a tungsten nitride film (WNx) is formed of a diffusion barrier layer or an electrode, and a heat treatment process is performed to form a tungsten nitride film. A method of forming a gate of a semiconductor device capable of improving current leakage and breakdown characteristics of a device by allowing nitrogen atoms to diffuse into a tantalum oxide film is proposed.

게이트, 탄탈륨 산화막, 확산 방지막, 텅스텐 질화막Gate, tantalum oxide, diffusion barrier, tungsten nitride

Description

반도체 소자의 게이트 형성 방법{Method of forming a gate in a semiconductor device} Method of forming a gate in a semiconductor device             

도 1은 본 발명에 따른 반도체 소자의 게이트 형성 방법을 설명하기 위해 도시한 소자의 단면도.1 is a cross-sectional view of a device shown for explaining a gate forming method of a semiconductor device according to the present invention.

도 2(a) 및 도 2(b)는 WNx, W, PVD TiN, CVD TiN의 열처리 전과 열처리 후의 항복 특성을 나타낸 그래프.2 (a) and 2 (b) are graphs showing yield characteristics before and after heat treatment of WN x , W, PVD TiN, and CVD TiN.

도 3(a) 및 도 3(b)는 확산 방지막으로 WNx 및 TiN을 형성하고 열처리 공정을 실시한 후의 단면 사진.
3 (a) and 3 (b) are cross-sectional photographs after forming WNx and TiN as a diffusion barrier and performing a heat treatment step.

<도면의 주요 부분에 대한 부호의 설명><Explanation of symbols for the main parts of the drawings>

11 : 반도체 기판 12 : 탄탈륨 산화막11 semiconductor substrate 12 tantalum oxide film

13 : 텅스텐 질화막 14 : 텅스텐막
13: tungsten nitride film 14: tungsten film

본 발명은 반도체 소자의 게이트 형성 방법에 관한 것으로, 특히 탄탈륨 산화막(Ta2O5)으로 게이트 산화막을 형성하고 확산 장벽층 또는 전극으로 텅스텐 질화막(WNx)을 형성하여 전류 누설 특성과 항복 특성을 향상시킬 수 있는 반도체 소자의 게이트 형성 방법에 관한 것이다.
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for forming a gate of a semiconductor device. In particular, a gate oxide film is formed of a tantalum oxide film (Ta 2 O 5 ) and a tungsten nitride film (WNx) is formed of a diffusion barrier layer or an electrode to improve current leakage and breakdown characteristics. A method of forming a gate of a semiconductor device that can be made.

반도체 소자의 디자인 룰이 감소함에 따라 RC 지연 및 폴리실리콘의 소모 문제를 해결하고, NMOS 트랜지스터 및 PMOS 트랜지스터를 낮은 전압에서 동시에 구동시키기 위한 저저항 게이트 전극으로 금속을 사용하려는 많은 연구가 있어 왔다. 또한, 게이트 산화막이 점점 얇아지고, 3.0㎚ 이하의 실리콘 산화막(SiO2) 등가 두께를 갖는 산화막이 요구됨에 따라 기존의 유전 물질로는 누설 전류 특성을 만족할 수 없게 되었다. 따라서, 유전율이 높은 물질로 실리콘 산화막을 대체하고 폴리실리콘 대신에 금속을 게이트 전극으로 사용하는 구조에 대한 요구가 높아지고 있다. 그러나, 금속 게이트 전극과 게이트 산화막과의 반응을 효과적으로 억제하는 동시에 전기적 특성을 만족하는 게이트 형성 공정에 대한 연구가 아직 충분히 이루어지고 있지 않다.
As the design rules of semiconductor devices decrease, there have been many studies to solve the problem of RC delay and polysilicon, and to use metal as a low resistance gate electrode for simultaneously driving NMOS transistors and PMOS transistors at low voltage. In addition, as the gate oxide film becomes thinner and requires an oxide film having a silicon oxide film (SiO 2 ) equivalent thickness of 3.0 nm or less, conventional dielectric materials cannot satisfy leakage current characteristics. Therefore, there is a growing demand for a structure in which a silicon oxide film is replaced by a material having a high dielectric constant and a metal is used as a gate electrode instead of polysilicon. However, studies on the gate forming process that effectively suppress the reaction between the metal gate electrode and the gate oxide film and satisfy the electrical characteristics have not been sufficiently conducted.

따라서, 본 발명은 금속 게이트 전극과 게이트 산화막과의 반응을 효과적으로 억제할 수 있으며 소자의 전기적 특성을 향상시킬 수 있는 반도체 소자의 게이트 형성 방법을 제공하는데 그 목적이 있다. Accordingly, an object of the present invention is to provide a method for forming a gate of a semiconductor device capable of effectively suppressing a reaction between a metal gate electrode and a gate oxide film and improving the electrical characteristics of the device.

상술한 목적을 달성하기 위한 본 발명은 반도체 기판 상부에 탄탈륨 산화막을 형성한 후 텅스텐 질화막 및 텅스텐막을 순차적으로 형성하는 단계와, 열처리 공정을 실시하여 상기 텅스텐 질화막의 질소 원자를 상기 탄탈륨 산화막으로 확산시키는 단계와, 상기 텅스텐막, 텅스텐 질화막 및 탄탈륨 산화막을 패터닝하여 게이트를 형성하는 단계를 포함하여 이루어진 것을 특징으로 하며, 상기 텅스텐막을 형성하지 않고 텅스텐 질화막만을 형성하는 것을 특징으로 한다.
The present invention for achieving the above object is to form a tantalum oxide film on the semiconductor substrate and then sequentially forming a tungsten nitride film and a tungsten film, and performing a heat treatment process to diffuse the nitrogen atoms of the tungsten nitride film to the tantalum oxide film And forming a gate by patterning the tungsten film, the tungsten nitride film, and the tantalum oxide film, wherein only the tungsten nitride film is formed without forming the tungsten film.

첨부된 도면을 참조하여 본 발명을 상세히 설명하기로 한다.The present invention will be described in detail with reference to the accompanying drawings.

도 1은 본 발명에 따른 반도체 소자의 게이트 형성 방법을 설명하기 위해 도시한 소자의 단면도이다.1 is a cross-sectional view of a device illustrated to explain a gate forming method of a semiconductor device according to the present invention.

반도체 기판(11) 상부에 게이트 산화막으로 탄탈륨 산화막(Ta2O5)(12)을 6∼10㎚의 두께로 형성하고, 750∼850℃ 정도의 온도를 유지하는 산소 분위기에서 열처리 공정을 실시한다. 전체 구조 상부에 텅스텐 질화막(WNx)(13) 및 텅스텐막 (W)(14)을 순차적으로 형성한다. 그리고, 800∼950℃ 정도의 온도를 유지하는 질소 분위기에서 10∼60초 동안 열처리 공정을 실시하여 텅스텐 질화막(13) 내부의 질소 원자가 탄탈륨 산화막(12)으로 확산되도록 한다. 텅스텐 질화막(13)은 5∼40㎚의 두께로 형성하고, 텅스텐막(14)은 40∼80㎚의 두께로 형성한다. 텅스텐막(14), 텅스텐 질화막(13) 및 탄탈륨 산화막(12)을 패터닝하여 게이트 전극을 형성한다.A tantalum oxide film (Ta 2 O 5 ) 12 is formed with a gate oxide film on the semiconductor substrate 11 to a thickness of 6 to 10 nm, and a heat treatment step is performed in an oxygen atmosphere maintaining a temperature of about 750 to 850 ° C. . The tungsten nitride film (WNx) 13 and the tungsten film (W) 14 are sequentially formed on the entire structure. Then, a heat treatment process is performed for 10 to 60 seconds in a nitrogen atmosphere maintaining a temperature of about 800 to 950 ° C. to allow nitrogen atoms inside the tungsten nitride film 13 to diffuse into the tantalum oxide film 12. The tungsten nitride film 13 is formed to a thickness of 5 to 40 nm, and the tungsten film 14 is formed to a thickness of 40 to 80 nm. The tungsten film 14, the tungsten nitride film 13 and the tantalum oxide film 12 are patterned to form a gate electrode.

상기에서 텅스텐막(14)을 형성하지 않고, 텅스텐 질화막(13)을 40∼120㎚의 두께로 형성한 후 이후 공정을 실시하여 게이트를 형성할 수 있다.
Instead of forming the tungsten film 14, the tungsten nitride film 13 may be formed to a thickness of 40 to 120 nm, and then a gate may be formed by a subsequent process.

도 2(a) 및 도 2(b)는 WNx, W, PVD TiN, CVD TiN을 열처리하기 전과 900℃에서 열처리한 후의 항복 특성을 나타낸 그래프이다. 그래프에서 볼 수 있는 바와 같이 WNx의 고온 특성이 다른 물질에 비해 우수함을 알 수 있으며, 열처리 공정을 통해 그 특성이 향상됨을 알 수 있다.
2 (a) and 2 (b) are graphs showing yield characteristics before heat treatment of WNx, W, PVD TiN, and CVD TiN and after heat treatment at 900 ° C. As can be seen in the graph, it can be seen that the high temperature property of WNx is superior to other materials, and the property is improved through a heat treatment process.

도 3(a) 및 도 3(b)는 확산 방지막으로 WNx 및 TiN을 형성하고 열처리 공정을 실시한 후의 단면 TEM 사진이다. 도시된 바와 같이 TiN내에는 보이드가 형성되어 하부층의 원자가 보이드를 통해 상부층으로 확산될 수 있어 소자의 특성을 열화시킬 수 있지만, WNx는 보이드가 형성되지 않으므로 TiN에 비해 확산 방지막으로서의 역할이 우수함을 알 수 있다.
3 (a) and 3 (b) are cross-sectional TEM photographs after forming WNx and TiN as a diffusion barrier and performing a heat treatment step. As shown, voids are formed in TiN, and the atoms of the lower layer can diffuse to the upper layer through the voids, thereby deteriorating the characteristics of the device. However, since WNx does not form voids, it has a superior role as a diffusion barrier than TiN. Can be.

상술한 바와 같이 본 발명에 의하면 게이트 산화막으로 유전율이 높은 탄탈륨 산화막을 형성함으로써 10㎚ 이상의 충분한 물리적 두께를 유지하면서도 3.0㎚ 이하의 실리콘 산화막 등가 두께를 갖는 얇은 산화막을 형성할 수 있다. 또한, 확산 방지막으로 WNx를 사용함으로써 확산 방지막을 형성하지 않고 텅스텐막을 형성하는 경우 또는 TiN을 확산 방지막으로 형성하는 경우에 비해 고온 열안정성과 전기적 특성을 향상시킬 수 있다. 한편, 일반적인 확산 방지막은 열처리 공정을 실시할 때 열화되는 경향이 있으나 WNx는 열처리 공정을 실시할 때 오히려 그 특성이 향상되므로 후속 열처리 공정시 게이트 전극과 게이트 산화막 사이에 우수한 확산 방지막을 인시투로 형성할 수 있다.As described above, according to the present invention, by forming a tantalum oxide film having a high dielectric constant as the gate oxide film, a thin oxide film having a silicon oxide film equivalent thickness of 3.0 nm or less can be formed while maintaining a sufficient physical thickness of 10 nm or more. In addition, by using WNx as the diffusion barrier, high temperature thermal stability and electrical characteristics can be improved as compared with the case where a tungsten layer is formed without forming a diffusion barrier or when TiN is formed as a diffusion barrier. On the other hand, general diffusion barriers tend to deteriorate when the heat treatment process is performed, but WNx has better properties when the heat treatment process is performed. can do.

Claims (11)

반도체 기판 상부에 탄탈륨 산화막을 형성한 후 텅스텐 질화막 및 텅스텐막을 순차적으로 형성하는 단계와,Forming a tantalum oxide film on the semiconductor substrate and sequentially forming a tungsten nitride film and a tungsten film; 열처리 공정을 실시하여 상기 텅스텐 질화막의 질소 원자를 상기 탄탈륨 산화막으로 확산시키는 단계와,Performing a heat treatment process to diffuse nitrogen atoms of the tungsten nitride film into the tantalum oxide film; 상기 텅스텐막, 텅스텐 질화막 및 탄탈륨 산화막을 패터닝하여 게이트를 형성하는 단계를 포함하여 이루어진 것을 특징으로 하는 반도체 소자의 게이트 형성 방법.And forming a gate by patterning the tungsten film, the tungsten nitride film, and the tantalum oxide film. 제 1 항에 있어서, 상기 탄탈륨 산화막은 6 내지 10㎚의 두께로 형성하는 것을 특징으로 하는 반도체 소자의 게이트 형성 방법.2. The method of claim 1, wherein the tantalum oxide film is formed to a thickness of 6 to 10 nm. 제 1 항에 있어서, 상기 탄탈륨 산화막을 형성한 후 750 내지 850℃의 온도를 유지하는 산소 분위기에서 열처리 공정을 실시하는 것을 특징으로 하는 반도체 소자의 게이트 형성 방법.The method of forming a gate of a semiconductor device according to claim 1, wherein after the tantalum oxide film is formed, a heat treatment step is performed in an oxygen atmosphere maintaining a temperature of 750 to 850 ° C. 제 1 항에 있어서, 상기 텅스텐 질화막은 5 내지 40㎚의 두께로 형성하는 것을 특징으로 하는 반도체 소자의 게이트 형성 방법.The method of claim 1, wherein the tungsten nitride film is formed to a thickness of 5 to 40 nm. 제 1 항에 있어서, 상기 텅스텐막은 40 내지 80㎚의 두께로 형성하는 것을 특징으로 하는 반도체 소자의 게이트 형성 방법.The method of claim 1, wherein the tungsten film is formed to a thickness of 40 to 80 nm. 제 1 항에 있어서, 상기 열처리 공정은 800 내지 950℃의 온도를 유지하는 질소 분위기에서 10 내지 60초 동안 실시하는 것을 특징으로 하는 반도체 소자의 게이트 형성 방법.The method of claim 1, wherein the heat treatment is performed for 10 to 60 seconds in a nitrogen atmosphere maintaining a temperature of 800 to 950 ° C. 6. 반도체 기판 상부에 탄탈륨 산화막을 형성한 후 텅스텐 질화막을 형성하는 단계와,Forming a tantalum oxide film on the semiconductor substrate and then forming a tungsten nitride film; 열처리 공정을 실시하여 상기 텅스텐 질화막의 질소 원자를 상기 탄탈륨 산화막으로 확산시키는 단계와,Performing a heat treatment process to diffuse nitrogen atoms of the tungsten nitride film into the tantalum oxide film; 상기 텅스텐 질화막 및 탄탈륨 산화막을 패터닝하여 게이트를 형성하는 단계를 포함하여 이루어진 것을 특징으로 하는 반도체 소자의 게이트 형성 방법.And forming a gate by patterning the tungsten nitride film and the tantalum oxide film. 제 7 항에 있어서, 상기 탄탈륨 산화막은 6 내지 10㎚의 두께로 형성하는 것을 특징으로 하는 반도체 소자의 게이트 형성 방법.8. The method of claim 7, wherein the tantalum oxide film is formed to a thickness of 6 to 10 nm. 제 7 항에 있어서, 상기 탄탈륨 산화막을 형성한 후 750 내지 850℃의 온도를 유지하는 산소 분위기에서 열처리 공정을 실시하는 것을 특징으로 하는 반도체 소자의 게이트 형성 방법.8. The method of claim 7, wherein after the tantalum oxide film is formed, a heat treatment step is performed in an oxygen atmosphere maintaining a temperature of 750 to 850 占 폚. 제 7 항에 있어서, 상기 텅스텐 질화막은 40 내지 120㎚의 두께로 형성하는 것을 특징으로 하는 반도체 소자의 게이트 형성 방법.8. The method of claim 7, wherein the tungsten nitride film is formed to a thickness of 40 to 120 nm. 제 7 항에 있어서, 상기 열처리 공정은 800 내지 950℃의 온도를 유지하는 질소 분위기에서 10 내지 60초 동안 실시하는 것을 특징으로 하는 반도체 소자의 게이트 형성 방법.The method of claim 7, wherein the heat treatment is performed for 10 to 60 seconds in a nitrogen atmosphere maintaining a temperature of 800 to 950 ° C. 9.
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JPH08274256A (en) * 1995-01-30 1996-10-18 Toshiba Corp Semiconductor device and manufacture thereof
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