KR100587149B1 - Source driver for LCD - Google Patents

Abstract

The present invention discloses a source driver circuit for an LCD which reduces the peak current by sequentially driving a plurality of latches arranged in a plurality of channels. A source driver circuit for an LCD of the present invention comprises: a data input unit for inputting R, G, and B data of a predetermined bit from the outside in accordance with an output signal of a shift register; A control logic unit generating a first load signal and a second load signal by a control signal and an internal clock signal provided from the outside; A latch unit configured to store data from the data input unit according to a first load signal and a second load signal generated from the control logic unit; A level shifter unit for converting a level of data provided from the latch unit; A register string for generating a gradation voltage according to the number of gradations to be expressed; A decoder unit for selecting a corresponding one of a plurality of gray voltages generated from a resistor string according to a signal output from the level shifter; And an output buffer unit for providing a gray scale voltage selected by the decoder unit to the LCD panel, wherein the latch unit includes a plurality of latches corresponding to the channel, and the plurality of latches correspond to the first and second load signals. Therefore, it is divided into at least two groups and driven sequentially.

LCD, Source Driver, Latch, Sequential Drive, Load Signal

Description

Source driver circuit for LCD {Source driver for LCD}             

1 is a block diagram of a conventional source driver circuit for LCD;

2 is a detailed view of a shift register of a conventional source driver circuit for LCD;

3 is an operation waveform diagram of a conventional source driver circuit for LCD;

4 is a block diagram of an LCD source driver circuit according to a first embodiment of the present invention;

5 is a detailed circuit diagram of a latch control logic section in the LCD source driver circuit of the present invention;

FIG. 6 is a view for explaining a method of controlling a latch of a source driver circuit for an LCD shown in FIG. 4;

7 is a block diagram of an LCD source driver circuit according to a second embodiment of the present invention;

8 is a view for explaining a method of controlling the latch of the source driver for LCD shown in FIG.

9 is an operation waveform diagram of a source driver for LCD of the present invention;

* Description of the symbols for the main parts of the drawings *

210, 310: shift registers 220, 320: latch control logic section

230, 330: register string 240, 340: data input

250, 350: latch portion 270, 370: level shifter portion

280, 380: decoder section 290, 390: output buffer section

The present invention relates to a source driver circuit for an LCD, and more particularly, to a source driver circuit capable of reducing an instantaneous peak current by sequentially dividing a plurality of latches arranged in a plurality of channels.

1 shows a block diagram of a conventional source driver circuit for LCD. Referring to FIG. 1, a conventional source driver circuit for an LCD includes a shift register unit 110, a latch control logic unit 120, a register string 130, a data input unit 140, and a latch unit 150. And a level shifter 170, a decoder 180, and an output buffer 190.

In accordance with the output signal of the shift register unit 110 controlled by the shift control signal SCS, R, G, and B data of predetermined bits are provided from the data input unit 140 to the latch unit 150, thereby providing a latch unit ( It is stored in a plurality of latches (151-15n) arranged in the first latch stage of 150.

As illustrated in FIG. 3, the latch control logic unit 120 inputs a control signal TP and an internal clock signal DCLK applied from the outside to be arranged at a second latch end of the latch unit 150. The load signal LD is generated by the latches 161-16n. Data is provided from the latches 151-15n arranged in the first latch stage to the latches 161-16n arranged in the second latch stage by the load signal LD generated from the latch control logic unit 120. .

The data stored in the latch unit 150 is provided to the level shifter 170 and level converted. The register string 130 receives a reference voltage Vref to generate a plurality of gray voltages corresponding to the number of bits of the R, G, and B data. The decoder unit 180 selects one of a plurality of gray voltages generated from the register string 130 according to data output through the level shifter 170 and provides it to the output buffer unit 190. The output buffer unit 190 drives the LCD panel in response to the selected gray voltage.

Fig. 2 shows a detailed view of each level shifter in the level shifter section in the conventional LCD source driver circuit. 2, each level shifter of the level shifter unit 170 includes first and second inverters I1 and I2 for inverting the input signal DIN, and first and second inverters I1 and I1. NMOS transistors M1-M4 constituting a differential amplifier having two output signals of I2) and PMOS transistors and NMOS transistors M6 for inverting the signals of the output node of the differential amplifier as input signals, respectively. M5) and (M8, M7).

The conventional level shifter having the above-described configuration inputs an input signal DIN having a low voltage level and level converts the output signals OUT and OUTB having a high voltage level. However, in the conventional level shifter, the PMOS transistor, the NMOS transistors M8, M7, and M6, M5 are simultaneously turned on to generate the peak current of the level shifter as shown in FIG. 3.

At this time, the source driver circuit for the LCD is composed of a plurality of channels as shown in Figure 1, the decoder unit 180 and the output buffer unit 190, each decoder and output buffer for each channel is arranged, the latch unit A plurality of latches are arranged to correspond to the number of R, G, and B data bits per channel, and the level shifter 170 includes a plurality of level shifters to correspond to the number of data bits per channel, that is, a plurality of latches. do.

Therefore, as in the conventional source driver circuit, the latches 161-16n of the latch unit 150 are simultaneously driven by the load signal LD provided from the control logic unit 120, and the level shifters 171-17n. ) Is driven at the same time, there is a problem that a large peak current (Ip) is generated when the NMOS transistor and the PMOS transistor is turned on at the same time, resulting in a decrease in reliability.

The present invention is to solve the problems of the prior art as described above, the source driver circuit for LCD and its driving method that can reduce the peak current by sequentially driving a plurality of latches, thereby improving the reliability The purpose is to provide.                         

Another object of the present invention is to provide a source driver circuit for an LCD and a method of driving the same, which can reduce the size of the chip by reducing the power wiring in the layout of the circuit.

In order to achieve the above object, the present invention provides a data source for inputting predetermined bits of R, G, and B data according to an output signal of a shift register in an LC source driver circuit having a plurality of channels. ; A control logic unit generating a first load signal and a second load signal by a control signal and an internal clock signal provided from the outside; A latch unit configured to store data from the data input unit according to a first load signal and a second load signal generated from the control logic unit; A level shifter unit for converting a level of data provided from the latch unit; A register string for generating a gradation voltage according to the number of gradations to be expressed; A decoder unit for selecting a corresponding one of a plurality of gray voltages generated from a resistor string according to a signal output from the level shifter; And an output buffer unit for providing the gray scale voltage selected by the decoder unit to the LCD panel, wherein the latch unit includes a plurality of latches corresponding to the channel, and the plurality of latches correspond to the first and second load signals. Accordingly, it is characterized by providing a source driver circuit for LCD which is divided into at least two groups and sequentially driven.

Among the plurality of latches of the latch unit, a latch arranged in some channels of the plurality of channels is driven by a first load signal, and a latch arranged in the remaining channels is driven by a second load signal, or each channel is R, A first rod signal drives a latch arranged in correspondence with the number of bits of the plurality of latches arranged in correspondence with the number of G and B data bits, and the second rod loads a latch arranged in correspondence with the remaining bits. It is characterized by driving by a signal.

The control logic unit may include a first signal generating means for generating a first load signal by inputting the external control signal and an internal clock signal, and an output signal and the internal clock signal of the first signal generating means to input a second load signal. It consists of a second signal generating means for generating a. The first signal generating means comprises a rising edge detector for detecting a rising edge of the external control signal to generate a first load signal, and the second signal generating means delays the first load signal by a predetermined time. It consists of a flip-flop generating two load signals.

The first load signal is enabled by one cycle of the internal clock signal, and the second load signal is characterized in that the first load signal is delayed by one cycle of the internal clock signal.

In addition, the present invention inputs R, G, B data of a predetermined bit from the outside, and generates a first load signal and a second load signal by the control signal and the internal clock signal provided from the outside, the first load signal Storing the R, G, and B data in some latches of the plurality of latches arranged corresponding to the plurality of channels by the first load signal of the second load signal, and converting the level of the data stored in the partial latches, The R, G, and B data are stored in the remaining latches among the plurality of latches arranged corresponding to the plurality of channels by the second load signal of the first load signal and the second load signal, and the data stored in the remaining latches is stored. And converting a level, selecting one of a plurality of gray voltages according to the level converted data, and providing the selected gray voltage to an LCD panel. .

Some of the latches are latches corresponding to odd-numbered channels of the plurality of channels, or latches corresponding to some of the R, G, and B data bits of each channel, and the remaining latches are even-numbered ones of the plurality of channels. Or a latch arranged in correspondence with a channel or a latch arranged in correspondence with the rest of a plurality of bits of each channel.

Hereinafter, embodiments of the present invention will be described with reference to the accompanying drawings.

4 shows a block diagram of an LCD source driver circuit according to a first embodiment of the present invention.

Referring to FIG. 4, the source driver circuit according to the first exemplary embodiment of the present invention may include a shift register 210, a latch control logic 220, a register string 230, a data input 240, and a latch 250. ), A level shifter 270, a decoder 280, and an output buffer 290.

The shift register unit 210 generates an output signal to the data input unit 240 by a shift control signal SCS provided from the outside, and the data input unit 240 outputs an output signal of the shift register unit 210. As a result, a predetermined bit of R, G, and B data is provided to the latch unit 250. The shift register unit 210 has a shift register number corresponding to the number of channels. When the number of channels is n, the shift register unit 210 includes n shift registers.

The latch unit 250 is provided from the control logic unit 220 and a first latch stage for storing a predetermined bit of R, G, and B data from the data input unit 240 according to the output of the shift register 210. A second latch stage for storing the R, G, B data provided from the first latch stage for each line according to the first load signal LD1 and the second load signal LD2.

The first latch stage is for storing R, G, and B data of a predetermined bit according to the output signal of the shift register 210, and the number of bits of R, G, and B data for each channel CH1 to CHn. Correspondingly, a plurality of latches 251-25n are arranged. At this time, although one latch is arranged for each channel CH1-CHn in the drawing, in practice, each latch 1, latch 2, ... latch n 251-25n are R, G, and B data, respectively. As many latches as the number of bits are arranged.

The second latch stage is R provided from the latches 251-25n of the first latch stage according to the first load signal LD1 and the second load signal LD2 provided from the control logic unit 220, It consists of a plurality of latches 261-26n for storing G and B data in line units. Similarly, in the plurality of latches 261-26n arranged in the second latch stage, the plurality of latches 261-26n are arranged in correspondence to the number of bits of the R, G, and B data for each channel CH1-CHn. . At this time, although one latch is arranged for each channel CH1-CHn in the drawing, in reality, each latch 1, latch 2, ... latch n 261-26n respectively represents R, G, and B data. As many latches as the number of bits are arranged.

The data stored in the latch unit 250 is provided to the level shifter 270 to perform a level conversion, for example, from a low voltage level of 3.3V to a data of a high voltage level of 15V. Like the plurality of latches 251-25n and 261-26n arranged in the latch unit 250, the level shifter unit 270 has the bits of the R, G, and B data for each channel CH1-CHn. A plurality of shift registers 261-26n are arranged corresponding to the numbers.

At this time, one shift register for each channel CH1-CHn is shown in the drawing, but in reality, each shift register 1, the sheet register 2, ... shift register n 271-27n are R, G, As many shift registers as the number of bits of the B data are arranged. Accordingly, the number of latches and level shifters of the latch unit 250 is determined according to the number of channels CH1-CHn and the number of bits of each channel, that is, the number of bits of the R, G, and B data. If the number of bits of each data is 6 bits, 3840 latches and level shifters are arranged.

The register string 230 inputs a reference voltage Vref to generate a plurality of gray voltages corresponding to the number of bits of the R, G, and B data, and is generated according to the number of gray levels to be expressed. The number of gradation voltages to be determined is determined. For example, when the R, G, and B data are 8 bits, the number of gray levels to be expressed is 256, and 256 gray voltages are generated from the register string 230.

The decoder 280 selects one of a plurality of gray voltages generated from the register string 230 according to data output through the level shifter 270 and provides it to the output buffer unit 290. The output buffer unit 290 drives each channel CH1-CHn of the LCD panel in response to the selected gray voltage. Since the decoder unit 280 and the output buffer unit 290 have one decoder and an output buffer for each channel, the decoders 281-28n and the plurality of output buffers correspond to the number of channels CH1-CHn. And each of (291-29n).

The latch control logic unit 220 includes a plurality of latches 261-26n arranged at the second latch end of the latch unit 250 when a control signal TP applied from the outside transitions from a low state to a high state. The first load signal LD1 and the second load signal LD2 are generated, and have a configuration as shown in FIG. 5.

5 is a detailed block diagram of the latch control logic unit 220 in the LCD source driver circuit according to the embodiment of the present invention. Referring to FIG. 5, the latch control logic unit 220 inputs a control signal TP and an internal clock signal DCLK applied from the outside to generate a first load signal LD1. And a second signal generating means 223 for inputting the output signal LD1 and the clock signal DCLK of the first signal generating means 221 to generate the second load signal LD2.

The first signal generating means 221 detects the rising edge of the external control signal TP and generates the rising edge for generating the first load signal LD1 enabled for one period of the internal clock signal DCLK. The second signal generating means 223 may be configured as a detector, and the first load signal LD1 generated by the rising edge detector of the first signal generating means 221 is one of the internal clock signal DCLK. It may be configured as a flip-flop 223, for example, a D-flop, which delays by a period to generate the second load signal LD2.

The external control signal TP is a signal that transitions from a low state to a high state whenever an R, G, B data signal is provided from the outside to the LCD panel, and loads R, G, B data into the LCD panel. This is an enable signal for enabling. The first load signal LD1 is a latch 261, 263, ... arranged in correspondence with an odd number channel among the plurality of latches 161-16n arranged at the second latch end of the latch unit 250. Is an enable signal for enabling the signal, and the second load signal LD2 is arranged corresponding to an even number channel among the plurality of latches 161-16n arranged at the second latch end of the latch unit 250. Enable signals for enabling the latches 262, 264, ... to be activated.

FIG. 6 schematically illustrates some of the plurality of latches 261-26n constituting the second latch stage of the latch unit 250. Referring to FIG. 6, a latch 261 arranged at a second latch end of the latch unit 250 by a first load signal LD1 and a second load signal LD2 output from the latch control logic unit 220. -16n) is sequentially driven time-divisionally. That is, the latch control logic unit 220 generates the first load signal LD1 to the latch unit 250 when a rising edge of the external control signal TP is detected. Accordingly, the latch control logic unit 220 generates a plurality of latches of the latch unit 250. The latches 261, 263, ... corresponding to the odd-numbered channels among the 262-26n are driven by the first load signal LD1. Subsequently, the latch control logic unit 220 generates a second load signal LD2 delayed by one period of the clock signal DCLK from the first load signal LD1, and latches 262 corresponding to even-numbered channels. , 264, ... are driven by the second load signal LD2.

That is, latches 1, latch 3, ... arranged in correspondence to the odd numbered channels among the plurality of channels CH1-CHn by the first load signal LD1 are R, G, and B as shown in FIG. Eight latches (D0-D7) are provided when the data is composed of 8 bits, and similarly, the level shifter 1 (271), the level shifter 3, and the like are similar to the eight shift registers when the R, G, and B data are composed of 8 bits. D0-D7).

On the other hand, latches 2, 4, ... arranged in correspondence with even-numbered channels among the plurality of channels CH1-CHn by the second load signal LD2 are R, G, and B as shown in FIG. Eight latches (D0-D7) are provided when the data is composed of 8 bits, and similarly, the level shifter 2 (272), the level shifter 4, and the like, are similarly applied to the eight shift registers when the R, G, and B data are composed of 8 bits. D0-D7).

The operation of the LCD source driver circuit of the present invention having the configuration as described above will be described with reference to FIG.

The shift register 210 is controlled by the shift register clock signal SCS to generate an output signal to the data input unit 240. The data input unit 240 provides R, G, and B data to the plurality of latches 251-25n arranged at the first latch stage of the latch unit 250 by the output signal of the shift register 210. .

In this case, as illustrated in FIG. 9, when the first load signal LD1 is generated from the latch control logic unit 220 according to the detection of the rising edge of the external control signal TP, the second portion of the latch unit 250 is generated. Of the plurality of latches 261-26n arranged at the latch stage, the latches 261, 263, ... arranged corresponding to the odd-numbered channels CH1, CH3, ... are driven to latch the first latch stage. Data is provided and stored from (251, 253, ...). The data stored in the latches 261, 263, ... are level-converted through the level shifters 271, 273, ... to convert the output buffers 291, 293, ... of the output buffer unit 290. Is output via

Subsequently, as illustrated in FIG. 9, when the second load signal LD2 is generated from the latch control logic unit 220, a plurality of latches 261-2 arranged at the second latch end of the latch unit 250 are provided. The latches 262, 264, ... arranged in correspondence with the even-numbered channels CH1, CH3, ... are driven to drive data from the latches 252, 254, ... of the first latch stage. Is provided and stored. The data stored in the latches 262, 264, ... are level-converted through the level shifters 272, 274, ... to convert the output buffers 292, 294, ... of the output buffer unit 290. Is output via

Accordingly, although the latches of the plurality of channels Ch1 -CHn are driven at the same time, in the present invention, the latches arranged in correspondence with the even and odd channels of the plurality of channels CH1 -CHn are latch control logic units ( The driving is sequentially performed by the first and second load signals LD1 and LD2 provided from 220. Therefore, as shown in Fig. 9, by driving a plurality of latches arranged in a plurality of channels by dividing, the peak current Ip of the level shifter is generated whenever the load signals LD1 and LD2 are applied. It can be seen that its size is reduced compared to the conventional.

7 shows a block diagram of an LCD source driver circuit according to a second embodiment of the present invention. As in the first embodiment, the LCD source driver circuit according to the second embodiment includes the shift register unit 310, the control logic unit 320, the register string 330, the data input unit 340, the latch unit 350, The level shifter 370, the decoder 380, and the output buffer 390 are provided.

Each component according to the second embodiment of the present invention has the same configuration and operation as in the first embodiment. However, the first load signal LD1 and the second load signal LD2 output from the latch control logic unit 320 are simultaneously provided to the latches corresponding to the channels CH1 to CHn and arranged in each channel. Some of the latches are driven by the first load signal LD1 and others are driven by the second load signal LD2.

In the first embodiment, the latches of some channels of the plurality of channels are driven, and then the latches of the remaining channels are sequentially driven to divide and drive the plurality of latches. After driving, the latches corresponding to the remaining bits of each channel are sequentially driven to divide and drive a plurality of latches.

That is, in the second embodiment of the present invention, as shown in FIG. 8, R, G, and B data are composed of 8 bits so that 8 latches D0-D7 are arranged for each of the channels 261 and 262. In this case, the latches D0-D3 corresponding to the first 4 bits of the plurality of latches D0-D7 arranged for each of the channels 261 and 262 are driven by the first load signal LD1, and the remaining 4 are driven. The latches D4-D7 corresponding to the bits are driven by the second load signal LD2. Even in this case, the peak current can be reduced by dividing a plurality of latches arranged in each of the plurality of channels into two groups and driving them sequentially.

In the exemplary embodiment of the present invention, a plurality of latches arranged in correspondence with a plurality of channels by two load signals LD1 and LD2 generated from the latch control logic unit 220 may be configured as two groups of latches, for example. Although the latches arranged in the even-numbered channel and the latches arranged in the odd-numbered channel or the respective bits are sequentially driven, not only can a plurality of latches be driven by dividing into two groups in various ways, but also into three or more groups. By dividing and driving sequentially, the peak current can be reduced.

The source driver circuit for an LCD according to the embodiment of the present invention as described above can reduce the peak current by dividing a plurality of latches arranged in correspondence to a plurality of channels into two groups of latches sequentially. In addition, as the peak current is reduced, not only the power wiring in the layout of the circuit can be reduced but also the chip size can be reduced.

Although described above with reference to a preferred embodiment of the present invention, those skilled in the art will be variously modified and changed within the scope of the invention without departing from the spirit and scope of the invention described in the claims below I can understand that you can.

Claims (8)

In a source driver circuit for a LC having a plurality of channels, A data input unit for inputting R, G, and B data of a predetermined bit from the outside according to the output signal of the shift register; A control logic unit generating a first load signal and a second load signal by a control signal and an internal clock signal provided from the outside; A latch unit configured to store data from the data input unit according to a first load signal and a second load signal generated from the control logic unit; A level shifter unit for converting a level of data provided from the latch unit; A register string for generating a gradation voltage according to the number of gradations to be expressed; A decoder unit for selecting a corresponding one of a plurality of gray voltages generated from a resistor string according to a signal output from the level shifter; An output buffer unit for providing a gray scale voltage selected by the decoder unit to the LCD panel, And a plurality of latches arranged in correspondence with the channel, and the plurality of latches are sequentially driven in at least two groups according to the first and second load signals. The method of claim 1, Among the latches of the latch unit, a latch arranged in some channels of the plurality of channels is driven by a first load signal, and a latch arranged in the remaining channels is driven by a second load signal. Driver circuit. The method of claim 1, A latch arranged corresponding to the number of bits of the plurality of latches of the latch unit arranged in correspondence to the number of R, G, and B data bits for each channel is driven by the first load signal and arranged in correspondence with the remaining number of bits. A source driver circuit for an LCD, wherein the latch is driven by a second load signal. The method of claim 1, The control logic unit First signal generating means for inputting the external control signal and the internal clock signal to generate a first load signal; And a second signal generator for inputting the output signal of the first signal generator and the internal clock signal to generate a second load signal. The method of claim 4, wherein The first signal generating means of the control logic unit is configured as a rising edge detector for detecting a rising edge of the external control signal to generate a first load signal, and the second signal generating means generates the first load signal for a predetermined time. A source driver circuit for an LCD comprising a flip-flop that is delayed to generate a second load signal. The method of claim 5, And the first load signal is enabled by one cycle of the internal clock signal, and the second load signal is delayed by one cycle of the internal clock signal by the second load signal. Inputs R, G, B data of predetermined bits from the outside, The first load signal and the second load signal are generated by the control signal and the internal clock signal provided from the outside, Storing the R, G, and B data in some latches of a plurality of latches arranged corresponding to a plurality of channels by a first load signal of the first load signal and the second load signal, Convert the level of data stored in the latches of the portion, Storing the R, G, and B data in the remaining latches among the plurality of latches arranged corresponding to the plurality of channels by the second load signal of the first load signal and the second load signal, Convert the level of data stored in the remaining latches, Selecting one of a plurality of gray voltages according to the level-converted data, and providing the selected gray voltage to an LCD panel. The method of claim 7, wherein And some of the latches are latches arranged corresponding to odd-numbered channels of the plurality of channels, and the other latches are latches arranged corresponding to even-numbered channels of the plurality of channels.

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