KR100587068B1 - Method for contrlling and monitering the tDPL in memory device acccording to thw variation of the operating frequency - Google Patents

Abstract

The present invention relates to a tDPL control method and a tDPL measurement method according to a change in operating frequency of a memory device, and more particularly, to a method for controlling tDPL using a cascade latency that varies according to an operating frequency and a method for measuring the same in a test mode. .

TDPL (tDPL: time from when a cas pulse generated internally by a write command is generated to when an internally generated precharge pulse signal is generated by a precharge command) according to a change in an operating frequency of a memory device As a result, the generation time of the precharge pulse signal is adjusted by using a cascade latency that is changed due to a change in an operating frequency of the memory device.

Description

Method for contrlling and monitering the tDPL in memory device acccording to thw variation of the operating frequency}

1A and 1B are diagrams illustrating tDPL according to a change in operating frequency.

2 is an example of a conventional precharge pulse signal generation circuit.

Figure 3 is an embodiment of a precharge pulse signal generation circuit according to the present invention that can adjust the delay time of the output signal in accordance with the operating frequency of the memory device.

4 and 5 are examples of the variable delay unit 300 shown in FIG. 3.

FIG. 6 is a waveform diagram of the precharge pulse signal generation circuit of the present invention shown in FIG.

7 is a waveform diagram in a test mode.

8 is a circuit of the second embodiment of the present invention capable of measuring a delay time of a precharge pulse signal generation circuit using a pad used for packaging.

9 is an example of an address buffer in accordance with the present invention.

10 is an example of a data output buffer in accordance with the present invention.

FIG. 11 is an output waveform diagram of the second embodiment of the present invention shown in FIG. 8; FIG.

The present invention relates to a tDPL control method and a tDPL measurement method according to a change in operating frequency of a memory device, and more particularly, to a method for controlling tDPL using a cascade latency that varies according to an operating frequency and a method for measuring the same in a test mode. .

 The present invention proposes a method for improving the last data-in to precharge delay time (tDPL) of a volatile memory device. Here, tDPL means a time from the time when the cas pulse generated internally by the write command is generated to the time when the precharge pulse signal generated internally by the precharge command is generated.

1A and 1B are diagrams illustrating tDPL according to a change in operating frequency.

1A and 1B, WT represents a write command, PCG represents a precharge command, and ACT represents an active command. casp represents a cas pulse signal generated inside the memory device by the write command, and pcgp represents a precharge pulse signal generated inside the memory device by the precharge command. The column operation or the precharge operation is internally performed by the cas pulse signal or the precharge pulse signal. tDPL represents the time from when the write command is applied to when the precharge signal is applied. In general, tDPL may be expressed as a time from when the cas pulse signal is generated to when the precharge pulse signal is generated.

1A is a case where the operating frequency of the memory device (eg, the frequency of CLK of the DDR DRAM) is low, and tDPL = 3tCK. Here, tCK represents the period of CLK.

Figure 1b is a case where the operating frequency of the memory device is high, tDPL = 3tCK.

As can be seen in FIGS. 1A and 1B, it can be seen that as the operating frequency of the memory device increases, tDPL becomes short. As such, shortening of tDPL results in a loss of write recovery time. In this case, as shown in Fig. 1B, the generation timing of the precharge pulse signal may be delayed to increase tDPL. However, even if the timing of occurrence of the precharge pulse signal is delayed, tRP, which is the time from the precharge command to the next active command, must be sufficiently guaranteed.

2 is an example of a conventional precharge pulse signal generation circuit.

In Fig. 2, pcgp6 is a pulse signal generated from a command decoder (not shown). The command decoder generates pcgp6 by combining external command signals such as / RAS, / CAS, / WE, and / CS. The precharge pulse signal generation circuit delays pcgp6 for a certain time and outputs pcgp9. Therefore, the waveforms of the pulse signal pcgp6 and the pulse signal pcgp9 are the same. bankt4 represents a signal having information about a bank of a memory device. at <10> is a signal for controlling the precharge operation of the entire memory bank. When this signal has a high level, the precharge pulse signal generating circuits of all banks operate. pwrup is a signal for setting an initial value, which is held at a high level, then drops to a low level and then continues at a low level. tm_reset is a signal used in test mode and maintains a low level during normal operation. The pcgp6 signal is a pulse signal output from the command decoder. When the pcgp6 is generated by the precharge command, the pcgp9 signal is generated after a predetermined time.

As can be seen from the circuit of Fig. 2, in the conventional case, the delay time until the pulse signal pcgp6 is output as the pulse signal pcgp9 is always constant regardless of the operating frequency of the memory device. For this reason, in the related art, when the operating frequency of the memory device is increased, it is inevitable to lose the write recovery time. In addition, in the related art, in order to change the delay time until the pulse signal pcgp6 is output as the pulse signal pcgp9, the metal option has to be modified through the FIB operation. For this reason, in the conventional case, there is a problem in that a large cost and time are consumed for delay time tuning.

The present invention has been proposed to solve the above-described problem, and proposes a method of controlling a delay time until a predetermined input signal is applied to the precharge pulse signal generation circuit and output according to an operating frequency of the memory device.

In addition, the present invention is to provide a method that can adjust the delay time in the precharge pulse signal generation circuit using CL (column latency) that varies depending on the operating frequency of the memory device.

In addition, the present invention provides a precharge pulse signal generation circuit that can be used universally even when the operating frequency of the memory device changes.

 In addition, the present invention proposes a method of adjusting a delay time of a precharge pulse signal generation circuit using an external address signal in a test mode.

According to a first embodiment of the present invention, a tDPL (tDPL: precharge pulse signal generated internally by a precharge command is generated from a time when a cas pulse generated internally by a write command is generated according to a change in an operating frequency of a memory device. 12. A method of controlling a time to an occurrence time point, the method comprising: (a) receiving a first precharge pulse signal generated by the precharge command; (b) generating a second precharge pulse signal by delaying the first precharge pulse signal for a predetermined time using a cascade latency signal that changes according to a change in an operating frequency of a memory device; (c) selecting an occurrence time point of the second precharge pulse signal as an end time point of the tDPL.
In the following description of the present invention, the first precharge pulse signal is generated by the precharge command to be the input signal pcgp6 of the precharge pulse signal generation circuit, and the second precharge pulse signal is the output signal pcgp9 of the precharge pulse signal generation circuit. Will be described by way of example.

In a first embodiment, step (b) includes increasing the predetermined time when the cas latency increases.

According to a second embodiment of the present invention, a method of measuring tDPL according to a change in an operating frequency of a memory device includes providing an address buffer for receiving an address signal; Providing a precharge pulse signal generation circuit configured to receive an address signal output from the address buffer in a test mode, receive a first precharge pulse signal, delay a predetermined time, and output a second precharge pulse signal; Providing a data output buffer receiving the second precharge pulse signal from the precharge pulse signal generation circuit and transferring the second precharge pulse signal to a data pad; Checking a time point when the second precharge pulse signal reaches the data pad.

In a second embodiment, the delay time in the precharge pulse signal generation circuit changes in accordance with a variation in cas latency that varies with the operating frequency of the memory device.

(Example)

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

FIG. 3 is an embodiment of a precharge pulse signal generation circuit according to the present invention capable of adjusting a delay time of an output signal according to an operating frequency of a memory device.

In FIG. 3, tmz_1 is a control signal for determining whether the test mode is in the test mode. cl2 represents a case where the column latency is 2, cl3 represents a case where the column latency is 3, cl4 represents a case where the column latency is 4, and cl5 represents a case where the column latency is five. add_0 and add_1 are external address signals and used in a test mode. The function of each of these signals will be described in more detail with reference to FIGS. 4 and 5. Among the signals used in FIG. 3, the pcgp6, bankt4, at <10>, pwrup, and tm_reset signals have already been described with reference to FIG. 2, and thus detailed descriptions thereof will be omitted.

The precharge pulse signal generation circuit of the present invention shown in FIG. 3 includes an input buffer 310 for receiving the input signal pcgp6, a mode selection unit 320 for selecting whether the operation mode is the normal mode or the test mode, and the variable delay unit. 300.

The input buffer 310 includes an inverter INV31 that receives the input signal pcgp6, an inverter INV32 that receives the output signal of the inverter INV31, and a PMOS transistor connected in series between the power supply voltage and the node NODE1. P31 and NMOS transistor N31, NMOS transistor N32 and NMOS transistor N33 connected in parallel between node NODE1 and ground voltage, and PMOS transistor connected between power supply voltage and node NODE1. P32 and an inverter INV33 connected between the node NODE1 and the PMOS transistor P32. The output terminal of the inverter INV32 is connected to the common gate of the PMOS transistor P31 and the NMOS transistor N31. The bankt4 signal is applied to the gate of the NMOS transistor N32, and the at <10> signal is applied to the gate of the NMOS transistor N33.

The mode selector 320 is composed of a NAND gate having three input terminals. The mode selector 320 receives an output signal of the input buffer 310, an inverted signal of pwrup, and an inverted signal of tm_resetp through three input terminals. Here, pwrup is inverted by the inverter INV34, and tm_resetp is inverted by the inverter INV35.

In normal operation, the pwrup and tm_resetp signals remain low. In test mode, the tm_resetp signal remains at a high level.

The variable delay unit 300 delays the output signal of the mode selector 320 for a predetermined time, and the delay degree is determined by a plurality of signals tmz_1, cl2, cl3, cl4, cl5, add_0 and add_1. For convenience of explanation, the delay period in the variable delay unit 300 is indicated by A-B.

The output signal of the variable delay unit 300 is output after passing through the plurality of inverters INV36, INV37, and INV37. Therefore, the final output signal of the precharge pulse signal generation circuit is pcgp9Z.

In normal operation, the precharge pulse signal pcgp6 generated by the command decoder passes through the input buffer 310, the mode selector 320, and the variable delay unit 300, and then is output as pcgp9z. In this case, the total delay time may be adjusted by adjusting the delay time of the variable delay unit.

4 and 5 are examples of the variable delay unit 300 illustrated in FIG. 3.

4 is a circuit diagram illustrating a method of controlling the delay time of the variable delay unit 300 by the column latency signals cl2, cl3, cl3, cl4, and cl5. FIG. 5 is a circuit located between C-D of FIG. 4 and is a delay circuit for further tuning the delay amount determined by the column latency signal when entering the test mode. The circuit of FIG. 5 uses the address signals add_0 and add_1 to control the additional delay amount.

Hereinafter, the circuit of FIG. 4 and FIG. 5 is demonstrated concretely.

4 includes a plurality of delay units 401, 402, 403, 404 and switching elements 411, 412, 413, 414, 415, 416 controlled by a column latency signal. In Figure 4, the total delay time is from A to B. Here, A and B of FIG. 4 are the same as A and B of FIG.

In FIG. 4, the column latency signals cl2, cl3, cl4, cl5 passing through the inverter are represented by column latency bar signals cl2z, cl3z, cl4z, cl5z.

The signal input through the node A of FIG. 4 is an output signal of the mode selector 320 of FIG. 3.

In FIG. 4, the turn on / off operations of the switching elements 411 and 414 are controlled by the column latency signals cl2z and cl3z. The turn on / off operation of the switching element 412 is controlled by the column latency signal cl4z. The turn on / off operation of the switching element 413 is controlled by the column latency signal cl5z. The turn on / off operation of the switching element 415 is controlled by the column latency signal cl2z. The turn on / off operation of the switching element 416 is controlled by the test mode signal tmz_1.

In operation, when the column latency is 2 or 3 (that is, when cl2 and cl3 are high levels), the output signal of the NAND gate NAND41 that receives the column latency signals clz2 and clz3 is at a high level. Thus, switching elements 411 and 414 are turned on. Therefore, the signal input through the node A passes through the delay units 401, 402, 403, 404. Herein, when the column latency is 2, the signal passing through the switching element 414 is transmitted to the node C through the delay unit 404, but when the column latency is not 2, the switching element ( The signal passed through 414 is passed directly to the C node.

In operation, when the column latency is 4 (ie, cl4 is high level), the switching element 412 is turned on. Therefore, the signal input through the node A passes through the delay units 401 and 402. Here, the signal passing through the delay unit 402 has a column latency of 4 and thus cannot pass through the delay unit 404. Accordingly, the signal passing through the delay unit 412 is directly transmitted to the C node.

In operation, when the column latency is 5 (that is, when cl5 is high level), the switching element 413 is turned on. Therefore, the signal input through the node A passes through the delay unit 401 and is then directly transmitted to the node C.

As can be seen above, as the number of column latencies increases (ie, as the operating frequency of the memory device increases), the amount of delay from node A to node C decreases.

The signal on node C is then passed to node B through switching element 416. The switching element 416 is controlled to be turned on / off by the test mode signal tmz_1. In the test mode, the test mode signal tmz_1 is maintained at a low level. In the normal operation mode, the test mode signal tmz_1 maintains a high level.

In the normal operating mode, the signal on the C node passes through the switching element 416 and the inverter INV41 to the B node.

However, in the test mode, the signal on the C node is output to the node D via the circuit shown in FIG. 5, and then passed to the B node through the switching element 416 and the inverter INV41 of FIG. 4. C and D in FIG. 4 are the same as C and D in FIG. That is, the circuit of FIG. 5 shows a circuit located between the C node and the D node of FIG.

The circuit of FIG. 5 is a configuration circuit of the precharge pulse signal generation circuit shown in FIG. 3 and is a circuit used in the test mode.

5 includes a plurality of delay units 501, 502, 503, 504 and switching elements 511, 512, 513, 514, 515 controlled by an address signal. In Figure 5, the total delay time is from C to D. Here, C and D in FIG. 5 are the same as C and D in FIG. 4.

In FIG. 5, address signals add_0 and add_1 passing through the inverter are represented by address bar signals add_0b and add_1b. By the combination of the address signals, selection signals sel_3z, sel_2z, sel_1z and sel_0z for controlling the turning on / off of the switching elements are made.

As shown in FIG. 5, when the address signals add_0 and add_1 are (Low, Low), the selection signal sel_3z is enabled low. When the address signals add_0 and add_1 are (Low, High), the selection signal sel_2z is enabled low. When the address signals add_0 and add_1 are (High, Low), the selection signal sel_1z is enabled low. When the address signals add_0 and add_1 are (High, High), the selection signal sel_0z is enabled low.

In FIG. 5, the turn on / off operation of the switching elements 511 and 514 is controlled by the selection signals sel2z and sel3z. The turn on / off operation of the switching element 512 is controlled by the selection signal sel1z. The turn on / off operation of the switching element 513 is controlled by the selection signal sel0z. The turn on / off operation of the switching element 515 is controlled by the selection signal sel3z.

In operation, when the selection signals sel2z and sel3z are (Low, Low), the output signal of the NAND gate NAND51 which receives the selection signals sel2z and sel3z is at a high level. Thus, switching elements 511 and 514 are turned on. Accordingly, the signal input through the C node passes through the delay units 501, 502, and 503. Here, when the selection signal sel3z is at the low level, the signal passing through the delay unit 503 is passed through the delay unit 504 and then passed through the inverters INV51 and INV52 to the D node. If the selection signal sel3z is at a high level, the signal passing through the delay unit 503 is directly passed through the inverters INV51 and INV52 to the D node. Therefore, when the selection signals sel2z and sel3z are (Low, Low), the signal passing through the delay unit 503 passes through the delay unit 504 and then passes through the inverters INV51 and INV52 to the D node. do.

In operation, when the selection signal sel1z is (Low), the switching element 512 is turned on. Therefore, the signal input through the C node passes through the delay units 501 and 502. In this case, since the selection signal sel3z is at a high level, the signal passing through the delay unit 502 is transmitted to the D node through the inverters INV51 and INV52.

In operation, when the selection signal sel0z is Low, the switching element 513 is turned on. Therefore, the signal input through the C node passes through the delay unit 501. In this case, since the selection signal sel3z is at a high level, the signal passing through the delay unit 501 is transmitted to the D node through the inverters INV51 and INV52.

As shown in FIG. 5, in the test mode, the delay time from the node C to the node D may be adjusted by using the selection signal generated by the combination of the external address signals add_0 and add_1.

FIG. 6 is a waveform diagram of the precharge pulse signal generating circuit of the present invention shown in FIG. 3. 6 shows the case of the normal mode. Thus, while the circuit of FIG. 4 operates, the circuit of FIG. 5 does not. As described above, in the normal operation mode, pwrup maintains a low level, and the test mode signal tmz_1 maintains a high level. In addition, the test mode reset pulse signal tm_resetp maintains a low level. Bankt4 remains at a high level to enable only certain banks. Thus, at <10>, the signal that enables all banks, remains at a low level.

As can be seen from FIG. 6, it can be seen that the delay time until the input signal pcgp6 of the precharge pulse signal generation circuit of FIG. 3 increases as the number of cas latencys increases. That is, it can be seen that the present invention can maintain an appropriate tDPL even if the operating frequency of the memory device is increased by using the cascade (see FIG. 1B).

7 shows a waveform diagram in a test mode. In the test mode, the test mode signal tmz_1 is kept at a low level. Thus, both the circuits of FIGS. 4 and 5 operate. That is, in FIG. 4, a signal arriving at node C through node A is applied to the circuit of FIG. 5 and transmitted to node D. In this case, the amount of time delay from node C to node D is determined according to the selection signal generated by the combination of the address signals.

 As shown in FIG. 7, when the cascading time is 2, the total delay amount when the select signal selz3 is at the low level is A, and the total delay amount when the select signal selz2 is at the low level is B. When the select signal selz1 is at the low level, the total delay amount is C, and when the select signal selz0 is at the low level, the total delay amount is D. That is, the delay degree is A> B> C> D. to be. This result is apparent from the circuit of FIG. In FIG. 7, it can be seen that similar results can be obtained when the cas latency is 2 even when the cas latency is 3, 4, and 5.

Next, a second embodiment of the present invention will be described.

The second embodiment of the present invention provides a method for externally measuring a delay time by using the above-described precharge pulse signal generation circuit.

8 is a circuit capable of measuring a delay time of a precharge pulse signal generation circuit using a pad used for packaging according to a second embodiment of the present invention.

As shown, the second embodiment includes an address buffer 800, a precharge pulse signal generation circuit 810, and a data output buffer 820. Internal circuit 81 represents a general internal circuit of a memory device that receives an external address signal. The internal circuit 82 is a circuit for transferring data up and dnb to the data output buffer 820.

An example of the address buffer 800 is shown in FIG. 9, and an example of the data output buffer 820 is shown in FIG. 10. The precharge pulse signal generation circuit 810 is the same as the precharge pulse signal generation circuit shown in FIG. 3.

9 is an example of an address buffer according to the present invention.

In Fig. 9, in the normal operation mode, the test mode signal tmz_2 is at a high level. In this case, therefore, the external address is applied to the internal circuit 81 of FIG. On the other hand, in the test mode, the test mode signal tmz_2 is at a low level. In this case, therefore, the external address is applied to the precharge pulse signal generation circuit 810.

10 is an example of a data output buffer according to the present invention.

In Fig. 10, in the normal operation mode, the test mode signal tmz_2 is in a high level. Therefore, in this case, data up and dnb are normally delivered to the DQ pad. On the other hand, in the test mode, the test mode signal tmz_2 is at a low level. In this case, transfer of data up and dnb is cut off, and the signal pcgp9z output from the precharge pulse signal generation circuit 810 of FIG. 8 is transferred to the DQ pad.

As shown in FIGS. 8 to 10, in the test mode, the external addresses add_0 and add_1 are applied through the pad while the test mode signal tmz_2 is kept at a low level. Therefore, by measuring the time until the input signal pcgp6 applied to the precharge pulse signal generation circuit 810 is output to the DQ pad of the data output buffer 820, the precharge pulse signal generation circuit 810 Delay time can be measured.

FIG. 11 shows an output waveform diagram of the second embodiment of the present invention shown in FIG. That is, the present invention provides a method of checking the time delay of the precharge pulse signal generation circuit by applying an address signal and a test mode signal through the pad.

In the normal mode, the test mode signal tmz_2 is maintained at a high level.

As shown in FIG. 11, in the normal mode, it can be seen that the data signals up1 and dn1b are transmitted to the output pad DQ of the data output buffer.

On the other hand, in the test mode, the test mode signal tmz_2 is maintained at a low level. In this case, the signal pcgp6 applied to the precharge pulse signal generation circuit 810 is output as an inverted signal pcgp9z after a predetermined time, and the output signal pcgp9z of the precharge pulse signal generation circuit 810 is data. It can be seen that it is delivered to the output pad DQ of the output buffer.

As can be seen from the above, the present invention provides a method of increasing the internal tDPL when the operating frequency of the memory device is increased. The present invention provides a method of increasing the internal tDPL by using a cascading time that varies according to an increase in operating frequency.

When using the method according to the present invention, the delay time of the pulse signal output from the internal precharge pulse signal generation circuit is varied to enable stable operation even if the operating frequency changes.                     

In addition, the present invention provides a method for measuring an internal delay time by using an address signal pad, which has an advantage of increasing production cost and yield.

Claims (8)

delete delete TDPL (tDPL: time from when a cas pulse generated internally by a write command is generated to when an internally generated precharge pulse signal is generated by a precharge command) according to a change in an operating frequency of a memory device As (a) receiving a first precharge pulse signal generated by the precharge command; (b) generating a second precharge pulse signal by delaying the first precharge pulse signal for a predetermined time using a cascade latency signal that changes according to a change in an operating frequency of a memory device; (c) selecting an occurrence time point of the second precharge pulse signal as an end time point of the tDPL; TDPL control method according to a change in an operating frequency of a memory device including a. The method of claim 3, wherein step (b) Increasing the constant time if the cas latency increases; TDPL control method according to the operating frequency of the memory device. The tDPL control method according to claim 4, wherein, in the test mode, an external address is applied to control the timing of generating the second precharge pulse signal. A tDPL measurement method according to a change in operating frequency of a memory device, Providing an address buffer for receiving an address signal; Providing a precharge pulse signal generation circuit configured to receive an address signal output from the address buffer in a test mode, receive a first precharge pulse signal, delay a predetermined time, and output a second precharge pulse signal; ; Providing a data output buffer receiving the second precharge pulse signal from the precharge pulse signal generation circuit and transferring the second precharge pulse signal to a data pad; And checking a time point when the second precharge pulse signal reaches the data pad. The tDPL measurement method according to a change in operating frequency of a memory device. The method of claim 6, And a delay time in the precharge pulse signal generation circuit is changed according to a change in cas latency, which is changed according to an operating frequency of the memory device. 8. The method of claim 7, wherein the delay time in the precharge pulse signal generation circuit is further adjustable using the address signal.

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