KR100587025B1 - Latch Structure of Semiconductor Memory - Google Patents
Latch Structure of Semiconductor Memory Download PDFInfo
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- KR100587025B1 KR100587025B1 KR1019980063545A KR19980063545A KR100587025B1 KR 100587025 B1 KR100587025 B1 KR 100587025B1 KR 1019980063545 A KR1019980063545 A KR 1019980063545A KR 19980063545 A KR19980063545 A KR 19980063545A KR 100587025 B1 KR100587025 B1 KR 100587025B1
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 26
- 239000000758 substrate Substances 0.000 claims abstract description 6
- 239000011229 interlayer Substances 0.000 claims description 4
- 238000000034 method Methods 0.000 abstract description 5
- 239000010410 layer Substances 0.000 description 10
- 238000010586 diagram Methods 0.000 description 8
- 239000012535 impurity Substances 0.000 description 2
- 239000002184 metal Substances 0.000 description 2
- 238000005468 ion implantation Methods 0.000 description 1
- 150000002500 ions Chemical class 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 229920005591 polysilicon Polymers 0.000 description 1
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- G—PHYSICS
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- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
- G11C7/1015—Read-write modes for single port memories, i.e. having either a random port or a serial port
- G11C7/1039—Read-write modes for single port memories, i.e. having either a random port or a serial port using pipelining techniques, i.e. using latches between functional memory parts, e.g. row/column decoders, I/O buffers, sense amplifiers
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- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/10—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
- H01L27/105—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration including field-effect components
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Abstract
본 발명은 반도체 메모리의 래치부 구조에 관한 것으로, 종래에는 래치부가 메모리 셀의 피치 범위를 벗어나게 됨에 따라 전체적인 반도체 메모리의 면적이 증가되는 문제점과; 제1,제2피모스 트랜지스터의 드레인을 비트라인 및 비트바라인에 접속시킬 때, 내부접속층이 요구됨에 따라 공정이 복잡해지는 문제점이 있었다. 따라서, 본 발명은 반도체기판 상에 형성된 피웰(21A) 및 엔웰(21B)과; 상기 피웰(21A)과 엔웰(21B) 상에 일측이 돌출된 형태를 갖는 직사각형이 이격되어 각기 맞물리도록 형성된 액티브영역(22A,22B)(22C,22D)과; 상기 액티브영역(22A,22C)의 상부를 가로지르며, 액티브영역(22B)의 돌출부와 접속되는 돌출부를 갖는 게이트(23A) 및 상기 액티브영역(22B,22D)의 상부를 가로지르며, 액티브영역(22A)의 돌출부와 접속되는 돌출부를 갖는 게이트(23B)와; 상기 액티브영역(22A∼22D) 상에 전원인가 배선과 접속되는 콘택(24A∼24D)과; 상기 게이트(23A,23B)의 상부에 형성된 비트바라인() 및 비트라인(BL)과; 상기 게이트(23B), 액티브영역(22A)의 돌출부와 비트라인(BL)을 접속하는 버티드 콘택(25A)과; 상기 게이트(23A), 액티브영역(22B)의 돌출부와 비트바라인()을 접속하는 버티드 콘택(25B)과; 상기 액티브영역(22C)의 돌출부와 비트라인(BL)을 접속하는 콘택(25C)과; 상기 액티브영역(22D)의 돌출부 및 비트바라인()을 접속하는 콘택(25D)으로 이루어지는 반도체 메모리의 래치부 구조를 제공하여 래치부가 메모리 셀의 피치 범위 내에 구현됨에 따라 전체적인 반도체 메모리의 면적을 감소시킬 수 있는 효과와 아울러 제1,제2피모스 트랜지스터의 드레인을 버티드 콘택을 통해 비트라인 및 비트바라인에 접속시킴에 따라 내부접속층을 형성할 필요가 없게 되므로, 공정의 단순화에도 기여하는 효과가 있다. The present invention relates to a structure of a latch portion of a semiconductor memory, and has a problem in that the area of the entire semiconductor memory increases as the latch portion is out of the pitch range of the memory cell; When the drains of the first and second PMOS transistors are connected to the bit lines and the bit bar lines, there is a problem in that the process becomes complicated as an internal connection layer is required. Accordingly, the present invention provides a Pwell 21A and an Enwell 21B formed on a semiconductor substrate; Active regions 22A and 22B (22C and 22D) formed so as to be spaced apart from each other by a rectangle having one side protruding from the pewell 21A and the enwell 21B; A gate 23A having a protrusion connected to the protrusion of the active region 22B and an upper portion of the active region 22B and 22D and crossing the upper portion of the active region 22A and 22C, and an active region 22A. A gate 23B having a protrusion connected to a protrusion of the < RTI ID = 0.0 > Contacts 24A to 24D connected to power supply wirings on the active regions 22A to 22D; Bit bar lines (B) and bit lines (BL) formed on the gates (23A, 23B); A butted contact 25A connecting the gate 23B, the protrusion of the active region 22A, and the bit line BL; A butted contact 25B for connecting the gate 23A, the protrusion of the active region 22B, and the bit bar line; A contact 25C connecting the protrusion of the active region 22C and the bit line BL; By providing a latch structure of a semiconductor memory comprising a protrusion 25D connecting the protruding portion of the active region 22D and a bit bar line, the area of the semiconductor memory is reduced as the latch portion is implemented within the pitch range of the memory cell. In addition, since the drains of the first and second PMOS transistors are connected to the bit lines and the bit bar lines through the butted contacts, there is no need to form an internal connection layer, thereby contributing to the simplification of the process. It works.
Description
본 발명은 반도체 메모리의 래치(latch)부 구조에 관한 것으로, 메모리셀의 피치(pitch) 내에 래치부를 구현하여 칩 사이즈(chip size)를 최소화할 수 있는 반도체 메모리의 래치부 구조에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a latch portion structure of a semiconductor memory, and more particularly, to a latch portion structure of a semiconductor memory capable of minimizing chip size by implementing a latch portion within a pitch of a memory cell.
일반적으로, 반도체 메모리의 래치회로는 도1의 회로도에 도시한 바와같이 전원전압(VCC)과 접지 사이에 직렬접속되는 피모스 트랜지스터(PM1) 및 엔모스 트랜지스터(NM1)와; 전원전압(VCC)과 접지 사이에 직렬접속되는 피모스 트랜지스터(PM2) 및 엔모스 트랜지스터(NM2)를 병렬로 접속하여 피모스 트랜지스터(PM1)와 엔모스 트랜지스터(NM1)의 드레인 및 피모스 트랜지스터(PM2)와 엔모스트랜지스터(NM2)의 게이트를 공통접속하여 비트라인(BL)에 접속시키고, 피모스트랜지스터(PM1)와 엔모스 트랜지스터(NM1)의 게이트 및 피모스 트랜지스터(PM2)와 엔모스트랜지스터(NM2)의 드레인을 공통접속하여 비트바라인()에 접속한다.In general, the latch circuit of the semiconductor memory includes a PMOS transistor PM1 and an NMOS transistor NM1 connected in series between the power supply voltage VCC and ground, as shown in the circuit diagram of FIG. PMOS transistor PM2 and NMOS transistor NM2 connected in series between the power supply voltage VCC and ground are connected in parallel to drain and PMOS transistors of PMOS transistor PM1 and NMOS transistor NM1 ( The gates of the PM2) and the NMOS transistor NM2 are connected in common to the bit line BL, and the gates of the PMOS transistor PM1 and the NMOS transistor NM1 and the PMOS transistors PM2 and the ENMOS transistor The drain of (NM2) is connected in common to the bit bar line ().
이때, 도2는 도1의 래치회로를 구현한 래치부의 레이아웃도로서, 이에 도시한 바와같이 반도체기판 상에 형성된 피웰(1A) 및 엔웰(1B)과; 상기 피웰(1A) 및 엔웰(1B) 상에 각각 형성된 액티브영역(2A,2B)과; 상기 액티브영역(2A,2B) 상에 각각 이격 형성된 링형게이트(3A∼3D)와; 상기 링형게이트(3A∼3D)의 내부영역에 불순물이온주입을 통해 각각 형성되는 제1,제2피모스 트랜지스터의 드레인(D1,D2) 및 제1,제2엔모스 트랜지스터의 드레인(D3,D4)과; 불순물이온주입을 통해 상기 링형게이트(3A,3B)의 이격영역에 형성되는 제1,제2피모스 트랜지스터의 공통 소스(S1) 및 링형게이트(3C,3D)의 이격영역에 형성되는 제1,제2엔모스 트랜지스터의 공통 소스(S2)와; 상기 액티브영역(2A,2B)의 상부와 하부를 가로질러 각기 형성되는 비트라인(BL) 및 비트바라인()과; 상기 드레인(D1,D2)과 각기 접속되는 내부접속층(4A,4B)과; 상기 비트라인(BL)과 내부접속층(4A)을 접속시키는 콘택(5A)과; 상기 비트라인(BL)과 링형게이트(3B,3C)를 각기 접속시키는 콘택(5B,5C) 및 비트라인(BL)과 드레인(D4)을 접속시키는 콘택(5D)과; 상기 비트바라인()과 내부접속층(4B)을 접속시키는 콘택(6B)과; 상기 비트바라인()과 링형게이트(3A,3D)를 각기 접속시키는 콘택(6A,6D) 및 비트바라인()과 드레인(D3)을 접속시키는 콘택(6C)과; 상기 공통 소스(S1,S2)와 전원인가 배선(미도시)을 접속시키는 콘택(7A,7B)으로 이루어진다.2 is a layout diagram of a latch unit implementing the latch circuit of FIG. 1, as shown in FIG. 2, with a pewell 1A and an enwell 1B formed on a semiconductor substrate; Active regions 2A and 2B formed on the pewells 1A and enwells 1B, respectively; Ring gates 3A to 3D spaced apart from each other on the active regions 2A and 2B; Drains D1 and D2 of the first and second PMOS transistors respectively formed by implanting impurity ions into the inner regions of the ring gates 3A to 3D, and drains D3 and D4 of the first and second NMOS transistors, respectively. )and; First and second common source S1 of the first and second PMOS transistors formed in the spaced apart regions of the ring gates 3A and 3B through impurity ion implantation and formed in the spaced apart regions of the ring gates 3C and 3D A common source S2 of the second NMOS transistor; A bit line BL and a bit bar line, which are formed across the upper and lower portions of the active regions 2A and 2B, respectively; Internal connection layers 4A and 4B respectively connected to the drains D1 and D2; A contact 5A connecting the bit line BL and the internal connection layer 4A; Contacts 5B and 5C connecting the bit line BL and the ring gates 3B and 3C, respectively, and a contact 5D connecting the bit line BL and the drain D4; A contact 6B for connecting the bit bar line () and the internal connection layer (4B); Contacts (6A, 6D) for connecting the bit bar lines () and ring-shaped gates (3A, 3D), respectively, and contacts (6C) for connecting the bit bar lines () and drains (D3); The contacts 7A and 7B connect the common sources S1 and S2 to a power supply wiring (not shown).
상기한 바와같은 종래의 래치부 레이아웃은 메모리 셀의 피치 범위를 벗어나게 됨에 따라 도3의 반도체메모리 블록도에 도시한 바와같이 2개의 메모리셀 어레이부(12,14)에 대하여 3개의 래치부(11,13,15)가 교번하여 위치한다. As described above, the conventional latch unit layout is out of the pitch range of the memory cell, and thus, as shown in the semiconductor memory block diagram of FIG. 3, three latch units 11 are provided for the two memory cell array units 12 and 14. , And 13 and 15 are alternately located.
또한, 비트라인(BL)과 비트바라인()에 엔형 도핑된 폴리실리콘을 적용함에 따라 제1,제2피모스 트랜지스터의 드레인(D1,D2)과 비트라인(BL) 및 비트바라인()을 각기 접속시킬 때, 금속층인 내부접속층(4A,4B)이 요구된다.In addition, as the n-type doped polysilicon is applied to the bit line BL and the bit bar line, the drains D1 and D2 of the first and second PMOS transistors, the bit line BL, and the bit bar line When connecting to each other, the internal connection layers 4A and 4B which are metal layers are calculated | required.
상술한 바와같이 종래 반도체 메모리의 래치부 레이아웃은 래치부가 메모리 셀의 피치 범위를 벗어나게 됨에 따라 메모리셀 어레이부의 양측에 위치되어 전체적인 반도체 메모리의 면적이 증가되는 요인으로 작용하는 문제점과; 제1,제2피모스 트랜지스터의 드레인을 비트라인 및 비트바라인에 접속시킬 때, 금속층의 내부접속층이 요구됨에 따라 공정이 복잡해지는 문제점이 있었다.As described above, the latch portion layout of the conventional semiconductor memory has a problem in that the latch portion is located at both sides of the memory cell array portion as the latch portion is out of the pitch range of the memory cell, thereby acting as a factor of increasing the total area of the semiconductor memory; When connecting the drains of the first and second PMOS transistors to the bit lines and the bit bar lines, there is a problem in that the process becomes complicated as the internal connection layer of the metal layer is required.
본 발명은 상기한 바와같은 종래의 문제점을 해결하기 위하여 창안한 것으로, 본 발명의 목적은 래치부를 메모리 셀의 피치 범위 내에 형성함과 아울러 제1,제2피모스 트랜지스터의 드레인을 직접적으로 비트라인 및 비트바라인에 접속시킬 수 있는 반도체 메모리의 래치부 구조를 제공하는데 있다. SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned conventional problems, and an object of the present invention is to form a latch portion within a pitch range of a memory cell and to directly drain the first and second PMOS transistors. And a latch portion structure of a semiconductor memory that can be connected to a bit bar line.
상기한 바와같은 본 발명의 목적을 달성하기 위한 반도체 메모리의 래치부 구조를 도4a 내지 도4c에 도시한 수순단면도를 참조하여 상세히 설명하면 다음과 같다.The latch portion structure of the semiconductor memory for achieving the object of the present invention as described above will be described in detail with reference to the cross-sectional view shown in Figures 4a to 4c.
먼저, 도4a에 도시한 바와같이 반도체기판 상에 피웰(21A)과 엔웰(21B)을 형성하고, 상기 피웰(21A)과 엔웰(21B) 상에 직사각형의 일측이 돌출된 형태를 갖는 액티브영역(22A,22B)(22C,22D)이 이격되어 각기 맞물리도록 형성한다.First, as shown in FIG. 4A, a pwell 21A and an enwell 21B are formed on a semiconductor substrate, and an active region having a form in which one side of the rectangle protrudes on the pwell 21A and the enwell 21B is formed. 22A, 22B) and 22C, 22D are spaced apart to engage with each other.
그리고, 도4b에 도시한 바와같이 상기 액티브영역(22A,22C)의 상부를 가로지르며, 액티브영역(22B)의 돌출부와 접속되는 돌출부를 갖는 게이트(23A) 및 상기 액티브영역(22B,22D)의 상부를 가로지르며, 액티브영역(22A)의 돌출부와 접속되는 돌출부를 갖는 게이트(23B)를 형성함과 아울러 상기 액티브영역(22A∼22D) 상에 전원인가 배선과 접속되는 콘택(24A∼24D)을 형성한다.As shown in Fig. 4B, the gate 23A and the active regions 22B and 22D, which intersect the upper portions of the active regions 22A and 22C and are connected to the protrusions of the active regions 22B, are formed. A gate 23B is formed across the upper portion, the gate 23B having a protrusion connected to the protrusion of the active region 22A, and contacts 24A to 24D connected to the power supply wiring on the active regions 22A to 22D. Form.
그리고, 도4c에 도시한 바와같이 상기 게이트(23A,23B)의 상부에 비트바라인() 및 비트라인(BL)을 형성하고, 상기 게이트(23B), 액티브영역(22A)의 돌출부와 비트라인(BL)을 접속하는 버티드(butted) 콘택(25A)과; 상기 게이트(23A), 액티브영역(22B)의 돌출부와 비트바라인()을 접속하는 버티드 콘택(25B)과; 상기 액티브영역(22C)의 돌출부와 비트라인(BL)을 접속하는 콘택(25C)과; 상기 액티브영역(22D)의 돌출부 및 비트바라인()을 접속하는 콘택(25D)을 형성한다.As shown in FIG. 4C, the bit bar line and the bit line BL are formed on the gates 23A and 23B, and the protrusions and the bit lines of the gate 23B and the active area 22A are formed. Butted contact 25A for connecting BL; A butted contact 25B for connecting the gate 23A, the protrusion of the active region 22B, and the bit bar line; A contact 25C connecting the protrusion of the active region 22C and the bit line BL; A contact 25D is formed to connect the protrusion of the active region 22D and the bit bar line.
한편, 도5는 도4c의 X-X선 단면을 간략하게 보인 단면도로서, 이에 도시한 바와같이 반도체기판 상의 필드영역(31A∼31C)을 통해 격리 형성된 액티브영역(22A,22B) 상에 피웰(21A)과 엔웰(21B)이 각각 형성되고, 상기 액티브영역(22A)의 상부에 게이트(23A)가 형성됨과 아울러 필드영역(31B)의 상부를 거쳐 액티브영역(22A,22B)의 상부에 게이트(23B)가 형성되며, 상기 게이트(23A,23B)가 형성된 구조물 상에 층간절연막(32)을 전체적으로 증착하여 평탄화한 다음 게이트(23A,23B) 사이의 이격영역 및 게이트(23B)의 일부가 동시에 노출되는 버티드 콘택홀을 형성하고, 상기 게이트(23A) 상의 층간절연막(32) 상부에 비트바라인()을 형성함과 아울러 상기 게이트(23B) 상의 층간절연막(32) 상부에 상기 버티드 콘택홀이 채워져 형성되는 버티드 콘택(25A)과 접속된 비트라인(BL)을 형성한다.FIG. 5 is a cross-sectional view schematically illustrating the cross-section of the XX line of FIG. 4C, and the pewell 21A is formed on the active regions 22A and 22B separated through the field regions 31A to 31C on the semiconductor substrate. And enwells 21B are formed, respectively, a gate 23A is formed on the active region 22A, and a gate 23B is formed on the active regions 22A and 22B through the field region 31B. Is formed, and the interlayer insulating film 32 is entirely deposited and planarized on the structure where the gates 23A and 23B are formed. A contact hole is formed, a bit bar line () is formed on the interlayer insulating layer 32 on the gate 23A, and the butted contact hole is filled on the interlayer insulating layer 32 on the gate 23B. A bit line BL connected to the butted contact 25A is formed. .
상기한 바와같은 본 발명에 의한 반도체 메모리의 래치부 구조는 메모리 셀의 피치 범위 내에 구현됨에 따라 도5의 블록도에 도시한 바와같이 2개의 메모리셀 어레이부(41,43)에 대해 1개의 래치부(42)가 중앙에 위치할 수 있게 된다.The latch structure of the semiconductor memory according to the present invention as described above is implemented within the pitch range of the memory cell, so that one latch is provided for the two memory cell array portions 41 and 43 as shown in the block diagram of FIG. The part 42 can be located at the center.
상술한 바와같이 본 발명에 의한 반도체 메모리의 래치부 구조는 래치부가 메모리 셀의 피치 범위 내에 구현됨에 따라 전체적인 반도체 메모리의 면적을 감소시킬 수 있는 효과와 아울러 제1,제2피모스 트랜지스터의 드레인을 버티드 콘택을 통해 비트라인 및 비트바라인에 접속시킴에 따라 내부접속층을 형성할 필요가 없게 되므로, 공정의 단순화에도 기여하는 효과가 있다. As described above, the latch structure of the semiconductor memory according to the present invention can reduce the area of the entire semiconductor memory as the latch portion is implemented within the pitch range of the memory cell, and the drain of the first and second PMOS transistors can be reduced. By connecting to the bit line and the bit bar line through the butted contact, there is no need to form an internal connection layer, thereby contributing to the simplification of the process.
도1은 일반적인 반도체 메모리의 래치회로를 보인 회로도.1 is a circuit diagram showing a latch circuit of a general semiconductor memory.
도2는 종래 반도체 메모리의 래치부를 구현한 레이아웃도.2 is a layout diagram implementing a latch unit of a conventional semiconductor memory.
도3은 종래 반도체 메모리의 개략적인 블록도.3 is a schematic block diagram of a conventional semiconductor memory;
도4는 본 발명의 일 실시예에 따른 수순단면도.Figure 4 is a cross-sectional view of the procedure according to an embodiment of the present invention.
도5는 본 발명에 의한 반도체 메모리의 개략적인 블록도.5 is a schematic block diagram of a semiconductor memory according to the present invention;
***도면의 주요 부분에 대한 부호의 설명****** Description of the symbols for the main parts of the drawings ***
21A:피웰 21B:엔웰21A: Pewell 21B: Enwell
22A∼22D:액티브영역 23A,23B:게이트22A to 22D: Active areas 23A and 23B: Gate
24A∼24D,25C,25D:콘택 25A,25B:버티드 콘택24A to 24D, 25C, 25D: Contact 25A, 25B: Butted Contact
BL:비트라인 :비트바라인BL: Bit Line: Bit Bar Line
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Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR950012607A (en) * | 1993-10-14 | 1995-05-16 | 제임스 조셉 드롱 | Method for pretreating aluminum containing surfaces of deposition chamber before depositing tungsten silicide coating on semiconductor substrate |
| JPH10200064A (en) * | 1996-10-31 | 1998-07-31 | Texas Instr Inc <Ti> | Semiconductor memory device |
| KR19990069611A (en) * | 1998-02-11 | 1999-09-06 | 구본준 | Sense Amplifier Structure of Semiconductor Memory |
| KR100305031B1 (en) * | 1998-05-30 | 2001-11-22 | 윤종용 | Lay-out of sense amplifier block in dram |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR950012607A (en) * | 1993-10-14 | 1995-05-16 | 제임스 조셉 드롱 | Method for pretreating aluminum containing surfaces of deposition chamber before depositing tungsten silicide coating on semiconductor substrate |
| JPH10200064A (en) * | 1996-10-31 | 1998-07-31 | Texas Instr Inc <Ti> | Semiconductor memory device |
| KR19990069611A (en) * | 1998-02-11 | 1999-09-06 | 구본준 | Sense Amplifier Structure of Semiconductor Memory |
| KR100305031B1 (en) * | 1998-05-30 | 2001-11-22 | 윤종용 | Lay-out of sense amplifier block in dram |
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