KR100585641B1 - Structure for infinite impulse response filter - Google Patents

Abstract

The present invention relates to the structure of an infinite impulse response filter. In the prior art, since the IIR filter has an internal block in the form of a feedback, it is quite difficult to maintain timing by using a pipeline unlike the FIR filter. Therefore, there has been a problem that the mounting test using the FPGA causes a considerable difficulty in meeting the required timing. Accordingly, the present invention relates to a filter having a critical path by an adder connected to two or more sequentially through a round / limiting unit for limiting a range of input signal and round-off noise, so that the first pipeline directs the direct adder directly from the front end. and; The round flag setting unit for setting the round flag and the second pipe line which leads through the delayer to the adder are configured in parallel, and the rounding flag is used to process the rounding in parallel with the feedback path, thereby reducing the delay caused by the round. The ability to remove them effectively allows for fairly fast testing even in field test applications such as FPGAs, where fast timing cannot be achieved, and facilitates the application of filters to high-speed communication systems.

Description

Structure of Infinite Impulse Response Filter {STRUCTURE FOR INFINITE IMPULSE RESPONSE FILTER}

1 is a block diagram showing the structure of a conventional infinite impulse response filter.

Figure 2 is a block diagram showing the structure of an infinite impulse response filter according to the present invention.

*** Description of the symbols for the main parts of the drawings ***

10: round flag setting unit 20: retarder

The present invention relates to the structure of the infinite impulse response filter, and more particularly to the structure of the infinite impulse response filter that can have a high-speed operating characteristics while minimizing the round-off noise of the filter.

Filters that limit the frequency characteristics of a signal are essential in a communication system and are important enough to determine the performance of the system as a whole.

In addition, unlike an analog filter, a digital filter having the above characteristics processes a quantized signal and accordingly, a rounding or limiting function is required.

However, the above functions (rounding, limiting) are additional functions required for the implementation of the digital filter. Therefore, the design speed must be considered in the design because it reduces the computational speed of the filter and reduces the speed of the entire system. Should be

On the other hand, there are finite impulse response filter (FIR) and infinite impulse response filter (IIR: INFINITE IMPULSE RESPONSE) structures.

Since the structure of the dual FIR filter is feedforward, the pipeline register can be used to maintain or increase the speed even when the above rounding or limiting function is inserted.

)에 대한 종래의 무한 임펄스 응답 필터의 구조를 보인 블록도로서, 이에 도시된 바와 같이 유리함수의 분자부분은 피드 포워드부(1)에서 처리하고, 분모부분은 피드백부에서 처리하도록 구성되어 있는데, 상기 피드백부에서 직렬로 연결된 2개의 덧셈기(S1,S2)와 바로 앞단에 라운드/리미팅부(3)가 연결되어 하나의 패스(Path)를 이루고 있는데, 바로 이 부분이 전체 IIR필터의 크리티컬 패스(Critical Path : 가장 지연이 큰 패스)가 되며 필터의 속도를 제한하게 된다.1 is a glass function (

As a block diagram showing the structure of a conventional infinite impulse response filter for), the molecular part of the glass function is processed in the feed forward part 1 and the denominator is processed in the feedback part, as shown here. Two adders S1 and S2 connected in series in the feedback unit and the round / limiting unit 3 are connected to the front end to form one path, which is the critical path of the entire IIR filter. Critical Path: This is the path with the most delay and limits the speed of the filter.

Therefore, while an IIR filter with an adder already designed and libraryed is the easiest way to speed up its timing, it is easiest to use pipeline registers, but to maintain the signal passing characteristics of the filter, it is necessary to insert a pipeline between adders. If you change the front round / limiting part to the truncation function, this part can only improve the timing because only the adder remains, but the overall round off noise of the filter increases. Performance is bad.

In other words, the second or more IIR filter has two or more sequentially added adders to the internal feedback part. In this way, a pipeline for increasing the speed may be inserted between adders calculated in series. In this situation, if the rounding and limiting functions are performed in addition to the addition operation, the filter will slow down considerably if the internal adder, MUX, etc. are not themselves fast. For FPGA-mounted tests that are difficult to obtain, the filter will not be able to operate above 10 MHz.

As described above, in the conventional technology, since the IIR filter has an internal block in the form of a feedback, it is very difficult to maintain timing by using a pipeline unlike the FIR filter, and thus, when testing the implementation using the FPGA, There was a problem that caused considerable difficulty in meeting the required timing.

Therefore, the present invention has been created to solve the above-mentioned conventional problems, the round flag setting unit for the round flag setting in the case of the round up and down in the case of the round up and the pipeline through the adder through the delay, the round down In this case, by applying the pipeline from the front end to the adder, it provides the structure of infinite impulse response filter that can increase the speed of the filter by eliminating the limiting part, which is the biggest delay element, while using the rounding function essential for reducing quantization noise. Has its purpose.

In order to achieve the above object, the present invention provides a filter having a critical path by an adder connected to two or more sequentially through a round / limiting unit for limiting a range of roundoff noise and an input signal. A first pipeline to allow; A round flag setting unit for setting a round flag, and a second pipe line through the retarder to communicate with the adder, characterized in that made in parallel.

Hereinafter, with reference to the accompanying drawings an embodiment according to the present invention taking the conventional glass function (H (z)) as an example as follows.

First, the internal structure of the round / limiting part is connected with a round flag setting part (not shown), a limiting part consisting of an adder (not shown) and a limiter (not shown), and this limiting part is the most important part of the delay factor. .

Therefore, as shown in FIG. 2, the present invention includes: a second pipe line passing from the retarder D2 to the round flag setting unit 10 and the adder S2 via the retarder 20; It can be seen that the limiting part is removed by constructing the first pipeline directly from the retarder D2 to the adder S2 in parallel.

In this way, instead of removing the limiting unit, the adder required for the limiting circuit is to share and use the adder S2 inside the IIR filter.

On the other hand, the round-off noise shows the smallest value in the case of a 2 'complement signal system because of their offset action when both the up and down functions are performed.

Therefore, in the structure according to the present invention, in the case of raising, it is applied after one cycle by the second pipeline configured in parallel with the first pipeline, and in the case of lowering, it is directly passed from the delayer D2 to the adder S2. Round off noise can be reduced by applying the first pipeline.

At this time, the error caused by the rounding applied after one cycle is a very small value corresponding to the value of the least significant bit (LSB), so it has little effect on the characteristics or performance of the filter. Also, the round flag is simply an AND gate logic circuit. Since it is simply implemented, its delay is very small and does not affect high speed operation.

As described above, the structure of the infinite impulse response filter of the present invention uses a rounding flag to process the rounding in parallel with the feedback path, thereby effectively eliminating the delay caused by the round, such as an FPGA, which is difficult to obtain fast timing. Even in the case of mounting test, the test can be performed considerably faster and the filter can be easily applied to a high speed communication system.

Claims (1)

CLAIMS 1. A filter having a critical path by an adder connected to two or more sequentially through a round / limiting unit for limiting a range of round-off noise and an input signal, the filter comprising: a first pipeline directing the adder directly from the front end to the adder; A structure of an infinite impulse response filter, comprising a parallel configuration of a round flag setting unit for setting a round flag, and a second pipeline connected to an adder through a delay unit.

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