KR100585062B1 - Semiconductor memory device having second write data amplifier - Google Patents

Abstract

A semiconductor memory device having a write data secondary amplifier is provided. The semiconductor memory device including the write data secondary amplifier has a cell array block structure having a plurality of matrix forms, an access transistor for connecting a bit line and one end of the cell according to a word line signal, A bit line sense amplifier intersecting the bit line and the bit line bar to amplify the data, and an input / output line and input / output line bar for inputting and outputting data, and a column selection line for connecting the bit line and the bit line bar according to a column selection line signal, respectively. A semiconductor memory device having a gate, comprising: a secondary amplifying unit configured to secondly amplify data input to the input / output line and the input / output line bar and to latch the amplified data when driving an input / output driver for inputting write data, Secondary amplification By latching, the write data can be quickly stored in the bit line and the cell through the column select line gate, thereby increasing the load of the input / output line and reducing the size limitation of the column select line gate, thereby enabling operation at a high frequency.

Description

Semiconductor memory device having a write data secondary amplification unit {Semiconductor memory device having second write data amplifier}

1 is a diagram illustrating a conventional semiconductor memory device.

FIG. 2 is a diagram for describing a data write operation of the semiconductor memory device shown in FIG. 1.

3 is a diagram illustrating a semiconductor memory device including a write data secondary amplifier according to a first embodiment of the present invention.

4 is a diagram illustrating a semiconductor memory device including a write data secondary amplifier according to a second embodiment of the present invention.

FIG. 5 is a diagram for describing a data write operation of the semiconductor memory device shown in FIG. 4.

<Description of the symbols for the main parts of the drawings>

BLK1 ... 2nd amplifier, CELL2 ... cell,

MN5 to MN11 ... NMOS transistors, MP3, MP4 ... PMOS transistors,

NC2 ... Access Transistor, SA2 ... Bitline Sense Amplifier,

U3, U4 ... I / O drivers, U5 ... and gates.

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device, and in particular, a write data secondary amplification unit capable of amplifying write data output from an input / output driver to a secondary to reliably write data without being limited by a write cycle when operating at a high frequency. It relates to a semiconductor memory device provided.

The semiconductor memory device constructed by using a plurality of row addresses and column addresses has a cell array block structure formed of a plurality of matrix forms, and word lines W / L are enabled in the cell array by decoding the row addresses.

After the word line is enabled, a read or write operation of the cell data is performed. When the read is performed, the cell data is sent to the bit line (B / L) and the bit line bar (B / LB) intersected with the word line. The data of the bit line B / L and the bit line bar B / LB are stored in the cell. At this time, the bit line (B / L) and the bit line bar (B / LB) shared with the cell are connected to the input / output line by a column select line gate (CSL Gate). And data of the bit line bar B / LB flows into the input / output line, and at the time of writing, data of the input / output line flows into the bit line B / L and the bit line bar B / LB.

1 shows a conventional semiconductor memory device. The semiconductor memory device shown in FIG. 1 includes a cell CELL1, an access transistor NC1, a bit line sense amplifier SA1, a column select line gate CSLG1, input / output lines IO, IOB, and write. Input / output drivers U1 and U2 for amplifying time data are provided. The sense amplifier SA1 includes NMOS transistors MN1 and MN2 and PMOS transistors MP1 and MP2, and the column select line gate CSLG1 includes transistors MN3 and MN4. In addition, in FIG. 1, the thick solid line display of the input / output lines IO and IOB indicates the loading of the input / output lines IO and IOB according to the position on the chip of the input / output lines IO and IOB.

FIG. 2 is a diagram for explaining a data write operation of the semiconductor memory device shown in FIG. 1 and illustrates changes in cell data. 2A: CSL of FIG. 2 (a) is a decoded signal of a column address and has one enable pulse interval in one cycle, and 2B: IO and IOB of FIG. 2 (b) represent write data in a write cycle. 2C: B / L, B / LB, and 2D: Cell in FIGS. 2C and 2D show bit lines B / L equal to the phase of data passing through the column select line gate CSLG1, respectively. ), Data of the bit line bar B / LB and the cell CELL1.

As the memory density increases, the size of the memory increases, and thus the length of the input / output lines IO and IOB of FIG. 1 increases in proportion to the size of the memory. This increases the line loading of the input / output lines IO and IOB so that 2E: B / L and B / LB in FIG. 2 (e) are 2B later than 2C: B / L and B / LB in FIG. It changes according to the phase of IO and IOB. In addition, since the size of the column select line gate CSLG1 is also limited according to the increase in the degree of integration, if the frequency applied to the memory device becomes high, the cycle times tCC0, tCC1 and tCC2 in FIG. 2E: B / L and B / LB of FIG. 2 (e) are inversely reduced, and data is not completely transmitted in the disable interval of CSL0 as shown in 2C: B / L and B / LB of FIG. 2 (c). 2F: Cell of FIG. 2 (f) is cross-crossed at the end section of tCC0, which causes a problem that the write data during the write cycle is not completely stored in the cell CELL1.

SUMMARY OF THE INVENTION The present invention provides a write data secondary amplification unit capable of amplifying write data output from an input / output driver to a secondary to reliably write data without being limited by the frequency of the write cycle when operating at a high frequency. It is to provide a semiconductor memory device.

In order to achieve the above technical problem, a semiconductor memory device including a write data secondary amplifier according to the present invention has a cell array block structure having a plurality of matrix forms, and a bit line and one end of the cell according to a word line signal. An access transistor for coupling, a bit line sense amplifier intersected with bit lines and bit line bars to amplify the data of the cell, an input / output line and an input / output line bar for inputting and outputting data, and a column selection line for the bit line and bit line bar. A semiconductor memory device having a column selection line gate for connecting to each other according to a signal, comprising: secondly amplifying data input to the input / output line and the input / output line bar when driving an input / output driver for inputting write data, and amplifying the amplified data. Includes Secondary Amplifier for Latching Characterized in that.

The secondary amplifier may include a secondary amplifier sense amplifier including a cross coupled NMOS transistor connected to the input / output line and the input / output line bar, an AND gate to which a write operation signal and a cell array block selection signal are input and logically multiplied. Preferably, the gate includes an NMOS transistor connected to an output terminal of the AND gate, a source is grounded, and a drain connected to the secondary amplifier sense amplifier.

The secondary amplifying unit may include a second amplification sense amplifier including a cross coupled PMOS transistor connected to the input / output line and the input / output line bar, a write operation signal, and a cell array block selection signal to be inverted and logically input. Preferably, the NAND gate and the gate are connected to an output terminal of the NAND gate, an internal power supply voltage is applied to a source, and a drain includes a PMOS transistor connected to the sense amplifier for the secondary amplifier.

Hereinafter, a semiconductor memory device including a write data secondary amplifier according to embodiments of the present invention will be described in detail with reference to the accompanying drawings.

3 is a diagram illustrating a semiconductor memory device including a write data secondary amplifier according to a first embodiment of the present invention. In the semiconductor memory device including the write data secondary amplifier shown in FIG. 3, bits crossed by bit lines B / L and bit line bars B / LB to amplify cell data stored in the cell CELL2. I / O lines IO and I / O line bars IOB, bit lines B / L and bit line bars B / I for inputting and outputting data output from the line sense amplifier SA2 and the input / output drivers U3 and U4. The column select line gate CSLG2 for connecting the LBs according to the column select line signal CSL, and the input / output line IO and the input / output line bar when driving the input / output drivers U3 and U4 for inputting write data. A secondary amplifying unit BLK1 is provided for secondary amplifying the write data input to the IOB and latching the amplified write data.

The secondary amplifier BLK1 includes a secondary amplifier sense amplifier CCSA having cross coupled NMOS transistors MN9 and MN10 connected to the input / output line IO and the input / output line bar IOB, The AND gate U5 and the gate, which are inputted and logically multiplied by the write operation signal PWR and the cell array block selection signal PBLSiD, are connected to the output terminal of the AND gate U5, the source is grounded, and the drain is the secondary amplification sense. The NMOS transistor MN11 connected to the amplifier CCSA is provided.

The bit line sense amplifier SA2 includes the NMOS transistors MN5 and MN6 and the PMOS transistors MP3 and MP4, and the column select line gate CSLG2 includes the NMOS transistors MN7 and MN8. Reference numeral NC2 is an access transistor for connecting the bit line B / L and one end of the cell CELL2 in accordance with the word line signal W / L. In addition, in FIG. 3, the thick solid line display of the input / output line IO and the input / output line bar IOB shows the input / output line IO and the input / output line bar according to the positions of the input / output line IO and the input / output line bar IOB. It indicates the loading of the IOB.

In the semiconductor memory device having the write data secondary amplifier according to the first embodiment of the present invention configured as described above, the write operation signal PWR and the cell array block selection signal PBLSiD are simultaneously enabled as "HIGH". Is turned on, the output of the AND gate U5 is in the "HIGH" state, and the transistor MN11 is turned on. As a result, the drain level of the transistor MN11 is excited to the source level, and the secondary amplifier sense amplifier CCSA connected to the input / output line IO and the input / output line bar IOB is turned on.

If the loading of the input / output line IO and the input / output line bar IOB is increased, and the write data is transmitted to the front end of the column selection line gate CSLG2, a time delay occurs, the cross provided in the secondary amplifier BLK1 A small signal of the input / output line IO and the input / output line bar IOB is secondly amplified by the secondary amplifier sense amplifier CCSA having the coupled NMOS transistors MN9 and MN10 to perform a column select line gate CSLG2. Since the signal at the front end is greatly amplified, the size limitation of the column select line gate CSLG2 can be largely relaxed.

In the above embodiment, a second amplification signal of the input / output line IO and the input / output line bar IOB is used as the secondary amplifier BLK1 to cross-charge the input / output data to the source power source for latching. The second embodiment uses a second coupled sense amplifier CCSA using the cross-coupled PMOS transistors MP5 and MP6 as shown in FIG. 4 and replaces the AND gate U5 of FIG. When the write operation signal PWR and the cell array block selection signal PBLSiD are simultaneously enabled as "HIGH" by using the NAND gate U6, the output of the NAND gate U6 becomes "LOW", The NMOS transistor MN11 of FIG. 3 may be replaced with the PMOS transistor MP7, and the secondary amplifier BLK1 may be configured by applying the internal power supply voltage IVC to the source of the PMOS transistor MP7.

By configuring the secondary amplifier BLK1 as described above, the signal level of the input / output lines IO and IOB during the second amplification of the write data is latched close to the internal power supply voltage IVC, and the column select line gate CSLG2 is used. ) When passing, the write data is transmitted to the bit line (B / L) and the bit line bar (B / LB) faster than the 2B: IO and IOB of FIG. 2 (b), as shown in 4B: IO and IOB of FIG. 5 (b). do.

FIG. 5 is a diagram for describing a data write operation of the semiconductor memory device shown in FIG. 4. 4A: CSL of FIG. 5 (a) is a column select line gate signal receiving a decoding signal of a column address, and 4B: IO and IOB of FIG. 5 (b) are column selection according to a circuit operation of the secondary amplifier BLK1. The data of the input / output line IO and the input / output line bar IOB in front of the line gate CSLG2 are illustrated. As shown in section (*) before 4A: CSL of FIG. 5 (a) is enabled as "HIGH" in 4B: IO and IOB of FIG. 5 (b), the input / output line IO and the input / output line bar IOB. The data cross point of FIG. 2 (b) is generated earlier than the data cross point of 2B: IO and IOB of FIG. 2 (b), so the bit line data of 4C: B / L and B / LB of FIG. 5 (c) and FIG. 5 (d) are shown. It can be seen that the 4D: Cell data of FIG. 5A is transmitted close to the turn-on time of the column select line gate CSLG2 shown in 4A: CSL of FIG.

As described above, in the semiconductor memory device having the write data secondary amplifier according to the present invention, when the line length of the input / output line is increased due to the increase in the integration degree of the memory device, the input / output line is increased when the resistance / capacitance loading of the input / output line is increased. Secondary amplification and latching of the data can be quickly stored in the bit lines and cells through the column select line gates, thereby increasing the load on the input and output lines and reducing the size limit of the column select line gates, enabling operation at high frequencies. There is an advantage.

Claims (3)

A cell array block structure having a plurality of matrix forms, an access transistor for connecting a bit line and one end of the cell according to a word line signal, and bits crossed by bit lines and bit line bars to amplify data of the cell A semiconductor memory device comprising a line sense amplifier, an input / output line and an input / output line bar for inputting and outputting data, and a column selection line gate for connecting the bit line and the bit line bar according to a column selection line signal. And a secondary amplifier configured to second amplify the write data input to the input / output line and the input / output line bar and to latch the amplified write data when driving the input / output driver for inputting write data. 2. The secondary amplifier of claim 1, wherein the secondary amplifier comprises a secondary amplifier sense amplifier including a cross coupled NMOS transistor connected to the input / output line and the input / output line bar, a write operation signal, and a cell array block selection signal. And an NMOS transistor having an AND gate and a gate multiplied by the AND and an output terminal of the AND gate, a source being grounded, and a drain connected to the secondary amplifier sense amplifier. 2. The secondary amplifier of claim 1, wherein the secondary amplifier comprises a secondary amplifier sense amplifier including a cross coupled PMOS transistor connected to the input / output line and the input / output line bar, a write operation signal, and a cell array block selection signal. And a PMOS transistor connected to an NAND gate and a gate inverted and logically connected to an output terminal of the NAND gate, an internal power supply voltage is applied to a source, and a drain connected to the sense amplifier for the second amplification.

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