KR100578827B1 - A plasma display panel and a driving apparatus of the same - Google Patents

Abstract

The present invention relates to a plasma display panel and a driving apparatus thereof.

According to the present invention, a Zener diode is connected between a source and a drain of a separation transistor separating two circuit parts, and a resistor is connected in series.

In this way, by connecting the zener diode between the source and the drain of the isolation transistor, a transistor with low breakdown voltage can be used, thereby reducing the circuit cost.

Plasma display panel, main switch, impedance, zener diode

Description

Plasma display panel and driving device thereof {A PLASMA DISPLAY PANEL AND A DRIVING APPARATUS OF THE SAME}

1 is a partial perspective view of an AC plasma display panel.

2 is an electrode array diagram of a plasma display panel.

3 is a driving waveform diagram of a plasma display panel.

4 is a driving circuit diagram of a conventional plasma display panel for implementing the driving waveform shown in FIG.

5 illustrates a plasma display panel according to an exemplary embodiment of the present invention.

6 is a driving circuit diagram of a plasma display panel according to an embodiment of the present invention.

FIG. 7 is a detailed circuit diagram of the circuit shown in FIG.

The present invention relates to a plasma display panel (PDP) and a driving apparatus thereof.

Recently, flat display devices such as liquid crystal displays (LCDs), field emission displays (FEDs), and PDPs have been actively developed. Among these flat panel display devices, PDPs have advantages of higher luminance and luminous efficiency and wider viewing angles than other flat panel display devices. Therefore, the PDP is in the spotlight as a display device to replace the conventional cathode ray tube (CRT) in a large display device of 40 inches or more.

PDPs are flat display devices that display characters or images using plasma generated by gas discharge, and dozens to millions or more of pixels are arranged in a matrix according to their size. Such PDPs are classified into a direct current type (DC type) and an alternating current type (AC type) according to the shape of the driving voltage waveform applied and the structure of the discharge cell.

In the DC-type PDP, since the electrode is exposed to the discharge space as it is, the current flows in the discharge space while voltage is applied, and there is a disadvantage in that a resistance for current limitation must be made for this purpose. On the other hand, in the AC type PDP, the electrode covers the dielectric layer, so the current is limited by the formation of a natural capacitance component, and the electrode is protected from the impact of ions during discharge.

1 is a partial perspective view of an AC plasma display panel.

As shown in FIG. 1, a scan electrode 4 and a sustain electrode 5 covered with a dielectric layer 2 and a protective film 3 are arranged in parallel on the first glass substrate 1. A plurality of address electrodes 8 are provided on the second glass substrate 6, and the address electrodes 8 are covered by the insulator layer 7. On the insulator layer 7 between the address electrodes 8, partition walls 9 are formed in parallel with the address electrodes 8. In addition, the phosphor 10 is formed on the surface of the insulator layer 7 and on both side surfaces of the partition wall 9. The first glass substrate 1 and the second glass substrate 6 have a discharge space 11 therebetween so that the scan electrode 4 and the address electrode 8 and the sustain electrode 5 and the address electrode 8 are orthogonal to each other. They are arranged to face each other. The discharge space at the intersection of the address electrode 8 and the pair of the scanning electrode 4 and the sustain electrode 5 forms the discharge cell 12.

2 shows an electrode arrangement diagram of the plasma display panel.

As shown in Fig. 2, the PDP electrode has a matrix structure of m x n. Specifically, the address electrodes A1 to Am are arranged in the column direction, and the scan electrodes Y1 to n rows in the row direction. Yn) and sustain electrodes X1 to Xn are arranged in a zigzag. Hereinafter, the scanning electrode will be referred to as "Y electrode" and the sustain electrode as "X electrode". The discharge cell 12 shown in FIG. 2 corresponds to the discharge cell 12 shown in FIG.

3 is a driving waveform diagram of a plasma display panel.

According to the driving method of the PDP shown in Fig. 3, each subfield is composed of a reset section, an address section, and a sustain section.

The reset section serves to erase the wall charge state of the previous sustain discharge and to set up wall charge in order to stably perform the next address discharge.

The address period is a period in which a wall charge is accumulated in a cell (addressed cell) that is turned on by selecting a cell that is turned on and a cell that is not turned on in the panel.

The sustain period is a period in which discharge for actually displaying an image on the addressed cell is performed.

Hereinafter, the operation of the reset section of the plasma display panel driving method will be described in more detail. As shown in Fig. 3, the reset section is composed of a Y ramp up section and a Y ramp down section.

(1) Y ramp up section

During this period, the address electrode and the X electrode are kept at 0 V, and a ramp voltage rising slowly from the voltage Vs toward the voltage Vset is applied to the Y electrode. While this ramp voltage is rising, the first weak reset discharge occurs in all discharge cells from the Y electrode to the address electrode and the X electrode, respectively. As a result, negative wall charges are accumulated at the Y electrode, and positive wall charges are accumulated at the address electrode and the X electrode.

(2) Y ramp descending section

Subsequently, in the second half of the reset period, while the X electrode is held at the constant voltage Ve, a ramp voltage that gently falls from the voltage Vs toward the negative voltage Vnf is applied to the Y electrode. While this ramp voltage is falling, again a second weak reset discharge occurs in every discharge cell.

At this time, among the field effect transistors (FETs) operating in the Y electrode board, when the Y electrode descends from the Vs voltage and finally goes to the negative voltage Vnf, a device for separating the Vs voltage and the Vnf voltage is required.

4 is a diagram illustrating a conventional circuit isolation device.

As shown in Fig. 4, according to the conventional circuit, the FET M1 is connected between the first circuit portion for outputting a high voltage and the second circuit portion for outputting a low voltage.

At this time, the first circuit portion is a circuit for outputting the Vs voltage among the waveforms shown in Fig. 3, and the second circuit portion is a waveform for decreasing the voltage from Vs to the lamp and outputting a negative voltage Vnf. At this time, the maximum voltage difference applied to the FET M1 which is a switching element separating the two circuit parts is a very high voltage corresponding to the voltage difference between the Vs voltage and the Vnf voltage. Therefore, a high breakdown voltage device capable of withstanding such a high voltage should be used as the FET device.

Therefore, according to the conventional driving circuit, since a high breakdown voltage switching element is used to separate the two circuit parts, there is a problem in that the cost increases.

SUMMARY OF THE INVENTION The present invention has been made in an effort to solve the problems of the prior art, and to provide a plasma display panel and a driving apparatus thereof capable of using a switching device having low breakdown voltage characteristics.

Driving apparatus for a plasma display panel according to an aspect of the present invention for achieving the above object is

A driving device of a plasma display panel including a scan electrode, a sustain electrode, and a panel capacitor formed between the scan electrode and the sustain electrode.

A first transistor and a second transistor connected in series between a first voltage and a second voltage and electrically connected to the scan electrode, wherein the sustain electrode is configured to apply the first voltage or the second voltage to the scan electrode. A discharge voltage generator; And

A first capacitor having one end connected to a contact point of the first transistor and the second transistor, a third transistor electrically connected to the other end of the first capacitor, a contact point of the first transistor and the second transistor, and the scan electrode A fourth transistor electrically connected to the second transistor; a Zener diode connected to a source-drain of the fourth transistor; and generating a rising ramp voltage for applying a rising ramp voltage to the scan electrode, the rising ramp voltage rising from a third voltage to a fourth voltage. Contains wealth.

On the other hand, the plasma display panel according to an aspect of the present invention

A plasma panel including a plurality of address electrodes arranged in a column direction, scan electrodes and sustain electrodes arranged in a zigzag pattern in a row direction; And

And a scan driver for supplying a scan voltage and a sustain discharge voltage to the scan electrode.

In this case, the scan driver

A first circuit unit outputting a first voltage to the scan electrode;

A second circuit unit outputting a second voltage greater than the first voltage when the first circuit unit supplies a first voltage;

A transistor electrically connected between the first circuit portion and the second circuit portion to separate the first voltage and the second voltage; And

And a Zener diode connected in parallel to the source-drain of the transistor.

Hereinafter, with reference to the drawings will be described an embodiment of the present invention;

5 is a diagram illustrating a plasma display panel (PDP) according to an embodiment of the present invention.

As shown in FIG. 5, the PDP according to the embodiment of the present invention includes a plasma panel 100, an address driver 200, a Y electrode driver 300, an X electrode driver 400, and a controller 500. .

The plasma panel 100 includes a plurality of address electrodes A1 to Am arranged in a column direction, first sustain electrodes Y1 to Yn, and second sustain electrodes X1 to Xn arranged in a zigzag direction in a row direction. Include.

The address driver 200 receives an address driving control signal S _A from the controller 500 and applies a display data signal for selecting a discharge cell to be displayed to each address electrode.

The Y electrode driver 300 and the X electrode driver 400 receive the Y electrode driving signal S _Y and the X electrode driving signal S _X from the controller 500 and apply them to the X electrode and the Y electrode, respectively.

The control unit 500 receives an image signal from the outside, generates an address driving control signal S _A , a Y electrode driving signal S _Y , and an X electrode driving signal S _X , respectively, and generates the address driving unit 200 and Y, respectively. It delivers to the electrode driver 300 and the X electrode driver 400.

The Y electrode driver 300 applies the reset waveform and the sustain waveform (sustain discharge voltage waveform) shown in FIG. 3 for each subfield. Therefore, the Y electrode driver 300 needs an FET (hereinafter referred to as a 'separation FET') that separates the Vs voltage and the Vnf voltage when the Y electrode descends from the Vs voltage and finally goes to the negative voltage Vnf. .

In this case, according to the related art, the maximum voltage applied to the separation FET becomes a difference between the sustain discharge voltage Vs and the negative voltage Vnf. However, when such a voltage difference is applied to the separation FET, since only a reset operation is performed in one subfield, it is inefficient to use a high breakdown voltage FET for this purpose.

Therefore, according to the driving circuit according to the exemplary embodiment of the present invention, as shown in FIG. 5, the resistor R1 and the zener diode ZD1 are disposed across the drain-source of the FET connected between the first circuit portion and the second circuit portion. Connection to prevent the breakdown of the FET.

For example, when the output voltage of the first circuit portion at the time when the FET is turned off is 180V, and the output voltage of the second circuit portion is ramped down from -180V to -80V after the FET is turned off, the conventional driving circuit shown in FIG. According to Roh, a maximum of 260V across the FET would have to be used with a FET with a 300V breakdown voltage. However, according to the embodiment of the present invention, as shown in Fig. 6, a Zener diode having a rating of 100 V, for example, is connected to both ends of the FET M1, and a small resistor R1 is connected in series.

As such, when the Zener diode is connected, the drain voltage of the FET follows the source voltage so that the voltage across the FET M1 does not become more than a specific voltage (about 100V). Therefore, it is possible to prevent the breakdown voltage of the FET M1 through this method.

7 is a detailed circuit diagram of the Y electrode driver 300 according to the embodiment of the present invention.

The Y electrode driving unit according to the exemplary embodiment of the present invention includes a sustain discharge voltage generator 320, a Y rising ramp voltage generator 340, a Y ramp falling voltage generator 360, and a scan IC 380.

The sustain discharge voltage generator 320 includes transistors Yr, Yf, Ys, and Yg, diodes Dr, Df, Ds, and Dg, an inductor L1, and a capacitor C1. The transistors Ys and Yg are connected in series between the sustain voltage Vs and the ground voltage, and are switching elements for supplying the voltage Vs and the ground voltage to the panel capacitor Cp, respectively. The capacitor C1, the inductor L1, and the transistors Yr and Yf form an energy recovery circuit to charge the voltage of the panel capacitor Cp to the voltage Vs or to discharge the voltage to the ground voltage. Do it.

The scan IC 380 gradually includes a transistor connected to the scan electrode (one end of the panel capacitor), and serves to sequentially supply the scan voltage to the scan electrode (Y electrode) of the plasma display panel.

The Y rising ramp voltage generator 340 includes a Zener diode ZD1 connected in series between a capacitor Cset, a rising ramp transistor Yrr, a main path transistor Ypp and Ynp, and a source-drain of the main path transistor Ynp. ) And a resistor R1, and a rising ramp voltage rising from the voltage Vs to the voltage Vset is applied to the panel capacitor Cp. The capacitor Cset is connected to the contacts between the transistors Ys and Yg and the drain of the transistor Yrr, and the main path transistor Ypp is connected between the contacts between the transistors Ys and Yg and the source of the transistor Yrr. Connected. The main path transistor Ynp is electrically connected to the source of the transistor Yrr and the panel capacitor.

The Y falling ramp voltage generation unit 360 includes a transistor Yfr and a diode Dfr, and applies a falling ramp voltage falling from the voltage Vs to a negative voltage Vnf to the panel capacitor Cp.

According to the driving circuit according to the embodiment of the present invention shown in FIG. 7, a Zener diode is connected between the source and the drain of the main path transistor Ynp, and a small resistor R1 is connected in series. At this time, comparing the circuits shown in FIGS. 6 and 7, it can be seen that the first circuit portion is the sustain discharge voltage generator 320 and the second circuit portion is the ramp falling voltage generator 360.

As described above, according to the exemplary embodiment of the present invention, since the Zener diode is connected between the source-drain of the main path transistor Ynp and the small resistor R1 is connected in series, the voltage between the both ends of the transistor Ynp does not exceed a specific voltage. The drain voltage of the transistor Ynp follows the source voltage so as not to. Therefore, according to the embodiment of the present invention, since a transistor with a low breakdown voltage can be used, there is an advantage that the circuit cost can be reduced.

At this time, according to the embodiment of the present invention, in order to prevent the DC current from flowing in the normal state, the Zener diode is determined by the difference between the voltage Vnf and the ground voltage (the output value of the steady state discharge generator when the falling ramp voltage is applied). The zener diode should be rated so that no current flows through it. For example, assuming that the voltage Vnf is -80V, the rated voltage of the zener diode may be set to 80V or more (for example, 100V).

Although the embodiments of the present invention have been described in detail above, the present invention is not limited to the above-described embodiments, and various other modifications and changes are possible.

 As described above, according to the present invention, since the Zener diode is connected between the source and the drain of the separation transistor separating the two circuit parts and the resistor is connected in series, a low voltage transistor can be used to reduce the circuit cost. have.

Claims (10)

A driving device of a plasma display panel comprising a scan electrode, a sustain electrode, and a panel capacitor formed between the scan electrode and the sustain electrode. A first transistor and a second transistor connected in series between a first voltage and a second voltage and electrically connected to the scan electrode, wherein the sustain electrode is configured to apply the first voltage or the second voltage to the scan electrode. A discharge voltage generator; And A first capacitor having one end connected to a contact point of the first transistor and the second transistor, a third transistor electrically connected to the other end of the first capacitor, a contact point of the first transistor and the second transistor, and the scan electrode A fourth transistor electrically connected to the second transistor; a Zener diode connected to a source-drain of the fourth transistor; and generating a rising ramp voltage for applying a rising ramp voltage to the scan electrode, the rising ramp voltage rising from a third voltage to a fourth voltage. part Driving device of the plasma display panel comprising a. The method of claim 1, A fifth transistor electrically connected between the fourth transistor and a fifth voltage, and further comprising a falling ramp voltage generation unit configured to apply a falling ramp voltage falling to the fifth voltage to the scan electrode; Drive. The method of claim 2, And the fifth voltage is a negative voltage. The method according to any one of claims 1 to 3, And wherein the first voltage is a sustain discharge voltage, and the second voltage is a ground voltage. The method according to claim 2 or 3, And a rated voltage of the zener diode is greater than a voltage difference between the second voltage and the fifth voltage. The method according to any one of claims 1 to 3, And a resistor connected in series with the zener diode. A plasma panel including a plurality of address electrodes arranged in a column direction, scan electrodes and sustain electrodes arranged in a zigzag pattern in a row direction; And A scan driver for supplying a scan voltage and a sustain discharge voltage to the scan electrode; The scan driver A first circuit unit outputting a first voltage to the scan electrode; A second circuit unit outputting a second voltage greater than the first voltage when the first circuit unit supplies a first voltage; A transistor electrically connected between the first circuit portion and the second circuit portion to separate the first voltage and the second voltage; And a Zener diode connected in parallel to the source-drain of the transistor. The method of claim 7, wherein The first voltage circuit portion includes first and second transistors connected in series between a first voltage and a second voltage and a contact is electrically connected to the scan electrode, wherein the first voltage or the first voltage is connected to the scan electrode. It is a sustain discharge voltage generator for applying two voltages, And the second voltage circuit unit is a falling ramp voltage generation unit configured to apply a falling ramp voltage falling to the scan electrode to a third voltage to the scan electrode. The method according to claim 7 or 8, And wherein the first voltage is a sustain discharge voltage and the second voltage is a ground voltage. The method according to claim 7 or 8, And a rated voltage of the zener diode is greater than a voltage difference between the second voltage and the fifth voltage.

Images