KR100578228B1 - Method for fabrication of semiconductor device with increased overlay margin - Google Patents

Abstract

The present invention is to provide a method for manufacturing a semiconductor device that can increase the overlay margin when forming a metal contact, for this purpose, the present invention forms two metal contacts that are in contact with the lower conductive layer and electrically connected to each other In an embodiment, the regions in which the two metal contacts are formed may have a long axis and a short axis, and may be spaced apart from each other in a long axis direction, and the parts adjacent to each other in the long axis direction may be coupled to each other to be a metal contact connected to each other. Provided is a method of manufacturing a semiconductor device, comprising performing an etching process using a mask pattern having two openings formed adjacent to each other.

Metal line, dumbbell shape, peanut shape, bit line, metal contact.

Description

Semiconductor device manufacturing method to increase overlay margin {METHOD FOR FABRICATION OF SEMICONDUCTOR DEVICE WITH INCREASED OVERLAY MARGIN}             

1 is a schematic view illustrating a plane in which a mask and a contact hole for a metal line contact of a bit line are formed in a peripheral region of a semiconductor memory device;

2 is a plan view illustrating a peripheral region of a semiconductor memory device in which metal lines are formed.

3 is a cross-sectional view taken along the line AA ′ of FIG. 2;

FIG. 4 schematically illustrates a plane in which a mask and a contact hole for a metal line contact of a bit line are formed in a peripheral region of a semiconductor memory device according to an embodiment of the present invention.

5 is a view illustrating a plane in which contact holes are formed using the mask of FIG. 4.

6 is a plan view illustrating a peripheral region of a semiconductor memory device in which metal lines are formed.

7 is a plan view illustrating a peripheral region of a semiconductor memory device in which metal lines are formed in accordance with an embodiment of the present invention.

Explanation of symbols on the main parts of the drawings

G601, G602 Gate Electrode B / L: Bit Line

C / T: Metal contact planned area M: Metal line

The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method for forming a metal contact of a semiconductor device.

The semiconductor device includes a plurality of unit devices therein. As semiconductor devices are highly integrated, various elements must be formed at high density on a constant cell area. As a result, the size of unit devices such as transistors and capacitors is gradually decreasing.

In particular, in semiconductor memory devices such as DRAM (Dynamic Random Access Memory), as the design rule decreases, the size of the unit devices formed inside the cell gradually decreases, but the aspect ratio increases in order to secure the capacity of the capacitor. This is unavoidable, which causes difficulties in the process of forming deep contact holes such as metal contacts.

Meanwhile, as the degree of integration of the device increases and the design rule decreases, the distance between adjacent conductive patterns (eg, gate electrodes) decreases. In contrast, as the thickness of the conductive pattern increases, the height of the conductive pattern and the conductive patterns decrease. The aspect ratio, which represents the ratio of the distances between, gradually increases.

A representative example thereof is a metal contact forming process for forming a metal line of a bit line in a peripheral region after forming a bit line and forming a capacitor of a cell region in manufacturing a semiconductor memory device.

FIG. 1 schematically illustrates a plane in which a mask and a contact hole for a metal line contact of a bit line are formed in a peripheral region of a semiconductor memory device.

Referring to FIG. 1A, a bit line B / L is formed and has a rectangular open area on the bit line B / L to form a metal line of the bit line B / L. The mask pattern P is formed. The open areas of the rectangles of the mask pattern P are spaced apart from each other at regular intervals so as not to exceed the width of the bit line B / L.

Referring to FIG. 1B, a plurality of insulating layers (not shown) and a bit line hard mask (not shown) are formed on the bit lines B / L using the mask pattern P of FIG. 1A. By selectively etching), it can be seen that the contact hole (C / T) is formed.

Although the open area of the mask pattern P has a rectangular shape, it can be seen that the contact hole C / T is formed in a hole type during the actual process.

2 is a plan view illustrating a peripheral region of a semiconductor memory device in which metal lines are formed.

Referring to FIG. 2, line-type gate electrodes G1 and G2 are formed on a substrate (not shown) at predetermined intervals, and the gate electrodes are disposed on the gate electrodes G1 and G2. Bit lines B / L vertically intersecting with G1 and G2 are formed, and metal contacts C / T for connection between the bit lines and the metal lines are formed at regular intervals, and the metal contacts C are formed. The metal line M is formed on / T).

3 is a cross-sectional view taken along the line AA ′ of FIG. 2.

Referring to FIG. 3, a field oxide film 11 is formed locally on a substrate 10, and a gate conductive film 12 and a gate hard mask 13 are stacked on the substrate 10, and spacers are formed on sidewalls thereof. Gate electrodes G1 and G2 having 14 are formed at predetermined intervals. Upper ends of the gate electrodes G1 and G2 are planarized with the first interlayer insulating film 15, and a second interlayer insulating film 16 is formed on the flattened upper portion. On the second interlayer insulating film 16, a bit line B / L made of a metal film 17 made of tungsten or the like and a hard mask 18 is formed. The third interlayer insulating film 19 and the fourth interlayer insulating film 20 are formed on the bit lines B / L. The fourth interlayer insulating film 20 corresponds to the vertical height of the capacitor in the cell region. The open portion formed by etching the fourth interlayer insulating film 20, the third interlayer insulating film 19, and the hard mask 18 is embedded, and the metal contacts 21 and C / T contacted to the metal film 17 are formed. On the metal contact 21, metal lines 22 and M are formed.

As shown in FIGS. 2 and 3, two adjacent metal contacts C / T use a hole type mask pattern. However, as the process becomes more sophisticated, it is difficult to secure margins between the two contacts.

In addition, the contact size between the metal contact (C / T) and the bit line (B / L) can no longer be reduced, the lack of overlay margin during the process and the metal contact (C / T) is the bit line (B / L) There is a possibility that the lower gate electrodes G and G2 are contacted without being exactly aligned with each other.

This means an electrical short between the metal line M and the gate electrodes G1 and G2, which leads to malfunction of the semiconductor device.

This lack of overlay margin occurs mainly in the 'K' portion shown in FIG.

The present invention has been proposed to solve the above problems of the prior art, and an object of the present invention is to provide a method for manufacturing a semiconductor device that can increase the overlay margin when forming a metal contact.

In order to achieve the above object, in the present invention, in forming two metal contacts that are in contact with the lower conductive layer and electrically connected to each other, the regions in which the two metal contacts are formed have long and short axes, respectively, and have long axes. Etch process using a mask pattern having two openings which are spaced apart from each other in the longitudinal direction and adjacent to each other in the major axis direction to be coupled to each other to form a metal contact connected to each other. A semiconductor device manufacturing method is provided.

In addition, to achieve the above object, the present invention, forming a plurality of gate electrodes having a predetermined interval on the substrate, and forming a bit line crossing the gate electrode in the vertical direction on the gate electrode And forming two metal contacts in contact with the bit line and electrically connected to each other, wherein regions in which the two metal contacts are formed are spaced apart from each other in a long axis direction having a major axis and a minor axis, To provide a method for manufacturing a semiconductor device characterized in that the etching process using a mask pattern having two openings formed adjacent to each other with the long axis and short axis so that the adjacent parts are bonded to each other to be connected to each other in the direction do.

In the present invention, when forming two contact holes electrically connected to each other and formed in a hole shape, the mask pattern is formed such that the two contact hole predetermined regions are adjacent to each other in a dumbbell shape. The two contact holes etched through the etching process using the same are connected to each other to have a dual dumbbell shape. As such, two metal contacts can be made into one metal contact, thus maximizing margin gain and increasing overlay margin due to the reduction of the width of the metal contact. This may eventually increase cell efficiency.

DETAILED DESCRIPTION Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art can more easily implement the present invention.

FIG. 4 is a view schematically illustrating a plane in which a mask and a contact hole for a metal line contact of a bit line are formed in a peripheral region of a semiconductor memory device according to an embodiment of the present invention, and FIG. 5 uses the mask of FIG. 4. To show a plane in which contact holes are formed.

Referring to FIG. 4, a mask pattern having a bit line B / L and having a dumbbell-shaped open area for forming a metal line of the bit line B / L on the bit line B / L P) is formed. The open area of the dumbbell shape which the mask pattern P has is spaced adjacent adjacent to the long axis direction, and does not exceed the width of the bit line B / L in the short axis direction.

In the conventional case as shown in FIG. 1, the size of the square was a square of 'x = 0.24' and 'y = 0.24', but in the present invention of FIG. 4, 'a = 0.16', 'b = 0.37', and 'c = 0.10' , 'd = 0.11', 'e = 0.10', and 'f = 0.84'.

Here, the unit is 'μm'.

Therefore, the length of the short axis can be reduced from 'x = 0.24' to 'a = 0.16' and 'c = 0.10'. In addition, the separation distance between two adjacent open regions approaches 'e = 0.10', thereby allowing the two open regions to be coupled to each other in an etching process for subsequent contact formation.

Referring to FIG. 5, after the proximity result of etching between two adjacent contact regions of FIG. 4, the two open regions are coupled to form a dumbbell-shaped contact hole H. Referring to FIG.

6 is a plan view illustrating a peripheral region of a semiconductor memory device in which metal lines are formed.

Referring to FIGS. 6A and 6B, line-shaped gate electrodes G601 and G602 spaced at predetermined intervals are formed on a substrate (not shown), and gate electrodes G601 and A bit line (B / L) intersecting the gate electrodes (G601, G602) perpendicular to the gate electrode (G601, G602) is formed on the upper part, and two metal contacts in the shape of dumbbells for connecting the bit line (B / L) and the metal line are scheduled. The mask pattern of the form where the area | region C / T is adjacent is formed.

Here, reference numeral 'M' indicates a metal line M to be formed on the metal contact plan region C / T.

In the case of having a square contact area C / T having a side length of "0.24 mu m" as in the related art, there is a margin of "0.08 mu m" on both sides of the bit line B / L in the short axis direction.

On the other hand, if it has the same shape as the present invention, as shown in Fig. 6 (a) there is a margin of about "0.11㎛" on both sides of the short axis of the bit line (B / L). In other words, it can be seen that the margin of "0.03㎛" increases.

As shown in FIG. 6B, even when the width of the bit line B / L is decreased by 0.02 μm in the peripheral area, about “0.10 μm” in both directions of the short axis of the bit line B / L is reduced. Since the margin of, the width of the bit line (B / L) can be reduced. This indicates that the width of the metal line in the peripheral area can be reduced, thereby increasing the cell efficiency.

FIG. 7 is a plan view illustrating a peripheral area of a semiconductor memory device having a metal line according to an embodiment of the present invention.

Referring to FIG. 7, line-shaped gate electrodes G601 and G6022 spaced at predetermined intervals are formed on a substrate (not shown), and gate electrodes G601 and G602 are disposed on gate electrodes G601 and G602. A bit line B / L intersecting with the vertical line is formed, a metal contact H for connecting the bit line and the metal line is formed, and a metal line M is formed on the metal contact H. have.

Meanwhile, as shown in FIG. 5, the two adjacent contact planar regions are coupled to each other, such that the metal contact C / T has one dumbbell shape or a peanut shape.

Therefore, it is possible to obtain substantially the same contact resistance while increasing the cell efficiency as compared with the prior art.

According to the present invention made as described above, when forming two contact holes electrically connected to each other and formed in a hole shape, a mask pattern is formed such that two contact hole predetermined regions are adjacent to each other in a dumbbell shape, and etching is performed using the same. The two contact holes etched through the process are connected to each other to have a double dumbbell shape, so that the two metal contacts can be made into one metal contact, thereby maximizing the margin securing and the overlay margin due to the reduction of the width of the metal contact. It can be seen through the embodiment that can be increased, the cell efficiency can be increased.

Although the technical idea of the present invention has been described in detail according to the above preferred embodiment, it should be noted that the above-described embodiment is for the purpose of description and not of limitation. In addition, those skilled in the art will understand that various embodiments are possible within the scope of the technical idea of the present invention.

For example, in the above-described embodiment of the present invention, the bit line metal wiring process is taken as an example. However, the present invention may be applied to any process for forming contact holes, such as forming a contact hole with a gate electrode pattern, a contact pad, or a metal wiring.

As described above, the present invention can increase the overlay margin during contact formation, thereby reducing the occurrence of defects during semiconductor device manufacturing, thereby improving the yield.

Claims (7)

In forming two metal contacts which are in contact with the lower conductive layer and are electrically connected to each other, The areas in which the two metal contacts are formed have a long axis and a short axis, respectively, and are spaced apart from each other in the long axis direction, and adjacent portions of the metal contact are adjacent to each other with the long axis and the short axis so that adjacent portions are joined to each other to be connected to each other. A method of manufacturing a semiconductor device, comprising performing an etching process using a mask pattern having two openings formed therein. The method of claim 1, The region in which the metal contact is formed is a semiconductor device manufacturing method characterized in that the dumbbell shape. The method according to claim 1 or 2, The two metal contacts are one dumbbell-shaped or peanut-shaped manufacturing method, characterized in that. The method according to claim 1 or 2, The conductive layer is a semiconductor device manufacturing method, characterized in that the bit line. Forming a plurality of gate electrodes having a predetermined interval on the substrate; Forming a bit line intersecting the gate electrode in a vertical direction on the gate electrode; Forming two metal contacts in contact with the bit line and electrically connected to each other; The regions where the two metal contacts are formed have a long axis and a short axis and are spaced apart from each other in the long axis direction, and adjacent portions of the two metal contacts are adjacent to each other so as to be metal contacts connected to each other by being coupled to each other in the long axis direction. A method of manufacturing a semiconductor device, comprising performing an etching process using a mask pattern having two openings. The method of claim 5, wherein The region in which the metal contact is formed is a semiconductor device manufacturing method characterized in that the dumbbell shape. The method according to claim 5 or 6, The two metal contacts are one dumbbell shape or peanut shape, characterized in that the manufacturing method.

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