KR100578125B1 - Method Of Patterning Interlayer Dielectric And Semiconductor Device Fabricated By Using The Method - Google Patents

Abstract

A method of patterning an interlayer insulating film and a semiconductor device formed thereby are provided. The method includes forming an interlayer insulating film on a semiconductor substrate and then forming a photoresist pattern having at least one bent portion on the resultant. Thereafter, the interlayer insulating layer is etched using the photoresist pattern as an etching mask. In this case, the photoresist patterns may be connected to each other to form a net shape or may be disposed in an L shape on one side of each of the active regions.

Description

A method of patterning an interlayer insulating film and a semiconductor device formed thereon {Method Of Patterning Interlayer Dielectric And Semiconductor Device Fabricated By Using The Method}

1 is a plan view illustrating a manufacturing process of a semiconductor device according to an embodiment of the present invention.

2 is a plan view illustrating a process of manufacturing a semiconductor device according to another embodiment of the present invention.

3 is a perspective view illustrating a semiconductor device having an interlayer insulating film pattern formed according to a preferred embodiment of the present invention.

4 to 7 are process cross-sectional views illustrating a method of patterning an interlayer insulating film according to a preferred embodiment of the present invention.

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a method for manufacturing the same, and more particularly, to a method for patterning an interlayer insulating film of a semiconductor device and a semiconductor device formed thereby.

The semiconductor device includes various kinds of materials, which may be classified into a conductive material, a semiconductor, and an insulating material according to the size of the resistivity. The semiconductor is a material whose resistance is changed by an applied potential, and a material corresponding thereto is a semiconductor substrate. The conductive material is mainly used as a wiring, and is formed of a metallic material such as tungsten, aluminum copper or the like or conductive polycrystalline silicon. The insulating material includes a silicon oxide film, a silicon nitride film, a silicon oxynitride film, and the like, and serves to electrically insulate or structurally support the conductive material or the semiconductor.

A conventional process of manufacturing a semiconductor device having a MOS transistor includes forming an isolation layer in a predetermined region of a semiconductor substrate. The device isolation layer serves to define an active region. After forming a gate pattern crossing the active region and the device isolation layer on the semiconductor substrate including the device isolation layer, impurity regions are formed in the active region between the gate patterns. The impurity regions are disposed on both sides of the gate pattern to be used as a source / drain of the MOS transistor. An interlayer insulating film is formed on the entire surface of the semiconductor substrate including the impurity regions to fill regions between the gate patterns.

Thereafter, the interlayer insulating layer is patterned to form openings that expose the impurity regions or the gate patterns. According to the general prior art, the opening is formed in a circular or elliptical shape when viewed in plan. However, the patterning patterning process for forming the opening includes an anisotropic etching process using a photoresist pattern on the interlayer insulating layer and using the photoresist pattern as an etching mask. At this time, the photoresist pattern also has an open area of the same circular or elliptical shape to define the opening. However, as semiconductor devices become highly integrated, the photolithographic process of forming the circular or elliptical open areas becomes increasingly difficult.

In order to overcome this general limitation of the prior art, Korean Patent No. 0281182 proposes a method of forming the photoresist pattern in the form of a bar. The method includes forming a photoresist pattern on the interlayer insulating film, crossing the gate pattern with a rod shape and exposing an upper portion of the active region. However, when the photoresist pattern is formed in the form of a rod, there is a problem that the photoresist pattern collapses due to the surface tension with the developer in the developing step.

In addition, when the shape of the unit cell is modified to improve the characteristics of the transistor, the rod-shaped photoresist pattern may not maximize the improved characteristics. That is, rod-shaped photoresist patterns are vulnerable in terms of adaptability to design changes.

SUMMARY OF THE INVENTION The present invention has been made in an effort to provide a method of manufacturing a semiconductor device capable of preventing the problem of a photoresist pattern falling down.

Another object of the present invention is to provide a method of patterning an interlayer insulating film to be suitable for planar structural changes.

Another object of the present invention is to provide a semiconductor device having an interlayer insulating film pattern that can be effectively adapted to design changes.

In order to achieve the above technical problem, the present invention provides a method of manufacturing a semiconductor device to form a photoresist pattern to have a bent portion in at least one place. The method includes forming an interlayer insulating film on a semiconductor substrate and then forming a photoresist pattern having at least one bent portion on the resultant. Thereafter, the interlayer insulating layer is etched using the photoresist pattern as an etching mask.

Preferably, before forming the interlayer insulating film, forming a device isolation film defining a plurality of active regions on the semiconductor substrate, and forming a plurality of gate patterns across the device isolation film and the active region. . In this case, the gate pattern is formed of a gate conductive pattern and a capping pattern that are sequentially stacked. The gate conductive pattern is formed of at least one material selected from polycrystalline silicon, silicide, and metal, and the capping pattern is formed of an insulating layer having an etch selectivity with respect to the interlayer insulating layer. Preferably, the capping pattern is formed of a silicon nitride film.

In addition, before forming the photoresist pattern, the step of planarizing etching the interlayer insulating film may be further performed until the upper surface of the capping pattern is exposed. In this case, the step of planarization etching the interlayer insulating film is preferably performed using a chemical mechanical polishing technique.

According to a preferred embodiment of the present invention, the photoresist patterns are connected to each other to form a mesh shape. According to another embodiment, the photoresist pattern may be disposed on one side of each of the active regions, forming an L-shape.

In order to achieve the above technical problem, the present invention provides a semiconductor device having an interlayer insulating film pattern of sidewalls inclined with respect to the gate pattern. The device includes a device isolation layer disposed in a predetermined region of a semiconductor substrate and defining a plurality of active regions, a plurality of gate patterns crossing the device isolation layer and the active regions, and exposing an upper surface of the active regions, between the gate patterns. Interlayer insulating films disposed on the substrate. In this case, some of the interlayer insulating layers may have oblique side surfaces on the gate patterns.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. However, the present invention is not limited to the embodiments described herein but may be embodied in other forms. Rather, the embodiments introduced herein are provided to ensure that the disclosed subject matter is thorough and complete, and that the spirit of the present invention to those skilled in the art will fully convey. In the drawings, the thicknesses of layers and regions are exaggerated for clarity. If it is also mentioned that the layer is on another layer or substrate it may be formed directly on the other layer or substrate or a third layer may be interposed therebetween.

1 and 2 are plan views illustrating a manufacturing process of a semiconductor device according to exemplary embodiments of the present invention, and FIGS. 4 to 7 illustrate a manufacturing process of a semiconductor device according to an exemplary embodiment of the present invention. Process cross-sectional views are provided.

1 and 4, the device isolation layer 110 defining the active region 110a is formed in a predetermined region of the semiconductor substrate 100. According to an embodiment of the present invention, the device isolation layer 110 is formed so that the active region 110a may have a cross-symmetrical cross shape. That is, according to this embodiment, the active region 110a is arranged in a cross-shaped island shape, and the device isolation layer 110 extends in a mesh shape surrounding the active regions 110a. A gate insulating layer 115 is formed on the active region 110a. The gate insulating film 115 is preferably a silicon oxide film formed using a thermal oxidation process.

A gate conductive layer and a capping layer are sequentially formed on the entire surface of the semiconductor substrate including the gate insulating layer 115, and then patterned to form a gate pattern 120 crossing the active region 110a and the device isolation layer 110. Form. The gate pattern 120 includes a gate conductive pattern 122 and a capping pattern 124 that are sequentially stacked. The gate conductive pattern 122 may be formed of a conductive material including polycrystalline silicon. At least one of tungsten, cobalt, and silicides thereof may be used. The capping pattern 124 may be one material selected from a silicon nitride film, a silicon oxynitride film, and a silicon oxide film.

After the gate patterns 120 are formed, an ion implantation process using the gate patterns 120 as an ion implantation mask is performed. Accordingly, impurity regions 130 used as the source / drain of the transistor are formed in the active region between the gate patterns 120.

Referring to FIG. 5, gate spacers 140 are formed on both side surfaces of the gate pattern 120. The gate spacer 140 may be made of the same material as the capping pattern 124 and is preferably formed of a silicon nitride layer. The forming of the gate spacer 140 may include forming a spacer insulating film conformally on the entire surface of the semiconductor substrate including the gate pattern 120, and then anisotropically etching the same. The etching of the spacer insulating layer may be performed so that etching damage does not occur on the semiconductor substrate 100. To this end, the etching of the spacer insulating film preferably uses an etching recipe having an etching selectivity with respect to the semiconductor substrate 100 or the gate insulating film 115.

Thereafter, an interlayer insulating film 150 is formed on the entire surface of the semiconductor substrate including the gate spacer 140. The interlayer insulating layer 150 is formed of an insulating layer having an etch selectivity with respect to the capping pattern 124 and the gate spacer 140. Accordingly, the interlayer insulating film 150 may be formed of one of insulating material films including a silicon oxide film.

Referring to FIG. 6, the interlayer insulating layer 150 is planarized and etched until the upper surface of the capping pattern 124 is exposed to fill the gap regions between the gate patterns 120. ). The planarization etching process is preferably carried out using a chemical mechanical polishing (CMP) process.

The photoresist pattern 160 is formed on the semiconductor substrate including the interlayer insulating layer pattern 155. According to an embodiment of the present invention, as shown in FIG. 1, the photoresist pattern 160 has a net shape disposed surrounding the active region 110a. In this case, the photoresist pattern 160 has a portion bent at at least one place. That is, the photoresist pattern 160 has at least one sidewall inclined with respect to the gate pattern 120. This bent portion allows the photoresist pattern 160 to be supported from the force applied in the developing step or the like. Accordingly, the problem of the photoresist pattern 160 falling down in the developing step may be minimized. In addition, the photoresist pattern 160 may be easily modified and applied through a method of adjusting the angle of bending of the bent portion, even when the cell layout is changed to improve the characteristics of the transistor.

According to another exemplary embodiment of the present invention, as shown in FIG. 2, the photoresist pattern 160 may have an L-shape having one bent portion. This embodiment can also obtain the same effect as that shown in FIG.

Referring to FIG. 7, the interlayer insulating layer pattern 155 is etched using the photoresist pattern 160 as an etching mask. The etching process uses an etching recipe capable of etching the interlayer insulating layer pattern 155 with etching selectivity with respect to the capping pattern 124 and the gate spacer 140. Accordingly, the interlayer insulating film pattern 155 disposed between the photoresist patterns 160 is etched to expose the lower impurity region 130. Since the interlayer insulating film pattern 155 and the gate insulating film 115 are mostly made of a silicon oxide film, the gate insulating film 115 is also etched during the etching process. In addition, the above-described etching selectivity implies the characteristics of etching at different etching rates, and the capping pattern 124 and the gate spacer 140 are etched together during the process of etching the interlayer insulating layer pattern 155. As shown in FIG. 7, exposed corner portions may be recessed.

Meanwhile, according to another exemplary embodiment of the present invention, the photoresist pattern 160 is formed on the interlayer insulating layer 150, and then the interlayer insulating layer 150 is patterned using the photoresist pattern 160 as an etching mask, thereby forming the impurity region. An interlayer insulating film pattern 155 may be formed to expose 130. According to this embodiment, the photoresist pattern 160 is formed without performing the step of planarizing etching the interlayer insulating film 150, which is different from the above-described embodiment. The omitted planarization etching process may be performed as a part of a so-called node separation process after performing a subsequent process of forming a plug conductive layer.

3 is a perspective view showing an interlayer insulating film pattern formed according to a preferred embodiment of the present invention.

1 and 3, an isolation layer 110 defining an active region 110a is disposed in a predetermined region of the semiconductor substrate 100. When the active region 110a has a cross shape, the active regions 110a are spaced apart from each other and arranged in an island shape. The device isolation layer 110 is disposed to surround the active regions 110a having the island shape.

Gate patterns 120 may be disposed on the semiconductor substrate including the active region 110a and the device isolation layer 110. The gate pattern 120 includes a gate conductive pattern 122 and a capping pattern 124 that are sequentially stacked. The gate conductive pattern 122 may be formed of at least one material selected from polycrystalline silicon, tungsten silicide, cobalt silicide, tungsten, cobalt, copper, and tungsten nitride. In addition, the capping pattern 124 is preferably formed of a silicon nitride film, a silicon oxynitride film or a silicon oxide film may be used. Gate spacers 140 are disposed on both sidewalls of the gate pattern 120. The gate spacer 140 may be formed of the same material as the capping pattern 124. That is, the gate spacer 140 is preferably formed of a silicon nitride film, and a silicon oxynitride film or a silicon oxide film may be used.

A gate insulating layer 115 is disposed between the gate pattern 120 and the active region 110a. The gate insulating film 115 is preferably a silicon oxide film formed through a thermal oxidation process. Impurity regions 130 used as the source / drain of the transistor are disposed in the active region 110a between the gate patterns 120. The impurity region 130 includes impurities of a conductive type different from that of the semiconductor substrate 100.

An interlayer insulating layer pattern 155 exposing the impurity region 130 is disposed between the gate patterns 120. The interlayer insulating layer pattern 155 is formed of a material layer having an etch selectivity with respect to the capping pattern 124 and the gate spacer 140. According to a preferred embodiment of the present invention, the interlayer insulating film pattern 155 is formed of an insulating material including a silicon oxide film. Some of the interlayer insulating layer patterns 155 may have sidewalls that are inclined with respect to the gate pattern 120. An angle between sidewalls of the interlayer insulating layer pattern 155 and the gate pattern 120 may not be perpendicular. Accordingly, the impurity region 130 is formed in a region between the gate patterns 120 among the active regions 110a, and the impurity region 130 is a gap region between the gate patterns 120. Is exposed by the interlayer insulating film patterns 155 having inclined sidewalls.

According to the present invention, after forming a photoresist pattern having obliquely intersecting the gate pattern and having at least one bent portion, the interlayer insulating film is patterned using this as an etching mask. Accordingly, the problem of collapse of the photoresist pattern is minimized. As a result, the process of manufacturing a semiconductor device can be easily progressed.

In addition, by patterning the interlayer insulating film using a photoresist pattern having a bent portion, this method can be easily modified and applied even when changing the cell layout. As a result, design changes and the like for improving the characteristics of the transistors are free, and excellent products can be easily developed.

Claims (10)

Forming a device isolation layer on the semiconductor substrate to define a plurality of active regions; Forming a plurality of gate patterns crossing the device isolation layer and the active region; Forming an interlayer insulating film on a resultant product on which the gate pattern is formed; Forming a photoresist pattern on the semiconductor substrate including the interlayer insulating layer, the photoresist pattern having an opening exposing the top surface of the interlayer insulating layer on the active region; And Forming a contact hole exposing the active regions on both sides of the gate pattern by etching the interlayer insulating layer using the photoresist pattern as an etching mask, And the opening portion of the photoresist pattern has at least one portion that is bent at a predetermined angle with respect to the gate pattern to prevent the photoresist pattern from falling down. The method of claim 1, And the gate pattern is formed by sequentially stacking a gate conductive pattern and a capping pattern. The method of claim 2, The gate conductive pattern is formed of at least one material selected from polycrystalline silicon, silicide and metal. The method of claim 2, And the capping pattern is formed of an insulating film having an etch selectivity with respect to the interlayer insulating film. The method of claim 2, And the capping pattern is formed of a silicon nitride film. The method of claim 2, Prior to forming the photoresist pattern, further comprising planarizing etching the interlayer insulating layer until the upper surface of the capping pattern is exposed. The method of claim 6, And planarization etching the interlayer insulating film is performed by using a chemical mechanical polishing technique. The method of claim 1, The photoresist pattern is connected to each other, to form a mesh shape interlayer insulating film patterning method of a semiconductor device. The method of claim 1, And the photoresist pattern is disposed on one side of each of the active regions so as to form an L-shape. An isolation layer disposed in a predetermined region of the semiconductor substrate and defining a plurality of active regions; A plurality of gate patterns crossing the device isolation layer and the active regions; And Interlayer insulating layers disposed between the gate patterns while exposing upper surfaces of the active regions, And some of the interlayer insulating films have at least one bent portion.

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