KR100576820B1 - semiconductor memory device - Google Patents

Abstract

The present invention discloses a semiconductor memory device. The apparatus is connected between each of the predetermined number of first partial local data input / output line pairs and the second partial local data input / output line pairs in response to the first control signal, thereby providing the predetermined number of first and second partial local data input / output lines. Control the connection between the pairs, and in response to the second control signal, a predetermined number of first number of first partial local data input / output line pairs connected to the first partial block and a predetermined number of first redundancy partial blocks Controlling the connection between the second portions of the first partial local data input / output line pairs, and the first and the first portions of the predetermined number of second partial local data input / output line pairs connected to the second partial block in response to the third control signal. And switching means for controlling the connection between the second portions of the predetermined number of second portion local data input / output line pairs connected to the two redundancy partial blocks. Therefore, when the number of the column select signal lines where the failure of the corresponding partial block is greater than the number of the column select signal lines that can be replaced by the corresponding redundancy partial block is replaced with the column select signal lines of the adjacent adjacent redundancy partial blocks. This increases the redundancy efficiency.

Description

Semiconductor memory device

1 is a block diagram showing the configuration of a semiconductor memory device having a conventional stack bank structure.

FIG. 2 shows a configuration of an embodiment of the semiconductor memory device shown in FIG.

3 is a block diagram showing the configuration of a semiconductor memory device having a stack bank structure of the present invention.

FIG. 4 shows a configuration of an embodiment of the semiconductor memory device shown in FIG.

FIG. 5 is a circuit diagram of an embodiment of a control signal generation circuit for generating the control signals shown in FIG.

The present invention relates to a semiconductor memory device, and more particularly, to a semiconductor memory device capable of increasing redundancy efficiency by using redundancy circuits of adjacent partial blocks separated from each other in a semiconductor memory device having a stack bank structure.

In a semiconductor memory device having a stack bank structure, word lines and local data input / output line pairs are disposed in the same direction, and local data input / output line pairs and global data input / output line pairs are disposed vertically.

In a memory cell array of a semiconductor memory device having a stack bank structure, a plurality of memory cell array banks are arranged in a word line direction, and a plurality of memory cell array blocks of each of the plurality of memory cell array banks are also arranged in a word line direction. Each of the plurality of memory cell array blocks is divided into a predetermined number of partial blocks, each of the separated predetermined number of partial blocks is connected to separate local data input / output line pairs, and each of the separated local data input / output line pairs Is connected to a plurality of global data input / output line pairs of a predetermined number of groups, respectively.

That is, in the semiconductor memory device of the conventional stack bank structure, each of the memory cell array blocks is separated into a predetermined number of partial blocks, and the local data input / output line pairs of the respective partial blocks are separated. Further, precharge circuits for precharging each of the local data input / output line pairs are separately configured in each of a predetermined number of local data input / output line pairs.

The redundancy partial blocks of the semiconductor memory device having the stack bank structure are configured in each of a predetermined number of local data input / output line pairs. Thus, when a failure occurs in the memory cell of the corresponding partial block, the column select signal line connected to the defective memory cell is replaced with a redundancy column select signal line connected to the memory cell of the redundancy block.

However, when the number of the column select signal lines connected to the memory cell in which the failure occurs is greater than the number of the redundancy column select signal lines connected to the redundant memory cells, redundancy becomes impossible. Therefore, such a semiconductor memory device cannot be saved.

Disclosure of Invention An object of the present invention is to provide a semiconductor memory device capable of replacing a memory cell of a partial block in which a failure occurs when performing a redundancy operation with a corresponding redundancy partial block, as well as a redundancy partial block of adjacent adjacent blocks. have.

The semiconductor memory device of the present invention for achieving the above object is the first partial block and the first partial block is connected to a predetermined number of first partial local data I / O line pairs respectively connected to the first plurality of global data I / O line pairs and the A plurality of first partial local data I / Os each connected to a plurality of first memory cell array blocks on the left each having a first redundancy partial block of each first partial block, and a plurality of second global data input / output line pairs. A plurality of second memory cell array blocks on the right each having a second partial block connected to line pairs and a second redundancy partial block of each of the second partial blocks, and the predetermined number of first and second partial local blocks Precharge circuits for precharging each of the data input / output line pairs, the predetermined number of first partial local data inputs in response to a first control signal A plurality of first switching means connected between each of the output line pairs and the second partial local data input / output line pairs to control a connection between the predetermined number of first and second partial local data input / output line pairs; A first portion of the predetermined number of first partial local data input / output line pairs connected to the first partial block and the predetermined number of first partial local data connected to the first redundancy partial block in response to a second control signal. Second switching means for controlling a connection between the second portions of the input / output line pairs, a first number of the predetermined number of second partial local data input / output line pairs connected to the second partial block in response to a third control signal A third switching number for controlling a connection between a portion and a second portion of the predetermined number of second portion local data input / output line pairs connected to the second redundancy portion block And a control signal generating means for generating the first, second and third control signals.

Hereinafter, a conventional semiconductor memory device will be described with reference to the accompanying drawings before describing the semiconductor memory device of the present invention.

1 is a block diagram illustrating a structure of a semiconductor memory device having a conventional stack bank structure, and includes a row decoder 10, column decoders 12, and memory cell array blocks BLA, BLB, BLC, and BLD. It is.

Each of the memory cell array blocks BLA, BLB, BLC, and BLD consists of partial blocks MCi1, MCi2, MCi3, MCi4, i = 1, 2, 3, and 4 (i is the number of memory cell array blocks). And the redundancy partial blocks LRMCi, i = 1, 2, 3, and 4 for the left partial blocks MCi1, MCi2, i = 1, 2, 3, and 4 and the partial blocks located on the right ( Redundancy partial blocks (RRMCi, i = 1, 2, 3, 4) for redundancy partial blocks (RRMCi, i = 1, 2, 3, 4) for MCi3, MCi4, i = 1, 2, 3, 4 4) is centered. Then, the partial local data input / output line pairs ((P1L11, P1L11B), (P1L12, P1L12B), (P1L23, P1L2B) located between the partial blocks MCi1, MCi2, i = 1, 2, 3, and 4 located on the left side. ), (P1L34, P1L34B), (P1L44, P1L44B) and the partial local data I / O line pairs ((P2L11,) located between the partial blocks (MCi3, MCi4, i = 1, 2, 3, 4) located on the right side. P2L11B), (P2L12, P2L12B), (P2L23, P2L2B), (P2L34, P2L34B), (P2L44, P2L44B)). Precharge circuits (PRE) 20-1, 20-2, 20-3, 20-4, and 20-5 are respectively connected to the partial local data input / output line pairs located on the left side and the partial local data located on the right side. Precharge circuits (PRE) 20-6, 20-7, 20-8, 20-9, and 20-10 connected to input / output line pairs, respectively.

The row decoder 10 inputs a row address to generate selection signals for selecting m word lines WL1,..., WLm, and each of the column decoders 12, 13 inputs a column address, respectively. As a result, selection signals for selecting n column selection signal lines CSL1 to CSLn are generated.

The global data input / output line pairs (GL1, GL1B) and (GL2, GL2B) are respectively connected to partial local data input / output line pairs located on the left side, and the global data input / output line pairs (GL3, GL3B), (GL4, GL4B)) are respectively connected to the partial local data input / output line pairs located on the right side.

Thus, when one memory cell array block is selected, data applied through a global data input / output line pair is stored in selected memory cells of partial blocks located at left and right sides of the corresponding memory cell array block, or data read from the selected memory cell is global data. Output is via an input / output line pair.

However, the semiconductor memory device of the conventional stack bank structure, as shown in FIG. 1, not only are the left and right partial blocks and the partial local data input / output line pairs separated from each other, but also the redundancy partial blocks are separated, thereby performing a redundancy operation. If a failure occurs in the memory cell connected to the column select signal line on the left side, it is replaced by a memory cell connected to the redundant column select signal line on the left side, and a redundant column on the right side when the memory cell connects to the column select signal line on the right side It is replaced by a memory cell connected to the select signal line.

However, since the number of memory cells of the partial block that can be replaced by the redundancy partial block is limited, it can be replaced when a failure occurs in more memory cells than the number of memory cells that can be replaced by the redundancy partial block. There is a problem that there is no.

For example, assuming that the number of column select signal lines that can be replaced by the redundancy partial block is one, a failure occurs in a memory cell connected to one column select signal line of a memory cell array on the left and Repair is possible only when a failure occurs in a memory cell connected to one column select signal line of a memory cell array. That is, when a failure occurs in a memory cell connected to two column select signal lines of a left or right memory cell array, repair is impossible.

FIG. 2 shows the configuration of the embodiment of the semiconductor memory device shown in FIG. 1, and includes the partial block MC12, the left partial red block LRMC1, the right partial red block RRMC1, and the partial block MC13. It represents.

The redundancy operation of the conventional semiconductor memory device will be described with reference to FIG. 2 as follows.

If the memory cell is connected to the column select signal line CSL (n + 1/2) of the partial block MC12 on the left side, and the column select signal line CSL (n / 2) of the partial block MC13 on the right side, When a failure occurs in a memory cell connected to the memory cell connected to the memory cell, the column select signal line CSL (n + 1/2) is replaced with the column select signal line LCSL, and the column select signal line CSL (n / 2) is replaced with the column select signal line CSL (n / 2). It is replaced by the column select signal line RCSL.

However, if a failure occurs in the column select signal line CSL (n + 1/2) and the not shown column select signal line CSLn of the partial block MC12 located on the left side, or the partial block located on the right side ( If a failure occurs in the column select signal line CSL (n / 2) and the not shown column select signal line CSL1 of the MC12, it cannot be repaired.

That is, since the number of column select signal lines that can be replaced by the redundancy partial block is limited to one, it cannot be repaired when two or more column select signal lines need to be replaced by the redundant column select signal lines.

FIG. 3 is a block diagram showing the structure of the semiconductor memory device of the present invention, and is provided with a switch composed of NMOS transistors in the block diagram of the semiconductor memory device shown in FIG.

That is, the precharge circuits 20-1, 20-2, 20-3, 20-4, and 20-5 located on the left side and the precharge circuits 20-6, 20-7, and 20-8 located on the right side And a switch composed of NMOS transistors controlled by the control signal C1 between each of the two, 20-9, and 20-10, and the partial blocks MC12, MC22, MC32, and MC42 and the redundancy partial blocks LRMC1. And LRMC2, LRMC3, and LRMC4 each having a switch composed of an NMOS transistor controlled by a control signal C2 between pairs of local data input / output lines, and the redundancy partial blocks RRMC1, RRMC2, RRMC3, and RRMC4. Each of the blocks MC13, MC23, MC33, and MC43 has a switch composed of an NMOS transistor controlled by a control signal C3 between pairs of local data input / output lines.

That is, when performing the precharge operation, the control signals C1, C2, and C3 are all set to the "high" level, and the NMOS transistors are turned on to precharge the local data input / output line pairs.

When the read or write operation is performed, the column select signal line connected to the left partial block is replaced with the column select signal line connected to the right partial blocks by changing the state of the control signals C1, C2, and C3. Alternatively, it is possible to replace the column select signal line connected to the right partial block with the column select signal line connected to the left partial block.

Therefore, it is possible to use the redundancy partial block on the left side as a circuit for replacing the memory cells of the right side block, or use the redundancy partial block on the right side as a circuit for replacing the memory cells of the left side block.

FIG. 4 is a block diagram of an embodiment for explaining the redundancy method of the semiconductor memory device shown in FIG.

The redundancy method of the semiconductor memory device of the present invention will be described with reference to FIG. 4 as follows.

If the redundancy partial block LRMC1 located on the left side is to be replaced with the partial block on the right side, the control signals C1, C2, and C3 are all set to the "high" level during the precharge operation, and the read or write operation is performed. When performing, the control signal C1 is set to the "low" level and the control signals C2 and C3 are set to the "high" level.

On the contrary, if the redundancy partial block RRMC1 located on the right side is to be replaced with the partial block on the left side, the control signals C1, C2, and C3 are all set to the "high" level during the precharge operation, and the read or write operation is performed. When performing, the control signal C3 is set to the "low" level and the control signals C1 and C2 are set to the "high" level.

If the redundancy partial block LRMC1 located on the left side is replaced with the partial block on the left side, and the redundancy partial block RRMC1 located on the right side is replaced with the partial block on the right side, the control signals C1 when the precharge operation is performed. , C2 and C3 are all at the "high" level, the control signal C2 is at the "low" level and the control signals C1, C3 are at the "high" level during the read or write operation.

FIG. 5 is a circuit diagram of an embodiment of a control signal generation circuit that generates the control signals C1, C2, C3 shown in FIG. 3, which includes left and right redundancy control circuits 30, 32, and inverters I1, I2. , NAND gate NA, XOR gate XOR, and OR gates OR1, OR2, OR3, OR4, OR5.

The operation of the circuit shown in Fig. 5 is as follows.

When the precharge operation is performed, the precharge control signal PRECI is at the "high" level, and the control signals C1, C2, and C3 are all at the "high" level. The precharge control signal PRECi is a signal that becomes a "high" level when one of the memory cell array blocks is selected when the row address strobe signal RAS is applied. That is, when one of the precharge control signals PREC1, PREC12, PREC23, PREC34, and PREC4 shown in Fig. 3 becomes the "high" level, it becomes a "high" level. Therefore, the control signals C1, C2, and C3 all become " high " levels so that the local data input / output line pairs are precharged.

In order to use the redundancy partial blocks LRMC1, LRMC2, LRMC3, and LRMC4 on the left side as the redundancy partial blocks on the right side when performing the read and write operations, the fuse of the left redundancy control circuit 30 is cut and the right redundancy control circuit ( Do not cut the fuse in 32). Then, the NAND gate NA generates a signal of "low" level, and the XOR gate XOR generates a signal of "high" level. The OR gates OR1 and OR2 generate signals of the "low" level and the "high" level, respectively. OR gates OR3, OR4, OR5 generate control signals C1, C2, C3 of "low" level, "high" level, and "high" level, respectively.

On the other hand, in order to use the redundancy partial blocks RRMC1, RRMC2, RRMC3, and RRMC4 on the right side as the redundancy partial blocks on the left side, the fuses of the right redundancy control circuit 32 are cut and the fuses of the left redundancy control circuit 30 are used. You do not have to cut. Then, the NAND gate NA generates a signal of "low" level, and the XOR gate XOR generates a signal of "high" level. The OR gates OR1 and OR2 generate signals of the "high" level and the "low" level, respectively. The OR gates OR3, OR4, OR5 generate control signals C1, C2, C3 of "high" level, "high" level, and "low" level, respectively.

The redundancy partial blocks RRMC1, RRMC2, RRMC3 and RRMC4 on the right side are used as the redundancy partial blocks on the right side, and the redundancy partial blocks LRMC1, LRMC2, LRMC3 and LRMC4 on the left side are used as the redundancy partial blocks on the left side. To do this, the fuses of the left and right redundancy control circuits 30 and 32 need not be cut. Then, the NAND gate NA generates a signal of "low" level, and the XOR gate XOR generates a signal of "low" level. The OR gates OR1 and OR2 each generate a "high" level signal. OR gates OR3, OR4, OR5 generate control signals C1, C2, C3 of "high" level, "low" level, and "high" level, respectively.

Therefore, the semiconductor memory device of the present invention can replace the redundancy partial block on the left side with the redundancy partial block on the right side and the redundancy partial block on the right side with the redundancy partial block on the left side.

Although the above has been described with reference to a preferred embodiment of the present invention, those skilled in the art will be variously modified and changed within the scope of the present invention without departing from the spirit and scope of the invention described in the claims below. I can understand that you can.

Accordingly, in the semiconductor memory device of the present invention, when the number of the column select signal lines where the failure of the corresponding partial block occurs is equal to or greater than the number of the column select signal lines that can be replaced by the corresponding redundancy partial blocks, the adjacent redundancy partial blocks are separated. Redundancy efficiency is increased by replacing with column select signal lines.

Claims (3)

A first partial block connected to a predetermined number of first partial local data input / output line pairs respectively connected to the first plurality of global data input / output line pairs, and a first redundancy partial block of each of the first partial blocks, respectively; A plurality of first memory cell array blocks on one left side;  And a second partial block respectively connected to a predetermined number of second partial local data input / output line pairs respectively connected to the second plurality of global data input / output line pairs, and a second redundancy partial block of each of the second partial blocks. A plurality of second memory cell array blocks on one right side; Precharge circuits for precharging each of the predetermined number of first and second partial local data input / output line pairs; The predetermined number of first and second partial local data input / output line pairs connected between each of the predetermined number of first partial local data input / output line pairs and the second partial local data input / output line pairs in response to a first control signal. A plurality of first switching means for controlling the connection therebetween; A first portion of the predetermined number of first partial local data input / output line pairs connected to the first partial block and the predetermined number of first partial local data connected to the first redundancy partial block in response to a second control signal. Second switching means for controlling the connection between the second portions of the input / output line pairs; The first number of the predetermined number of second partial local data input / output line pairs connected to the second partial block and the predetermined number of second partial local data connected to the second redundancy partial block in response to a third control signal. Third switching means for controlling the connection between the second portions of the input / output line pairs; And And control signal generating means for generating said first, second and third control signals. The method of claim 1, wherein the control signal generating means Generate the first, second, third control signals of the "high" level when the precharge operation is performed; When performing a read or write operation, the first redundancy partial block is used to replace a failure of the plurality of first memory cell array blocks, and the second redundancy partial block is used to replace the plurality of second memory cell array blocks. In order to replace the defects, the first and third control signals of the "high" level and the second control signal of the "low" level are generated, and the first redundancy partial block is used as the plurality of second memory cell array blocks. In order to replace the defects, the first control signal having a "low" level and the second and third control signals having a "high" level are generated, and the second redundancy partial block is used as the plurality of first memory cell arrays. When used to replace defective blocks, the semiconductor memory device is characterized by generating first and second control signals of "high" level and third control signals of "low" level. . The method of claim 1, wherein each of the first, second, and third switching means A semiconductor memory device comprising an NMOS transistor.

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