KR100575881B1 - A high voltage detector for a high voltage generator - Google Patents

Abstract

The present invention relates to a high voltage detector that can be operated in the same way as a general high voltage detector when the consumption of high voltage is not large, and to increase the high voltage holding time of the high voltage generator when the consumption of the high voltage is large. A high voltage detector for a high voltage generator according to the present invention includes a first differential amplifier for receiving a first reference voltage and a second reference voltage (voltage obtained by voltage division of a high voltage) and outputting a first signal; A second differential amplifier for receiving a three reference voltage (voltage obtained by voltage division of the high voltage and lower than the second reference voltage) and outputting a second signal, and detecting an enable time of the first signal to detect the first A first detector for outputting a signal, a second detector for detecting a disable point in time of the second signal, and outputting a second detection signal, and receiving a first detection signal and a second detection signal and outputting a third detection signal And a flip-flop circuit and an output unit for receiving the first signal, the third detection signal, and the operation mode signal and outputting an output signal of the high voltage detector. In the standby mode and the burn-in mode, the high voltage detector of the present invention operates in the same manner as the conventional circuit operation, but in the active mode, it is possible to output a relatively stable high voltage level by delaying the time when the pumping circuit is deactivated. Make sure

Description

High voltage detector for a high voltage generator

1 is a basic block diagram of a typical high voltage generator.

2A is an example of a typical high voltage detector.

2B is a graph illustrating a relationship between an output signal (Enable) and a high voltage of a high voltage generator.

3A is an example of a high voltage detector in accordance with an embodiment of the present invention.

3B is a waveform diagram of an output signal of the high voltage detector shown in FIG. 3A.

4A is a waveform diagram of a signal to be used in an active mode.

4B is a circuit for generating an Enable_A signal to be used in an active mode.

4C is a waveform diagram of a signal output from the circuit shown in FIG. 4B.

5A is a circuit diagram according to the present invention for generating signals for sequentially operating a ring oscillator and a pumping circuit in accordance with an operating mode.

5B is a waveform diagram of an output signal of the circuit shown in FIG. 5A.

The present invention relates to a high voltage detector for use in a high voltage generator, in particular, when the high voltage consumption is not large, the same operation as a general high voltage detector, when the high voltage consumption is high high voltage detector that can increase the high voltage holding time of the high voltage generator It is about.

In general, a high voltage refers to a voltage having a higher potential than a voltage provided to a semiconductor device. Hereinafter, the operation of the high voltage generator will be briefly described.

1 shows a basic block diagram of a typical high voltage generator.

In FIG. 1, a high voltage detector (VPP detector) 100 is a device for detecting a potential level of a high voltage, and detects when a high voltage falls below a predetermined level to generate a signal (Enable) that activates the ring oscillator 110. Let's do it.

The ring oscillator 110 starts oscillation by an enable signal. The oscillation frequency of the ring oscillator is appropriately selected to efficiently form a high voltage, and the oscillation signal output from the ring oscillator is represented by OSC.

The control signal generator 120 receives the oscillation signal OSC and applies a predetermined control signal CTR PULSE to the pumping circuit 130 that outputs the high voltage VPP by the charge pumping operation.

The pumping circuit 130 outputs the high voltage VPP by the pumping operation.

Since the basic structure and operation of the high voltage generator described above are well known to those skilled in the art, a detailed description thereof will be omitted. However, since the present invention relates to a high voltage detector, it will be described in detail below.

Figure 2a is an example of a general high voltage detector, the basic structure is in the form of a differential amplifier.

In FIG. 2A, VPP denotes a high voltage, VREF denotes a reference voltage having a substantially constant voltage level regardless of the change in the supply voltage VDD, and VBIAS denotes a bias signal that controls the operation of the high voltage detector. The VPP_REF is designed to be equal to the voltage level of the VREF when the voltage level of the high voltage VPP is equal to the target value of the designer. For example, if VDD is 3V, the target high voltage is 3.5V, and VREF is 1.5V, VPP_REF is designed to be 1.5V when the high voltage is 3.5V by resistance distribution.

In operation, when the high voltage (VPP) level falls below the target value, the high voltage detector outputs a high level enable signal. In this case, the ring oscillator and the pumping circuit of the high voltage generator operate sequentially to raise the potential level of the high voltage.

Next, if the high voltage (VPP) level is higher than the target value, the high voltage detector outputs a low level enable signal. In this case, the operation of the ring oscillator and the pumping circuit of the high voltage generator is interrupted to stop the pumping operation of the high voltage generator.

By the way, in the case of a semiconductor device using such a high voltage generator, for example, a memory device, since high voltage demand is not high in the standby mode, high voltage generation is easy. In addition, in the burn-in mode, the high power supply makes it easy to generate a high voltage.

However, in the active mode, the consumption of the high voltage is large, so the level of the high voltage tends to be low. In particular, when several banks existing in the memory device are active at the same time, a phenomenon in which the potential level of the high voltage falls is prominent.

2B is a graph illustrating a relationship between an output signal (Enable) and a high voltage of the high voltage generator.

As shown, when the potential level of the high voltage falls below a predetermined level (target value), the output signal (Enable) of the high voltage detector becomes a high level, and as a result, the potential level of the high voltage rises due to the operation of the pumping circuit. When the potential level of the high voltage rises above a certain level by the pumping operation, the output signal (Enable) of the high voltage detector becomes a low level and the pumping operation is stopped, and as a result, the potential level of the high voltage drops rapidly. have. Sudden drop in the high voltage potential level due to interruption of the pumping operation results in a drop in the average high voltage potential level, which leads to instability of the operation of the memory device.

SUMMARY OF THE INVENTION The present invention has been proposed to solve the above-described problem, and an object thereof is to provide a high voltage detector capable of stably maintaining an average high voltage level even when the memory device operates in an active mode.

To this end, in the present invention, in the standby mode and burn-in mode, the high voltage detector is operated in the same manner as a conventional high voltage detector, and in the active mode, the operation time of the high voltage detector can be increased to increase the average voltage level of the high voltage. To provide.

A high voltage detector for a high voltage generator according to the present invention includes a first differential amplifier for receiving a first reference voltage and a second reference voltage (voltage obtained by voltage division of a high voltage) and outputting a first signal, the first reference voltage and A second differential amplifier receiving a third reference voltage (voltage obtained by voltage division of a high voltage and lower than the second reference voltage) and outputting a second signal, and detecting an enable time point of the first signal A first detector for outputting a first detection signal, a second detector for detecting a disable point in time of the second signal, and outputting a second detection signal, a third detection signal for receiving the first detection signal and a second detection signal; A flip-flop circuit for outputting a detection signal, and an output unit for receiving the first signal, the third detection signal, and an operation mode signal to output an output signal of a high voltage detector.

In the present invention, when the second reference voltage is lower than the first reference voltage, the first signal of the first differential amplifier is enabled, and when the second reference voltage is higher than the first reference voltage, The first signal of the first differential amplifier is disabled; The second signal of the second differential amplifier is enabled when the third reference voltage is lower than the first reference voltage, and the second signal of the second differential amplifier is enabled when the third reference voltage is higher than the first reference voltage. The second signal is disabled. Here, the third detection signal output from the flip-flop circuit is enabled by the first detection signal, and is disabled by the second detection signal. In addition, the operation mode signal includes a standby mode, an active mode, and a burn-in mode of the semiconductor device. Here, in the standby mode and the burn-in mode, an enable time point of the output signal of the output unit is synchronized with an enable time point of the first signal output from the first differential amplifier, and the disable time point is the first differential amplifier. Synchronized with the disable timing of the first signal output from the; In the active mode, an enable time point of the output signal of the output unit is synchronized with an enable time point of the first signal output from the first differential amplifier, and a disable time point is output from the flip-flop. Synchronized at the time of disable of.

(Example)

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

3A is an example of a high voltage detector according to an embodiment of the present invention.

As shown, the high voltage detector according to the embodiment of the present invention has two differential amplifiers 301 and 302.

In FIG. 3A, VPP represents a high voltage, VREF represents a reference voltage having a substantially constant voltage level regardless of the change in supply voltage VDD, and VBIAS represents a bias signal that controls the operation of the high voltage detector.

VPP_REF1 represents an input signal applied to the differential amplifier 301, and VPP_REF2 represents an input signal applied to the differential amplifier 302. Here, the input signal VPP_REF1 is designed to be equal to the voltage level of the VREF when the voltage level of the high voltage VPP is equal to the target value of the designer.

As can be seen in the figure, the voltage level of the input signal VPP_REF1 is higher than the voltage level of the input signal VPP_REF2. In addition, the reference voltage VREF applied to each differential amplifier is the same. Therefore, the operation of the circuit of FIG. 2A is as follows.

In operation, the potential level of the high voltage is much higher than the target value such that the input signals VPP_REF1 and VPP_REF2 are higher than the reference voltage VREF. In this case, the output signals Enable1 and Enable2 of the differential amplifiers 301 and 302 will both maintain a low level.

Next, assume that the potential level of the high voltage is maintained so that the input signal VPP_REF1 is higher than the reference voltage VREF and the input signal VPP_REF2 is lower than the reference voltage VREF. This case shows a case where the potential level of the high voltage is slightly higher than the target value. In this case, the output signal Enable1 of the differential amplifier 301 is at a low level, and the output signal Enable2 of the differential amplifier 302 is at a high level.

Next, when the high voltage is less than or equal to the target value, since the input signals VPP_REF1 and VPP_REF2 are lower than the reference voltage VREF, the output signals Enable1 and Enable2 of the differential amplifiers 301 and 302 both become high levels.

Next, when the output signals Enable1 and Enable2 of the differential amplifiers 301 and 302 are both at a high level, and the potential level of the high voltage exceeds the target value by the pumping operation, the output signal of the differential amplifier 301 is enabled. Goes to the low level. However, the output signal Enable2 of the differential amplifier 302 maintains a high level until the high voltage level far exceeds the target value and then transitions to a low level.

FIG. 3B is a diagram illustrating a waveform of an output signal of the high voltage detector illustrated in FIG. 3A.

As shown in FIG. 3B, the output signal Enable2 of the differential amplifier 302 transitions to a high level faster than the output signal Enable1 of the differential amplifier 301 and to a low level later.

In the present invention, when the memory device is in the standby mode and the burn-in mode, the pumping circuit is operated using the output signal Enable1 of the differential amplifier 301, and in the active mode, the output signals Enable1 and Enable2 are combined. We want to operate the pumping circuit.

4A shows a waveform diagram of a signal to be used in the active mode.

In FIG. 4A, the Enable1 signal is a signal used in the standby mode and the burn-in mode, and Enable_A is a signal used in the active mode. As shown, the rising timing of the Enable_A signal used in the active mode is synchronized to the rising edge of the Enable1 signal, and the polling timing of the Enable_A signal is synchronized to the falling edge of the Enable2 signal.

4B shows a circuit for generating an Enable_A signal to be used in the active mode.

As shown, the circuit of FIG. 4B includes a detector 401 that receives an Enable1 signal and outputs an X signal, a detector 402 that receives an Enable2 signal and outputs a Y signal, and receives X and Y signals to enable_A. And a flip-flop 403 for outputting a signal.

The detector 401 includes an Enable1 signal and a NAND gate NA1 that receives a signal obtained by delaying Enable1 for a predetermined time and inverting the enable1.

The detector 402 includes a NAND gate NA2 that receives an inverted signal of the Enable2 signal and a signal obtained by delaying Enable2 for a predetermined time.

The flip-flop 403 receives the X and Y signals through the NAND type flip-flops NA3 and NA4 and outputs an Enable_A signal.

FIG. 4C shows a waveform diagram of a signal output from the circuit shown in FIG. 4B.

As shown, the signal X transitions from high to low in synchronization with the rising edge of the Enable1 signal, and then transitions to a high level after a period of time. The signal Y transitions from high to low in synchronization with the falling edge of the Enable2 signal, and then transitions to a high level after a predetermined time. The Enable_A signal transitions to the high level in synchronization with the falling edge of signal X and transitions to the low level in synchronization with the falling edge of signal Y.

5A is a circuit diagram in accordance with the present invention for generating signals for sequentially operating a ring oscillator and pumping circuit in accordance with an operating mode.

In FIG. 5A, when the level of ACT_EN is high level, the memory device is in active mode, when the level of ACT_EN is low level, the memory device is in standby mode, and when the level of Burn-In is high level, the memory device is burn-in. Mode. Enable_FIN is a signal applied to the ring oscillator constituting the high voltage generator. When the level of the enable_FIN signal is high, the ring oscillator is operated.

The circuit of FIG. 5A includes a detector 501 that receives an Enable1 signal and outputs an X signal, a detector 502 that receives an Enable2 signal and outputs a Y signal, and a flip that receives the X and Y signals and outputs an Enable_A signal. And a flop 503.

The detector 501 includes a NAND gate NA1 that receives an Enable1 signal and a signal obtained by delaying and inverting Enable1 for a predetermined time.

The detector 502 includes a NAND gate NA2 that receives an inverted signal of the Enable2 signal and a signal obtained by delaying Enable2 for a predetermined time.

The flip-flop 503 receives the X and Y signals with the NAND type flip-flops NA3 and NA4 and outputs an Enable_A signal.

The output unit 504 includes a NAND gate NA5 that receives an Enable_A signal, an ACT_EN signal, and a Burn-In signal, an inverter 54 that receives an output signal of the NAND gate NA5, an Enable1 signal, and the inverter 54. NOR gate (NOR) for receiving the output signal of the) and an inverter 55 for receiving the output signal of the NOR gate to output the Enable_A signal. Here, the NOR gate NOR and the inverter 55 may be replaced with an OR gate.

In addition, the circuit configurations of the detectors 501 and 502, the flip-flop circuit 503, and the output unit 504 of the present invention are one embodiment of the present invention, and various circuit modifications for obtaining the same output waveform are possible.

FIG. 5B shows a waveform diagram of the output signal of the circuit shown in FIG. 5A.

As shown, the waveform diagrams of Enable1, Enable2, and Enable_A are the same as in FIG. 4C.

When in standby mode (that is, when ACT_EN is low level), the waveform of the Enable_FIN signal is the same as that of the Enable1 signal.

In the burn-in mode (that is, when Burn_In is at a high level), the waveform of the Enable_FIN signal is the same as that of the Enable1 signal.

Therefore, in the standby mode and the burn-in mode, when the high voltage generated from the high voltage generator falls below the target value, the high voltage detector detects this and starts the pumping operation of the high voltage generator. When the high voltage rises above the target value by the pumping operation, the high voltage detector is detected. Detects this and stops the pumping operation of the high voltage generator.

However, in the active mode (ie, when ACT_EN is at a high level), the rising edge of the Enable_FIN signal is synchronized with the rising edge of the Enable1 signal, and the falling edge of the Enable_FIN signal is synchronized with the falling edge of the Enable2 signal. Therefore, in the active mode, when the high voltage falls below the target value, the high voltage generator starts the pumping operation and continues to perform the pumping operation for a predetermined time even when the high voltage reaches the target value by the pumping operation. Thereafter, the pumping operation is stopped in synchronization with the falling edge of the Enable2 signal. Therefore, in the active mode with high voltage consumption, the pumping operation time of the high voltage generator is increased to increase the average value of the high voltage. Therefore, the memory device operating in the active mode can be supplied with a stable high voltage.

The present invention provides a circuit for classifying an operation mode of a memory device into a standby mode, a burn-in mode, and an active mode to operate a high voltage generator to suit each mode. However, this technical concept of the present invention is applicable to all semiconductor devices using a high voltage generator.

As can be seen from the above, the high voltage detector of the present invention operates in the same manner as the conventional circuit operation in the standby mode and the burn-in mode, but in the active mode, the pumping circuit is deactivated, thereby delaying the relative time. It is possible to output stable high voltage level.

Claims (9)

A first differential amplifier receiving a first reference voltage and a second reference voltage (voltage obtained by voltage division of the high voltage) and outputting a first signal; A second differential amplifier receiving the first reference voltage and the third reference voltage (voltage obtained by voltage division of high voltage and lower than the second reference voltage) and outputting a second signal; A first detector for detecting an enable time of the first signal and outputting a first detection signal; A second detector for detecting a disable time point of the second signal and outputting a second detection signal; A flip-flop circuit which receives the first detection signal and the second detection signal and outputs a third detection signal; And an output unit configured to receive the first signal, the third detection signal, and an operation mode signal to output an output signal of a high voltage detector. The method of claim 1, wherein the first signal of the first differential amplifier is enabled when the second reference voltage is lower than the first reference voltage, and when the second reference voltage is higher than the first reference voltage. The first signal of the first differential amplifier is disabled, The second signal of the second differential amplifier is enabled when the third reference voltage is lower than the first reference voltage, and the second signal of the second differential amplifier is enabled when the third reference voltage is higher than the first reference voltage. And the second signal is disabled. 3. The high voltage detector of claim 2, wherein the third detection signal output from the flip-flop circuit is enabled by the first detection signal and is disabled by the second detection signal. 4. The high voltage detector of claim 3, wherein the operation mode signal comprises a standby mode, an active mode, and a burn-in mode of a semiconductor device. The method of claim 4, wherein in the standby mode and the burn-in mode, an enable time point of the output signal of the output unit is synchronized with an enable time point of the first signal output from the first differential amplifier, and the disable time point is Synchronized with the disable timing of the first signal output from the first differential amplifier, In the active mode, an enable time point of the output signal of the output unit is synchronized with an enable time point of the first signal output from the first differential amplifier, and a disable time point is output from the flip-flop. A high voltage detector for a high voltage generator, characterized in that it is synchronized with the time of disabling. The high voltage detector of claim 1, wherein when the high voltage reaches a target value, the second reference voltage is set to have the same potential level as the first reference voltage. The method of claim 1, wherein the first detector includes a first NAND gate configured to receive a signal obtained by delaying and inverting the first signal and the first signal for a predetermined time. And the second detector comprises a second NAND gate for receiving an inverted signal of the second signal and a signal obtained by delaying the second signal for a predetermined time. 8. The high voltage detector of claim 7, wherein the flip flop is a NAND type flip flop. The method of claim 8, The output unit A NAND gate configured to receive a third detection signal and the operation mode signal; An inverter receiving the output signal of the NAND gate; And an OR gate configured to receive the first detection signal and the output signal of the inverter.

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