KR100572333B1 - Nor flash memory device being capable of simply discharging data line - Google Patents

Abstract

The present invention relates to a NOR flash memory device capable of simply discharging a data line. The NOR flash memory device according to the present invention includes a sense amplifier circuit for sensing and amplifying a current of a memory cell, a tri-state buffer for receiving an output value of the sense amplifier circuit, a data latch circuit for latching an output value of the tri-state buffer, And a data line connecting the status buffer and the data latch circuit. The NOR flash memory device according to the present invention removes the charge in the data line by using a latch enable signal applied to the tri-state buffer before the read operation. According to the present invention, since a separate circuit for discharging the data line is unnecessary, the area of the NOR flash memory device can be reduced.

Description

NOR FLASH MEMORY DEVICE BEING CAPABLE OF SIMPLY DISCHARGING DATA LINE} for Easy Discharge of Data Lines

1 is a block diagram illustrating a NOR flash memory device according to an exemplary embodiment of the present invention.

FIG. 2 is a circuit diagram illustrating an embodiment of the tristate buffer shown in FIG. 1.

3 is a circuit diagram illustrating an embodiment of the data latch circuit shown in FIG. 1.

4 is a timing diagram illustrating an operation of the NOR flash memory illustrated in FIG. 1.

* Description of the symbols for the main parts of the drawings *

10: memory cell 20: bit line discharge circuit

100: sense amplifier circuit 200: tri-state buffer

300: data latch circuit

The present invention relates to a nonvolatile memory device, and more particularly, to a NOR flash memory device capable of simply discharging a data line.

A non_volatile memory device is a memory device that is stored without losing data even when the power supply is cut off. The nonvolatile memory device includes a programmable ROM (PROM), an erasable PROM (EPROM), an electrically EPROM (EEPROM), a flash memory device (Flash Memory Device), and the like.

Flash memory devices have low power consumption and free input and output of information, making them suitable for mobile devices such as digital cameras, mobile phones, and PDAs. Flash memory devices are roughly divided into NAND and NOR types according to the structure of a memory cell array. NAND flash memory devices are relatively simple in structure, making them suitable for increasing memory capacity and being cheaper than the NOR type. NAND flash memory devices are data storage type memory devices mainly used for USB storage devices and MP3 players. On the other hand, the NOR flash memory device is a code storage type memory device and is used in a mobile phone terminal for which high speed data processing is necessary because of its fast processing speed.

NOR flash memory devices remove charges from previous sensing processes before reading data stored in memory cells. The NOR flash memory device according to the prior art includes a bit line discharge circuit to remove charge stored in the bit line before a read operation. The bit line discharge circuit consists of an NMOS transistor connected between the bit line and ground. When a bit line discharge signal is applied to the bit line discharge circuit, the charge remaining on the bit line is removed.

Meanwhile, the NOR flash memory device according to the related art includes a data line discharge circuit for removing a charge stored in a data line before a read operation. The data line discharge circuit consists of an NMOS transistor coupled between the data line and ground. When a control signal is applied to the data line discharge circuit, the charge remaining on the data line is removed.

However, the data line discharge circuit for discharging the data line has a problem of occupying a large area since it must be provided for each sense amplifier circuit. In addition, there is a problem in that a control signal for controlling the data line discharge circuit must be provided every time a read operation is started.

SUMMARY OF THE INVENTION The present invention has been proposed to solve the above problems, and an object of the present invention is to provide a NOR flash memory device capable of eliminating a data line discharge circuit and a control signal used for each memory cell.

The NOR flash memory device according to the present invention comprises: a sense amplifier circuit for sensing and amplifying current of a memory cell; A tri-state buffer receiving an output value of the sense amplifier circuit; And a data latch circuit for latching an output value of the tristate buffer, wherein the tristate buffer initializes the data latch circuit in response to a latch enable signal.

In this embodiment, the latch enable signal is generated before the data latch circuit latches the output value of the tri-state buffer.

In this embodiment, the tri-state buffer includes an inverter for inverting the output value of the sense amplifier circuit. Here, the inverter is characterized in that the operation in response to the latch enable signal.

In this embodiment, the data latch circuit operates in response to the latch enable signal.

In addition, another aspect of the NOR flash memory device according to the present invention includes a memory cell connected to a bit line; A bit line discharge circuit for discharging the bit line; A sense amplifier circuit for sensing and amplifying the current in the bit line; A tri-state buffer receiving an output value of the sense amplifier circuit; A data latch circuit for latching an output value of the tri-state buffer; And a data line connecting the tri-state buffer and the data latch circuit, wherein after the bit line discharge circuit discharges the bit line, the tri-state buffer closes the data line in response to a latch enable signal. It is characterized by discharging.

In this embodiment, the bit line discharge circuit is characterized in that the NMOS transistor to discharge the bit line in response to a bit line discharge signal.

In this embodiment, the sense amplifier circuit is characterized in that its output value is set to a high level when the bit line is discharged.

In this embodiment, the latch enable signal is generated before the data latch circuit latches the output value of the tri-state buffer.

In this embodiment, the tri-state buffer includes an inverter for inverting the output value of the sense amplifier circuit. Here, the inverter is characterized in that the operation in response to the latch enable signal.

In this embodiment, the data latch circuit operates in response to the latch enable signal.

DETAILED DESCRIPTION Hereinafter, exemplary embodiments of the present invention will be described with reference to the accompanying drawings so that those skilled in the art may easily implement the technical idea of the present invention. do.

1 is a block diagram illustrating a NOR flash memory device according to an exemplary embodiment of the present invention. Referring to FIG. 1, the NOR flash memory device 1 includes a memory cell 10, a bit line discharge circuit 20, a sense amplifier circuit 100, a three-state buffer 200, and a data latch circuit 300. ).

The memory cell (MC) 10 is a cell transistor used in a flash memory. The memory cell 10 has a source and a drain doped with N + impurities with a channel region between the P-type semiconductor substrates interposed therebetween. And a floating gate formed on the channel region with a thin insulating film of 100 Å or less therebetween, and a control gate formed on the floating gate with an insulating film interposed therebetween. The source, drain, control gate, and semiconductor substrate of the memory cell 10 are connected to power terminals for applying voltages required for program, erase, and read operations, respectively. . The control gate is connected to the word line WL, the drain is connected to the bit line BL, and the source is connected to the sensing line SL.

In a read operation, a voltage applied to the power terminals of the memory cell 10 may be a positive voltage (eg, 1V) at a drain, a predetermined voltage (eg, 4.5V) at a gate, and 0V at a source. to be. When the read operation is performed according to the above conditions, the programmed cell blocks the current path from the drain to the source, and the erased cell forms the current path. Herein, the programmed cell is called an 'off cell' and stores data '0'. The erased cell is called an "on cell" and stores data "1".

The sense amplifier circuit 100 senses and amplifies the current of the bit line BL connected to the memory cell 10. Depending on whether the memory cell 10 is an OFF cell or an ON cell, the amount of current flowing in the bit line BL during a read operation varies.

The sense amplifier circuit 100 includes PMOS transistors P1 and P2 forming a current mirror and an NMOS transistor N1 that receives a reference voltage Vref. Here, the reference voltage Vref is provided in a reference voltage generation circuit (not shown).

When the voltage between the gate and the source of the PMOS transistor P2 is lower than the threshold voltage of the PMOS transistor P2, a current flows through a current path formed between the source and the drain of the PMOS transistor P2. Will flow. At this time, when the amount of current flowing through the PMOS transistor P2 is greater than the amount of current flowing through the NMOS transistor N1, the voltage level of the output node SA0 of the sense amplifier circuit 100 increases.

The tri-state buffer 200 receives an output value of the sense amplifier circuit 100. The tri-state buffer 200 initializes the data latch circuit 300 in response to the latch enable signals ENLAT and nENLAT. The latch enable signals ENLAT and nENLAT are signals complementary to each other. The structure and operation of the tri-state buffer 200 will be described in detail with reference to FIG.

The data latch circuit 300 is connected to the tri-state buffer 200 through a data line DL. The data latch circuit 300 latches an output value of the tri-state buffer 200 in response to the latch enable signals ENLAT and nENLAT. The structure and operation of the data latch circuit 300 will be described in detail with reference to FIG. 3.

Meanwhile, the bit line discharge circuit 20 is a circuit for removing the charge in the bit line BL before reading the data stored in the memory cell 10. The bit line discharge circuit 20 is connected to the bit line BL. The bit line discharge circuit 20 includes an NMOS transistor N2 that discharges the bit line BL in response to a bit line discharge signal BLDIS. A drain of the NMOS transistor N2 is connected to a bit line BL, a source is connected to ground, and a gate receives the bit line discharge signal BLDIS.

When the bit line discharge circuit 20 discharges the bit line BL, the PMOS transistor P2 of the sense amplifier circuit 100 is turned on. At this time, the output node SA0 of the sense amplifier circuit 100 is set to a high level. In the state where the output node SA0 is set to the high level, the latch enable signals ENLAT and nENLAT are applied to the tri-state buffer 200. When the latch enable signals ENLAT and nENLAT are applied, the data latch circuit 300 is initialized. That is, the charge in the data line DL is discharged through the tri-state buffer 200.

In general, NOR flash memory devices have means for removing charges in the bit and data lines prior to a read operation. In particular, separate control signals and NMOS transistors are needed to remove the charge on the data lines. The NOR flash memory device 1 according to the present invention removes the charge in the data line DL by using the latch enable signals ENLAT and nENLAT applied to the tri-state buffer 200 before a read operation.

FIG. 2 is a circuit diagram illustrating an embodiment of the tristate buffer shown in FIG. 1. Referring to FIG. 2, the tri-state buffer 200 includes an inverter connected to an output node SA0 and a data line DL of the sense amplifier circuit 100 (see FIG. 1). The inverter consists of a PMOS transistor P3 and an NMOS transistor N3. The inverter inverts the output value of the sense amplifier circuit 100.

The tri-state buffer 200 operates in response to the latch enable signals ENLAT and nENLAT. The tri-state buffer 200 further includes a PMOS transistor P4 and an NMOS transistor N4. The PMOS transistor P4 is connected between a power supply terminal VCC and the inverter. The NMOS transistor N4 is connected between the inverter and ground. The PMOS transistor P4 receives a latch enable signal nENLAT, and the NMOS transistor N4 receives a latch enable signal ENLAT.

When the latch enable signal ENLAT is activated while the output value of the sense amplification circuit 100 is set to a high level, the electric charge in the data line DL is removed. That is, the charge in the data line DL exits to ground through the NMOS transistors N3 and N4.

3 is a circuit diagram illustrating an embodiment of the data latch circuit shown in FIG. 1. Referring to FIG. 3, the data latch circuit 300 includes two inverters INV1 and INV2 and a pass transistor PT1.

The inverters INV1 and INV2 latch data input through the data line DL. The pass transistor PT1 is turned on in response to the latch enable signals ENLAT and nENLAT. That is, when the latch enable signal ENLAT is activated, the data latch circuit 300 latches an output value of the tri-state buffer 200 (see FIG. 1).

4 is a timing diagram illustrating an operation of the NOR flash memory illustrated in FIG. 1. Hereinafter, the operation of discharging the data line before the read operation will be described with reference to FIGS. 1 and 4.

First, when the bit line discharge signal BLDIS is activated, the output node SA0 of the sense amplifier circuit 100 is set to a high level. In the state where the output node SA0 of the sense amplifier circuit 100 is set to the high level, the latch enable signals ENLAT and nENLAT are input to the tri-state buffer 200. When the latch enable signals ENLAT and nENLAT are input, the charge in the data line DL is removed.

Next, when the latch enable signals ENLAT and nENLAT are input to the tristate buffer 200 and the data latch circuit 300, the data latch circuit 300 outputs the output values of the tristate buffer 200. Will latch. As shown in FIG. 4, when the memory cell 10 is a programmed cell, that is, an OFF cell, the data line DL is in a high level state. On the other hand, if the memory cell 10 is an erased cell, that is, an ON cell, the data line DL is in a low level state.

The NOR flash memory device 1 according to the present invention does not need to separately include means for removing the charge of the data line DL at an input terminal of the data latch circuit 300. The NOR flash memory device 1 according to the present invention removes the electric charge in the data line DL by applying the latch enable signals ENLAT and nENLAT to the tri-state buffer 200 before the read operation.

On the other hand, in the detailed description of the present invention has been described with respect to specific embodiments, various modifications are of course possible without departing from the scope of the invention. Therefore, the scope of the present invention should not be limited to the above-described embodiments, but should be defined by the equivalents of the claims of the present invention as well as the following claims.

As described above, the NOR flash memory device according to the present invention may remove a charge in a data line by applying a latch enable signal to a tri-state buffer before a read operation. Therefore, according to the NOR flash memory device according to the present invention, since the data line discharge circuit is unnecessary, the area of the NOR flash memory device can be reduced. In addition, according to the NOR flash memory device according to the present invention, it is possible to eliminate the inconvenience of providing a signal for controlling the data line discharge circuit before the read operation.

Claims (10)

A sense amplifier circuit for sensing and amplifying current in the memory cell; A tri-state buffer receiving an output value of the sense amplifier circuit; And A data latch circuit for latching an output value of the tri-state buffer, And the tri-state buffer initializes the data latch circuit in response to a latch enable signal. The method of claim 1, And the latch enable signal is generated before the data latch circuit latches an output value of the tri-state buffer. The method of claim 1, And the tri-state buffer includes an inverter for inverting an output value of the sense amplifier circuit, wherein the inverter operates in response to the latch enable signal. The method of claim 1, And the data latch circuit operates in response to the latch enable signal. A memory cell connected to the bit line; A bit line discharge circuit for discharging the bit line; A sense amplifier circuit for sensing and amplifying the current in the bit line; A tri-state buffer receiving an output value of the sense amplifier circuit; A data latch circuit for latching an output value of the tri-state buffer; And A data line connecting the tri-state buffer and the data latch circuit, And after the bit line discharge circuit discharges the bit line, the tri-state buffer discharges the data line in response to a latch enable signal. The method of claim 5, wherein And the bit line discharge circuit is an NMOS transistor configured to discharge the bit line in response to a bit line discharge signal. The method of claim 5, wherein And the sense amplifying circuit is set to a high level when the bit line is discharged. The method of claim 5, wherein And the latch enable signal is generated before the data latch circuit latches an output value of the tri-state buffer. The method of claim 5, wherein And the tri-state buffer includes an inverter for inverting an output value of the sense amplifier circuit, wherein the inverter operates in response to the latch enable signal. The method of claim 5, wherein And the data latch circuit operates in response to the latch enable signal.

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