KR100570475B1 - Methods of fabricating a magnetic random access memory cell having split sub-digit lines surrounded by cladding layers - Google Patents

Abstract

Provided are methods of manufacturing a magnetic ram cell having divided sub digit lines surrounded by a plating layer. These methods include forming a first interlayer insulating layer on a semiconductor substrate and forming a groove in the first interlayer insulating layer. A conformal cladding layer is formed on the substrate having the groove. A separating wall is formed on a predetermined region of the plating layer in the groove to divide at least a portion of the groove into first and second grooves. First and second sub digit lines are formed in the first and second grooves, respectively. An opening is formed through the isolation wall and the plating layer and passes through the area between the sub digit lines, and a spacer is formed on the sidewall of the opening. The first interlayer insulating layer is etched using the spacer as an etch mask to form a magnetoresistive contact hole exposing the semiconductor substrate.

Description

Methods of fabricating a magnetic random access memory cell having split sub-digit lines surrounded by cladding layers}

1 is a cross-sectional view showing a conventional magnetic ram cell.

2 is a cross-sectional view illustrating a conventional magnetic ram cell having divided sub digit lines.

3 is a cross-sectional view illustrating magnetic ram cells according to example embodiments.

4 through 10 are cross-sectional views for describing a method of manufacturing a magnetic ram cell according to example embodiments.

The present invention relates to methods of fabricating semiconductor memory cells, and more particularly to methods of fabricating magnetic RAM cells having divided sub digit lines surrounded by a plating layer.

Magnetic RAM devices are widely used as nonvolatile memories that can operate at low voltages and high speeds. In the unit cell of the magnetic RAM device, data is stored in a magnetic tunnel junction (MTJ) of a magnetic resistor. The magnetic tunnel junction MTJ includes first and second ferromagnetic layers and a tunneling insulation layer interposed therebetween. Magnetic polarization of the first ferromagnetic layer, also referred to as a free layer, can be varied using a magnetic field across the magnetic tunnel junction. The magnetic field may be induced by a current passing around the magnetic tunnel junction, and the magnetic polarization of the free layer is parallel or antiparallel to the magnetic polarization of the second ferromagnetic layer, also referred to as a pinned layer. It can be anti-parallel. Current for generating the magnetic field flows through a conductive layer called a digit line disposed around the magnetic tunnel junction.

According to spintronics based on quantum mechanics, when the magnetic spindles in the free layer and the fixed layer are arranged parallel to each other, the tunneling current flowing through the magnetic tunnel junction shows a maximum value. In contrast, when the magnetic spindles in the free layer and the fixed layer are arranged antiparallel to each other, the tunneling current flowing through the magnetic tunnel junction shows a minimum value. Thus, the data of the magnetic ram cell may be determined according to the direction of the magnetic spindle in the free layer.

1 is a cross-sectional view showing a conventional magnetic ram cell.

Referring to FIG. 1, a first interlayer insulating layer 3 is stacked on a semiconductor substrate 1. The digit line 5 is disposed on the first interlayer insulating layer 3. The digit line 5 and the first interlayer insulating layer 3 are covered with a second interlayer insulating layer 7. The magnetoresistive member 16 is disposed on the second interlayer insulating layer 7 so as to overlap a predetermined region of the digit line 5. The magnetoresistive body 16 includes a lower electrode 11, a magnetic tunnel junction 13, and an upper electrode 15 that are sequentially stacked. The magnetoresistive body 16 and the second interlayer dielectric layer 7 are covered with a third interlayer dielectric layer 17. A bit line 19 electrically connected to the upper electrode 15 is disposed on the third interlayer insulating layer 17.

The lower electrode 11 should be electrically connected to a predetermined region of the semiconductor substrate 1. Therefore, the lower electrode 11 should be formed to have a wider width than the digit line 5. In other words, the lower electrode 11 should be formed to have an extension portion A that does not overlap the digit line 5. The extension portion A is electrically connected to a predetermined region of the semiconductor substrate 1 through a lower electrode plug 9 penetrating the first and second interlayer insulating layers 3 and 7.

In conclusion, the extension A of the lower electrode 11 causes difficulty in shrinking the conventional magnetic ram cell size shown in FIG. 1.

Recently, a magnetic RAM cell having divided sub digit lines has been proposed to solve the above problems. In addition, a cladding layer surrounding sidewalls and bottom surfaces of the digit lines is widely used to improve the writing efficiency of the magnetic RAM cell. The magnetic ram cell employing the plating layer is described in US Patent No. 6,430,084 B1 as "Magnetic random access memory having digit lines and bit lines with a ferromagnetic cladding layer". It has been disclosed by Rizza et al. In the title.

FIG. 2 is a cross-sectional view illustrating a magnetic RAM cell in which the plating layer disclosed in US Pat. No. 6,430,084 B1 is applied to the divided sub digit lines.

Referring to FIG. 2, a first interlayer insulating layer 23 is stacked on the semiconductor substrate 21. First and second parallel sub-digit lines 27a and 27b are disposed in the first interlayer insulating layer 23. Both sidewalls and the bottom surface of the first sub digit line 27a are surrounded by the first plating layer 25a, and both sidewalls and the bottom surface of the second sub digit line 27b are also the second plating layer 25b. Surrounded by). A second interlayer insulating layer 29 is stacked on the entire surface of the semiconductor substrate having the first and second sub digit lines 27a and 27b and the first and second plating layers 25a and 25b. The predetermined region of the semiconductor substrate 21 is electrically connected to the magnetic tunnel junction contact plug 31 passing through the first and second interlayer insulating layers 23 and 29. The magnetic tunnel junction contact plug 31 passes through an area between the first and second sub digit lines 27a and 27b. A magnetic tunnel junction 33 in contact with the magnetic tunnel junction contact plug 31 is disposed on the second interlayer insulating layer 29.

When writing current is applied to the divided sub digit lines 27a and 27b to store data in the magnetic RAM cell shown in FIG. 2, first and second magnetic fields 35a and 35b are formed. do. The first and second magnetic fields 35a and 35b are mainly distributed in one side and the other side of the magnetic tunnel junction 33, respectively, as shown in FIG. 2. In other words, it is difficult to form a uniformly distributed magnetic field throughout the magnetic tunnel junction 33 during the writing operation. This is because all sidewalls of the first and second sub digit lines 27a and 27b are surrounded by the first and second plating layers 25a and 25b. Accordingly, even if the magnetic ram cell having the divided sub digit lines 27a and 27b adopts a plating layer that focuses a magnetic field, there is a limit in improving the write efficiency of the magnetic ram cell.

SUMMARY OF THE INVENTION The present invention has been made in an effort to provide methods for manufacturing magnetic RAM cells, which may improve integration efficiency as well as write efficiency.

According to one aspect of the present invention, methods of manufacturing a magnetic ram cell having divided digit lines are provided. These methods include forming a first interlayer dielectric layer on a semiconductor substrate and forming a groove in the first interlayer dielectric layer. A conformal cladding layer is formed on the substrate having the groove. A separating wall is formed on a predetermined region of the plating layer in the groove to divide at least a portion of the groove into first and second grooves. First and second sub digit lines are formed in the first and second grooves, respectively. While forming the sub digit lines, the plating layer on the top surface of the first interlayer insulating layer is selectively removed. As a result, a plating layer pattern covering only the sidewalls and the bottom surface of the groove is formed. A capping layer is formed on the substrate having the sub digit lines and the plating layer pattern. An opening penetrating the capping layer, the isolation wall, and the plating layer pattern is formed. The opening is formed to pass through an area between the first and second sub digit lines. An insulating spacer is formed on the sidewall of the opening. The first interlayer insulating layer is etched using the insulating spacer as an etch mask to form a magnetoresistive contact hole exposing the semiconductor substrate.

In some embodiments of the present invention, the groove may be formed by partially etching the first interlayer insulating layer.

In other embodiments, the plating layer may be formed of a ferromagnetic layer.

In still other embodiments, the forming of the isolation wall may include forming a molding layer on the substrate having the plating layer, planarizing the molding layer, and forming a molding layer pattern in the groove. The method may include exposing the plating layer on an upper surface of the one interlayer insulating layer and patterning the molding layer pattern.

In still other embodiments, the isolation wall may be formed to have a line shape or an island shape. When the isolation wall is formed to have the line shape, the first and second grooves may be parallel to each other. In addition, when the isolation wall is formed to have the island shape, the first and second grooves may be connected to each other to form a single merged groove.

In still other embodiments, the formation of the first and second sub digit lines may include forming a conductive layer filling the first and second grooves on the substrate having the isolation wall, and forming the conductive layer and the plating layer. Planarization may include exposing an upper surface of the first interlayer insulating layer and an upper surface of the isolation wall. The conductive layer may be formed of a copper layer, and the conductive layer and the plating layer may be planarized using a chemical mechanical polishing process.

In other embodiments, the capping layer and the insulating spacer may be formed as an insulating layer having an etch selectivity with respect to the first interlayer insulating layer.

In still other embodiments, before forming the magnetoresistive contact hole, a second interlayer insulating layer may be further formed on the substrate having the insulating spacer. In this case, the magnetoresistive contact hole may be formed by etching the first and second interlayer insulating layers using the capping layer and the insulating spacer as an etching mask.

Furthermore, a magnetoresistive contact plug can be formed in the magnetoresistive contact hole, and a magnetoresistive body electrically connected to the magnetoresistive contact plug can be formed on the insulating layer. In addition, an upper interlayer insulating layer may be formed on a substrate having the magnetoresistive body, and a bit line electrically connected to the magnetoresistive body may be formed on the upper interlayer insulating layer. The bit line may be formed to cross the upper portion of the sub digit lines.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. However, the present invention is not limited to the embodiments described herein and may be embodied in other forms. Rather, the embodiments introduced herein are provided to ensure that the disclosed subject matter is thorough and complete, and that the scope of the invention to those skilled in the art will fully convey. In the drawings, the thicknesses of layers and regions are exaggerated for clarity. Like numbers refer to like elements throughout.

3 is a cross-sectional view for describing magnetic ram cells according to example embodiments.

Referring to FIG. 3, the device isolation layer 101 is disposed in a predetermined region of the semiconductor substrate 51. The device isolation layer 101 defines an active region 101a. Source regions 107s and drain regions 107d spaced apart from each other are provided in the active region 101a. The gate electrode 105 is disposed on the channel region between the source region 107s and the drain region 107d. The gate electrode 105 may extend to cross the upper portion of the active region 101a to serve as a word line. A gate insulating layer 103 is interposed between the gate electrode 105 and the channel region. The gate electrode 105, the source region 107s and the drain region 107d constitute an access transistor.

The semiconductor substrate having the access transistor is covered with a lower interlayer insulating layer 109. The common source line 111 is disposed on the lower interlayer insulating layer 109. The common source line 111 is electrically connected to the source region 107s through a common source line contact plug 110 passing through the lower interlayer insulating layer 109. The common source line 111 may be disposed to be parallel to the gate electrode 105.

The common source line 111 and the lower interlayer insulating layer 109 are covered with a first interlayer insulating layer 53. First and second sub digit lines 57a and 57b spaced apart from each other are disposed in the first interlayer insulating layer 53. A bottom surface and an outer sidewall of the first sub digit line 57a are surrounded by a first cladding layer pattern 55a. The outer wall of the first sub digit line 57a corresponds to a side wall located opposite the second sub digit line 57b. Similarly, the bottom surface and the outer wall of the second sub digit line 57b are surrounded by a second cladding layer pattern 55b. The first and second sub digit lines 57a and 57b are conductive layers such as a copper layer or an aluminum layer, and the first and second plating layer patterns 55a and 55b are nickel iron (NiFe). It is preferable that the ferromagnetic layer (ferromagnetic layer). The first and second plating layer patterns 55a and 55b focus magnetic flux generated by a current flowing through the first and second sub digit lines 57a and 57b.

The first and second sub digit lines 57a and 57b may extend to contact each other. In this case, a hole-shaped opening is provided between the first and second sub digit lines 57a and 57b. Alternatively, the first and second sub digit lines 57a and 57b may extend and be parallel to each other. In this case, a line-shaped opening is provided between the first and second sub digit lines 57a and 57b.

The first interlayer insulating layer 53 may include a first lower interlayer insulating layer 53a and a first upper interlayer insulating layer 53b that are sequentially stacked. In this case, the first and second plating layer patterns 55a and 55b together with the first and second sub digit lines 57a and 57b may be provided in the first upper interlayer insulating layer 53b. have.

Top surfaces of the first and second sub digit lines 57a and 57b may be covered with a capping layer 59. The capping layer 59 extends to cover the first interlayer insulating layer 53. In addition, inner sidewalls of the first and second sub digit lines 57a and 57b, that is, sidewalls of the opening, may be covered with an insulating spacer 65. The insulating spacer 65 preferably extends to cover sidewalls of the capping layer 59 on the first and second sub digit lines 57a and 57b.

The semiconductor substrate having the capping layer 59 and the insulating spacer 65 is covered with a second interlayer insulating layer 67. The capping layer 59 and the insulating spacer 65 may be an insulating layer having an etch selectivity with respect to at least the first and second interlayer insulating layers 53 and 67. For example, when the first and second interlayer insulating layers 53 and 67 are silicon oxide layers, the capping layer 59 and the insulating spacer 65 may be silicon nitride layers. The drain region 107d is electrically connected to the magnetoresistive contact plug 69 passing through the first and second interlayer insulating layers 53 and 67 and the lower interlayer insulating layer 109. The magnetoresistive contact plug 69 passes through an area between the first and second sub digit lines 57a and 57b. In this case, the magnetoresistive contact plug 69 may be self-aligned with the sub digit lines 57a and 57b due to the presence of the capping layer 59 and the insulating spacer 65.

A magnetoresistive element 71 is provided on the second interlayer insulating layer 67 to cover the magnetoresistive contact plug 69. The magnetoresistance 71 may include a lower electrode 121, a pinning layer 123, a pinned layer 125, a tunneling insulation layer 127, and a free layer, which are sequentially stacked. 129 and the upper electrode 131. In this case, the lower electrode 121 is electrically connected to the magnetoresistive contact plug 69. The pinning layer 123 is an antiferromagnetic layer, and the pinned layer 125 and the free layer 129 are ferromagnetic layers. In addition, the tunneling insulating layer 127 may be an insulating layer such as an aluminum oxide layer.

The magnetoresistive element 71 and the second interlayer dielectric layer 67 are covered with an upper interlayer dielectric layer 73. The bit line 75 is provided on the upper interlayer insulating layer 73. The bit line 75 is disposed to cross the upper portions of the first and second sub digit lines 57a and 57b and passes through the bit line contact hole through the upper interlayer insulating layer 73. And electrically connected to 131.

4 to 10 are cross-sectional views illustrating methods of manufacturing the magnetic ram cell shown in FIG. 3.

Referring to FIG. 4, a first interlayer insulating layer 53 is formed on the semiconductor substrate 51. Prior to forming the first interlayer insulating layer 53, the device isolation layer 101, the access transistor, the lower interlayer insulating layer 109 and the common shown in FIG. The source line 111 may be formed.

The first interlayer insulating layer 53 is partially etched to form a groove G. A conformal cladding layer 55 and a molding layer filling the groove G are sequentially formed on the first interlayer insulating layer 53 having the groove G. The conformal plating layer 55 may be formed of a ferromagnetic layer, and the molding layer may be formed of a material layer having an etch selectivity with respect to the plating layer 55. For example, when the plating layer 55 is formed of a nickel iron (NiFe) layer, the molding layer may be formed of a silicon oxide film, a silicon nitride film, or a silicon oxynitride film. The molding layer is planarized to form a molding layer pattern 56 in the groove G until the plating layer 55 on the upper surface of the first interlayer insulating layer 53 is exposed. The planarization of the molding layer may be performed using an etch back process or a chemical mechanical polishing process.

The first interlayer insulating layer 53 may be formed by sequentially stacking a first lower interlayer insulating layer 53a and a first upper interlayer insulating layer 53b. In this case, the first upper interlayer insulating layer 53b may be formed of an insulating layer having an etching selectivity with respect to the first lower interlayer insulating layer 53a, and the groove G may be formed in the first layer. It may be formed in the upper interlayer insulating layer 53b.

Referring to FIGS. 5 and 6, the molding layer pattern 56 is patterned to isolate at least a portion of the groove G into first and second grooves G1 and G2. Forming a separating wall 56a. When the isolation wall 56a is formed to have a line shape, the first and second grooves G1 and G2 may be parallel to each other. Alternatively, when the isolation wall 56a is formed to have an island shape, the first and second grooves G1 and G2 may be divided into regions between the isolation walls 56a. Are connected to each other to form a merged groove.

A conductive layer filling the first and second grooves G1 and G2 is formed on the substrate having the isolation wall 56a. The conductive layer may be formed of a metal layer such as a copper layer or an aluminum layer. The embodiments may be suitable when the conductive layer is formed of a metal layer that cannot be patterned using conventional photolithography / etching processes. In other words, the embodiments may be suitable when the conductive layer is formed of a metal layer that must be patterned by a damascene process. For example, the embodiments may be effective when the conductive layer is formed of a copper layer.

The conductive layer and the plating layer 55 are planarized to expose the top surface of the first interlayer insulating layer 53 and the top surface of the isolation wall 56a. When the conductive layer is formed of a copper layer as described above, the conductive layer and the plating layer 55 may be planarized using a chemical mechanical polishing process. As a result, a plating layer pattern 55 ′ covering sidewalls and bottom surface of the groove G is formed, and first and second grooves G1 and G2 are respectively formed in the first and second grooves G1 and G2. Sub digit lines 57a and 57b are formed. When the isolation wall 56a has a line shape as described above, the first and second sub digit lines 57a and 57b may be formed to be parallel to each other. Alternatively, if the isolation wall 56a has an island shape as described above, the first and second sub digit lines 57a and 57b are connected to each other in the regions between the isolation walls 56a. To form a merged digit line.

Subsequently, a capping layer 59 may be formed on the substrate having the first and second sub digit lines 57a and 57b. The capping layer 59 may be formed of an insulating layer having an etch selectivity with respect to the first interlayer insulating layer 53. For example, when the first interlayer insulating layer 53 is formed of a silicon oxide layer, the capping layer 59 may be formed of a silicon nitride layer or a silicon oxynitride layer. On the other hand, when the first interlayer insulating layer 53 is formed by sequentially stacking the first lower interlayer insulating layer 53a and the first upper interlayer insulating layer 53b as described above, the capping layer ( 59 may be formed of an insulating layer having an etch selectivity with respect to at least the first lower interlayer insulating layer 53a.

A photoresist pattern 61 is formed on the capping layer 59. The photoresist pattern 61 is formed to have an opening 61a exposing a portion of the capping layer 59. The opening 61a may be positioned above the isolation wall 56a and may have a hole shape. The width 61w of the opening 61a may be greater than or equal to the width 56w of the isolation wall 56a. Alternatively, the width 61w of the opening 61a may be smaller than the width 56w of the isolation wall 56a.

Referring to FIG. 7, the capping layer 59, the isolation wall 56a, and the plating layer pattern 55 ′ are etched using the photoresist pattern 61 as an etching mask to form the sub digit lines ( An opening 63 passes through the area between 57a and 57b. As a result, a first plating layer pattern 55a covering only the bottom surface 57sb and the outer wall 57sw of the first sub digit line 57a is formed, and the bottom surface 57sb of the second sub digit line 57b is formed. ) And a second plating layer pattern 55b covering only the outer wall 57sw is formed. That is, no plating layer is formed on the inner walls of the first and second sub digit lines 57a and 57b. When the width 61w of the opening 61a of the photoresist pattern 61 is larger than the width 56w of the isolation wall 56a, the sub digit lines 57a and 57b are formed in the opening 63. While forming the may act as an etch stop layer. Next, the photoresist pattern 61 is removed.

Referring to FIG. 8, an insulating spacer layer is formed on the substrate from which the photoresist pattern 61 is removed, and the insulating spacer layer is anisotropically etched to form an insulating spacer 65 covering sidewalls of the opening 63. do. The insulating spacer layer may be formed of an insulating layer having an etch selectivity with respect to the first interlayer insulating layer 53. For example, when the first interlayer insulating layer 53 is formed of a silicon oxide layer, the insulating spacer layer may be formed of a silicon nitride layer or a silicon oxynitride layer. On the other hand, when the first interlayer insulating layer 53 is formed by sequentially stacking the first lower interlayer insulating layer 53a and the first upper interlayer insulating layer 53b as described above, the insulating spacer layer May be formed as an insulating layer having an etch selectivity with respect to at least the first lower interlayer insulating layer 53a. As a result, the insulating spacer 65 covers inner walls of the first and second sub digit lines 57a and 57b and inner walls of the first and second plating layer patterns 55a and 55b. Is formed.

Referring to FIG. 9, a second interlayer insulating layer 67 may be formed on a substrate having the insulating spacer 65. The second interlayer insulating layer 67 may be formed of the same material layer as the first interlayer insulating layer 53. Accordingly, the capping layer 59 and the insulating spacer 65 may have an etch selectivity with respect to the first and second interlayer insulating layers 53 and 67. Subsequently, the first and second interlayer insulating layers 53 and 67 are patterned using an etching process to pass through a region between the first and second sub digit lines 57a and 57b. The resistor contact hole 67a is formed. As shown in FIG. 3, when the access transistor and the lower interlayer insulating layer 109 are formed on the semiconductor substrate, the magnetoresistive contact hole 67a penetrates through the lower interlayer insulating layer 109 to access the access transistor. Drain region (107d in FIG. 3) is exposed.

The capping layer 59 and the spacer 65 serve as an etch stop layer while the magnetoresistive contact hole 67a is formed. Accordingly, the magnetoresistive contact hole 67a may be self-aligned with the first and second sub digit lines 57a and 57b.

Referring to FIG. 10, the magnetoresistive contact plug 69 may be formed in the magnetoresistive contact hole 67a using a conventional method. A magnetoresistive element 71 covering the magnetoresistive contact plug 69 is formed on the second interlayer insulating layer 67. The magnetoresistive element 71 sequentially forms a lower electrode layer, a pinning layer, a pinning layer, a tunneling insulation layer, a free layer, and an upper electrode layer on the magnetoresistive contact plug 69 and the second interlayer insulating layer 67. The upper electrode layer, the free layer, the tunneling insulating layer, the pinning layer, the pinning layer and the lower electrode layer may be formed by successively patterning. The pinning layer is formed of an antiferromagnetic layer, and the pinned layer and the free layer are formed of a ferromagnetic layer. Subsequently, an upper interlayer insulating layer 73 is formed on the semiconductor substrate having the magnetoresistive body 71.

The upper interlayer insulating layer 73 is patterned to form a bit line contact hole exposing the magnetoresistive element 71. Forming a conductive layer such as a metal layer on the semiconductor substrate having the bit line contact hole, patterning the conductive layer to cover the bit line contact hole and crossing the upper portion of the sub digit lines 57a and 57b. Form 75. As a result, the bit line 75 is electrically connected to the magnetoresistive element 71 through the bit line contact hole.

As described above, the first and second plating layer patterns 55a and 55b of the magnetic RAM cell according to the present invention may have only bottom surfaces and outer walls of the first and second sub digit lines 57a and 57b. It is formed to cover. Accordingly, when a write current I _D is applied to the sub digit lines 57a and 57b, a uniform magnetic field H is generated along the direction parallel to the bit line over the entire magnetoresistive element 71. Can be formed. This is because the plating layer patterns 55a and 55b are not formed on the inner walls of the sub digit lines 57a and 57b. Accordingly, the magnetic RAM cell according to the present invention may exhibit a markedly improved write efficiency compared to the prior art. In addition, the sub digit lines 57a and 57b can be patterned using a damascene technique that employs a chemical mechanical polishing process. Therefore, the present invention may be very useful when the sub digit lines 57a and 57b are formed of a copper layer.

Claims (14)

Forming a first interlayer insulating layer on the semiconductor substrate, Forming a groove in the first interlayer insulating layer, Forming a conformal cladding layer on the substrate having the groove, Forming a separating wall on a predetermined region of the plating layer in the groove to divide at least a portion of the groove into first and second grooves, Forming a plating layer pattern covering only the sidewalls and the bottom surface of the groove while exposing the top surface of the first interlayer insulating layer while forming first and second sub digit lines filling the first and second grooves, respectively; , Forming a capping layer on the substrate having the sub digit lines and the plating layer pattern; An opening passing through an area between the first and second sub-digit lines through the capping layer, the isolation wall, and the plating layer pattern, Forming a spacer covering a sidewall of the opening, Forming a magnetoresistive contact hole exposing the semiconductor substrate by etching the first interlayer insulating layer using the spacer as an etching mask. The method of claim 1, And wherein the groove is formed by partially etching the first interlayer insulating layer. The method of claim 1, The plating layer is a magnetic ram cell manufacturing method, characterized in that formed by a ferromagnetic layer. The method of claim 1, wherein forming the isolation wall Forming a molding layer on the substrate having the plating layer, Planarizing the molding layer to form a molding layer pattern in the groove while simultaneously exposing the plating layer on an upper surface of the first interlayer insulating layer; And patterning the molding layer pattern. The method of claim 1, The isolation wall is a magnetic ram cell manufacturing method, characterized in that formed to have a line form or an island form. The method of claim 5, wherein And when the isolation wall is formed to have the line shape, the first and second grooves are defined to be parallel to each other. The method of claim 5, wherein When the isolation wall is formed to have the island shape, the first and second grooves are connected to each other to form a single merged groove. The method of claim 1, wherein forming the first and second sub digit lines Forming a conductive layer filling the first and second grooves on the substrate having the isolation wall, And planarizing the conductive layer and the plating layer to expose the top surface of the first interlayer insulating layer and the top surface of the isolation wall. The method of claim 8, The conductive layer is a magnetic RAM cell manufacturing method, characterized in that formed of a copper layer. The method of claim 8, And the conductive layer and the plating layer are planarized using a chemical mechanical polishing process. The method of claim 1, And the capping layer and the spacer are formed of an insulating layer having an etch selectivity with respect to the first interlayer insulating layer. The method of claim 1, And forming a second interlayer insulating layer on the substrate having the spacers before forming the magnetoresistive contact holes, wherein the magnetoresistive contact holes are formed by using the capping layer and the spacers as etch masks. And etching the second interlayer insulating layers. The method of claim 1, Forming a magnetoresistive contact plug filling the magnetoresistive contact hole, And forming a magnetoresistance electrically connected to the magnetoresistive contact plug on the insulating layer. The method of claim 13, Forming an upper interlayer insulating layer on the substrate having the magnetoresistance; And forming a bit line electrically connected to the magnetoresistance on the upper interlayer insulating layer, wherein the bit line is formed to cross the upper portion of the sub digit lines. .

Images