KR100568420B1 - Write Malfunction Prevention Circuit in Hard Disk Drive - Google Patents

Abstract

end. The technical field to which the invention described in the claims belongs:

A technology related to hard disk drives.

I. The technical problem the invention is trying to solve:

Provided is a light malfunction prevention circuit that can guarantee the light operation even in a situation where the system power is turned on and beyond.

All. The gist of the solution of the invention:

According to the present invention, a power reset signal related to power on / off as well as a guaranteed light gate signal QWG outputted for light verification when a problem occurs during operation of a controller is provided. In combination with, the write operation is guaranteed based on the state of the guarantee light gate signal after the system power is applied without the write enable in the section where the system power is reset.

la. Important uses of the invention:

Lite control on hard disk drive

Description

Write Malfunction Prevention Circuit in Hard Disk Drive

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a hard disk drive (hereinafter referred to as an HDD), and more particularly to a circuit for preventing a write operation at power on.

These days, data storage and reading devices are rapidly increasing in capacity in response to the multimedia implementation of the system, and are being developed to enable high-speed data access. One example of such a data storage and reading device is a hard disk drive (HDD). The HDD is widely used as an auxiliary memory device of a computer system due to the advantage of enabling high-speed data access and high capacity.

FIG. 1 is a block diagram of a typical HDD block, which shows an HDD block structure using two disks as an example. In FIG. 1 disk 2 is rotated by spindle motor 52. Head 4 is located on the surface of disk 2 and is installed in front of the vertically extending arm of arm assembly 7 of actuator 6. The preamplifier 22 preamplifies the signal picked up by the head 2 when data is read, and drives the head 4 to write the encoded write data applied from the read / write channel circuit 24 to the disc 2 during data writing. Record it. The read / write channel circuit 24 detects and decodes a data pulse from a read signal applied from the preamplifier 22 and applies the read / write channel circuit 24 to the DDC 54, and codes the write data applied from the DDC 54. Apply to preamplifier 22. The DDC 54 interfaces the communication between the host computer and the microcontroller 40 and between the host computer and the read / write channel circuit 24. The microcontroller 40 controls track search and track following in response to a read or write command received from the host computer. The VCM (Voice Coil Motor) drive unit 44 receives the value of the servo control (position control of the head) of the microcontroller 40 through the D / A converter 42 and generates a driving current to drive the actuator 6 and applies it to the VCM of the actuator 6. do. The actuator 6 moves the heads 4 in the radiation direction on the disk 2 in response to the direction and level of the drive current applied from the VCM driver 44. The motor controller 48 applies a control value for controlling the rotation of the disk 2 to the spindle motor driver 50 under the control of the microcontroller 40, and the spindle motor driver 50 drives the spindle motor 52 to rotate the disks 2 according to the control value. The A / D converter 36 digitally converts a position error signal PES based on the burst signal among the servo information applied through the read / write channel circuit 24 and outputs it to the microcontroller 40. The gate array 38 generates various timing signals necessary for read / write and decodes the servo information and applies it to the microcontroller 40.

Among the many signals provided in the DDC 54 of FIG. 1, the QWG QWG is basically output for write verify when a problem occurs during operation. When the guaranteed light gate signal QWG is output from the DDC 54, the write disable bit in the decoder control register should be inactive. The write enable bit is in an inactive state as follows. Firstly, the missing STM latch is inactive, secondly the shock input latch is inactive, and thirdly the write unsefe signal is not set. If not.

The operation for guaranteeing the light gate may effectively guarantee the write operation when the operation is performed after the system power is turned on. However, in the situation where the system power is on, only the operation for the light gate guarantee cannot completely guarantee the write operation.

Therefore, it is required to ensure stable light operation even when the system power is turned on.

Accordingly, an object of the present invention is to provide a light malfunction preventing circuit that can guarantee the light operation even in a situation in which the system power is turned on and after that.

According to the above object, the present invention, in the circuit for preventing the recording malfunction in the hard disk drive, in the disk controller for data interface between the host and the disk guarantees to output for write verification in case of a problem in the operation of the disk controller And a logic gate for outputting a read / write mode signal for creating a read and write mode section by logically gating the write gate signal and a power reset signal related to power on / off.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

According to an embodiment of the present invention, a power reset signal related to power on / off as well as the guaranteed light gate signal QWG output for write verification in case of a problem during operation of the DDC 54 of FIG. Combination ensures write operation even in a situation where the system power is turned on and beyond. For this operation, an embodiment of the present invention includes a logic gate as shown in FIGS. 2 and 3.

2 and 3 are diagrams illustrating logic gates for preventing light malfunction according to an exemplary embodiment of the present invention. 4 is a waveform diagram showing that the stable light mode operation is performed by the write malfunction prevention circuit according to FIGS. 2 and 3.

First, the logic gate for preventing the light malfunction shown in FIG. 2 receives the guarantee light gate signal QWG at one input terminal and the power reset signal at the type force stage. It consists of NAND gate 60 that receives the input. The output of the NAND gate 60 is a read / write mode signal R / indicating a read and write mode state. to be.

Next, the logic gate for preventing the light malfunction shown in FIG. 3 receives the guaranteed light gate signal QWG through an input terminal D and the power reset signal to a clear terminal R. Referring to FIG. Is inputted and the power supply voltage Vcc is applied to the preset stage (P) and the reverse output stage ( ) The read / write mode signal R / It consists of a D flip-flop 70. The clock signal CLK of 40 MHz is applied to the clock terminal CLK of the D-type flip-flop 70.

In order to prevent write malfunction, the NAND gate 60 shown in FIG. 2 and the D flip-flop 70 shown in FIG. 3 are guaranteed light gate signals QWG and the power reset signal. All of these are in the enable mode (binary logic "high" state according to Figure 4) lead / write mode signal R / Outputs The power reset signal When binary logic of "high", it means the state that power is applied. Lead / right mode signal R / in light mode Is a binary logic " low " state as shown in FIG.

Table 1 shows the guarantee light gate signal QWG and the power reset signal. The read / write mode signal R / outputted from the NAND gate 60 of FIG. 2 and the D flip-flop 70 of FIG. Binary state of.

TABLE 1

As shown in Table 1 and FIG. 4 showing the signal waveforms of Table 1, the power reset signal even when the guarantee light gate signal QWG is enabled In this power reset state (binary logic "low"), the read / write mode signal R / Is a binary logic " high " state, which prevents write enable. The write enable is performed by the guarantee light gate signal QWG and the power reset signal as shown in FIG. All of this is done in the interval of binary logic logic "high".

As described above, the present invention provides a power reset signal related to power on / off as well as a guaranteed light gate signal QWG output for light verification when a problem occurs during operation of the controller. In combination with, the write operation is guaranteed based on the state of the guarantee light gate signal after the system power is applied without the write enable in the section where the system power is reset. As a result, there is an advantage of ensuring stable write operation in the HDD.

1 is a block diagram of a typical HDD block;

2 and 3 is a logic gate configuration for preventing the light malfunction according to an embodiment of the present invention,

4 is a waveform diagram showing that the stable light mode operation is performed by the light malfunction prevention circuit according to FIGS. 2 and 3.

Claims (4)

In a circuit for preventing a recording malfunction in a hard disk drive, In the disk controller for the data interface between the host and the disk, when the disk controller is in operation, the write and write mode sections are executed by a predetermined logic gate between the guaranteed light gate signal output for write verification and the power reset signal related to power on / off. And a logic gate for outputting a read / write mode signal. The circuit of claim 1, wherein the logic gate outputs the read / write mode signal as a write mode state when both the guarantee light gate signal and the power reset signal are enabled. The circuit of claim 2, wherein the logic gate is a NAND gate which receives the guarantee light gate signal through one input terminal and receives the power reset signal through a type force terminal. 3. The logic gate of claim 2, wherein the logic gate receives the guarantee light gate signal as an input terminal, receives the power reset signal as a clear stage, receives a power voltage to a preset stage, and outputs the read / write mode signal to an inverted output stage. A circuit characterized in that the flip-flop.