KR100564763B1 - Digital audio broadcasting receiver and method for controlling the same - Google Patents

Abstract

The present invention discloses a digital audio broadcast receiver and a control method thereof. The disclosed invention additionally inserts and transmits length information of CRC-applied data in a specific bit field of a DAB audio frame header in an audio encoder of a DAB transmitter. In addition, an audio decoder controller is provided between the Viterbi decoder and the audio decoder of the DAB receiver to control the audio decoding process using the transmitted additional information. Therefore, the CRB check is performed in the DAB receiver stage before the audio decoder process, thereby preventing unnecessary decoding of the audio decoder. That is, it is possible to selectively control the process of storing all the output bits of the Viterbi decoder in the audio data input buffer, and to prevent unnecessary decoding of the audio decoder, thereby reducing the computational burden of the audio decoder, Furthermore, the power consumption of the DAB receiver is reduced.

Digital audio broadcasting, audio decoder, cyclic redundancy code (CRC)

Description

Digital audio broadcasting receiver and method for controlling the same

1 is a block diagram schematically illustrating a general digital audio broadcasting receiver.

2 is a block diagram illustrating a digital audio broadcast receiver according to the present invention.

3 is a block diagram illustrating an audio decoder controller of FIG. 2.

4 is a diagram illustrating an audio frame structure of digital audio broadcasting according to the present invention.

5 is a diagram illustrating a CRC generator of the present invention.

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a digital audio broadcasting (DAB) receiver, and more particularly, to a DAB receiver capable of reducing the computational burden of an audio decoder.

An audio decoder of a general DAB receiver reads audio bit stream data received in an audio data input buffer and extracts header information. In addition, the audio decoder decodes the information on the number of bits allocated to each sub band and the scale factor of each sub band based on the header information described above, thereby decoding the frequency band. Create a sample of. The frequency band samples thus generated are finally output in the form of pulse code modulation (PCM) samples in the time domain through a synthesis filter while performing inverse quantization and inverse normalization.

1 is a block diagram illustrating an audio decoding process of a general DAB receiver.

The DAB receiver 10 has a radio frequency (RF) front-end (11), an analog-to-digital converter (ADC: 12), a digital front-end 13, mode and synchronization, as shown in FIG. Detector 14, fast Fourier transformer 15, differential quadrature phase shift keying, DQPSK demodulator 160, deinterleaver 170, viterbi decoder 180 and audio decoder 190 It includes.

The general driving of the DAB receiver 10 having such a configuration is as follows.

The signal received from the antenna is converted into a digital signal by the analog-to-digital converter 12 and then separated into a base band I / Q signal in the mode and sync detector 14. The separated signal is demodulated by the fast Fourier transformer 15 and the differential demodulator 16, and the demodulated signal is deinterleaved by the deinterleaver 17. The signal is then restored to an audio signal by the DAB audio decoder 19 after performing the channel decoding process by the Viterbi decoder 18.

In the conventional DAB receiver, a substantial audio decoding process is performed in which the output bits of the Viterbi decoder 18 are stored in an audio data input buffer (not shown) in the audio decoder 19, and then the bit allocation information and the SCFSI information are decoded. Is performed. That is, in the conventional DAB receiver, after data, such as bit allocation information and size factor selection information, is input and decoded to the audio decoder 19, a CRC check is performed.

However, since the CRC check is performed after data is input to the audio decoder, the conventional DAB receiver checks whether the audio bitstream is valid in the process of performing the actual audio decoding process after the data is input to the audio decoder. do. Therefore, if the audio bitstream is invalid, an unnecessary audio decoding operation must be performed. This increases the computational burden on the audio decoder and increases the power consumption of the DAB receiver.

Accordingly, an object of the present invention is to provide a DAB receiver capable of reducing the computational burden and power consumption of an audio decoder of a DAB receiver.

Another object of the present invention is to provide a control method of the DAB receiver.

In order to achieve the above technical problem, the DAB receiver of the present invention, a converter for converting an analog signal input from the antenna into a digital signal, a mode and sync detector for separating the digital signal into an I / Q signal, A fast Fourier transformer and a differential demodulator for demodulating the separated signal, a deinterleaver for deinterleaving the demodulated signal, a Viterbi decoder for channel decoding the deinterleaved signal, and restoring the decoded signal to an audio signal And an audio decoder configured to accumulate a shift register for converting the bit stream data output from the Viterbi decoder into parallel data between the Viterbi decoder and the audio decoder, and accumulating an input in units of bits of the shift register to check CRC. By setting a range and CRC checking the bitwise data of the range, And an audio decoder controller for outputting a control signal to the audio decoder.

The audio decoder controller is configured to: input a bitwise output of the shift register, generate a 16-bit CRC word, a CRC buffer to store the generated 16-bit CRC word in a DAB audio frame header, and receive 16 bits A CRC comparator for comparing the CRC word with the generated CRC word to generate an audio decoder control signal, and a counter unit for accumulating the bit unit input of the shift register to control the CRC generator, the CRC buffer, and the CRC comparator.

The CRC buffer stores, according to the control signal of the counter unit, 16 bits from the 33rd bit of the shift register as parallel data in the CRC buffer.

The CRC comparator compares the 16-bit CRC word received by the control signal of the counter with the 16-bit CRC word generated from the bitstream data to which the CRC is applied to control whether the audio decoder operates normally.

In addition, according to another aspect of the present invention, a method of controlling a DAB receiver includes a method of controlling a bit string to which a fixed bit field and an unused bit field of a audio frame header are applied to a digital audio broadcasting (DAB) transmitter. Insert length information to control the audio decoder.

(Example)

Hereinafter, preferred embodiments of the present invention will be described with reference to the accompanying drawings. However, embodiments of the present invention may be modified in many different forms, and the scope of the present invention should not be construed as being limited by the embodiments described below. Embodiments of the present invention are provided to more completely explain the present invention to those skilled in the art. Accordingly, the shape and the like of the elements in the drawings are exaggerated to emphasize a more clear description, and the elements denoted by the same reference numerals in the drawings means the same elements.

2 is a block diagram illustrating a DAB receiver according to the present invention.

The DAB receiver 100 has a radio frequency (RF) front-end (110), an analog to digital converter (ADC: 120), a digital front-end 130, mode and synchronization, as shown in FIG. Detector 140, fast Fourier transformer 150, differential quadrature phase shift keying (DQPSK) demodulator 160, deinterleaver 170, Viterbi decoder 180 and audio decoder 190. . In addition, a shift register 210 and an audio decoder controller 220 may be provided between the Viterbi decoder 180 and the audio decoder 190 to reduce power consumption while reducing the computational burden on the audio decoder. The shift register 210 and the audio decoder controller 220 are interposed to allow the CRC check to proceed before the data signal is input to the audio decoder 190.

General driving of the DAB receiver 100 having such a configuration is as follows.

The signal received from the antenna is converted into a digital signal by the analog-to-digital converter 120, and then separated by the mode and sync detector 140 into an I / Q signal of the baseband. A signal separated into an I / Q signal is input to the fast Fourier transformer 150 and the differential demodulator 160 to generate a demodulated signal, which is again deinterleaved while passing through the deinterleaver 170. Thereafter, after the channel decoding process is performed by the Viterbi decoder 180, the DAB audio decoder 190 restores the audio signal.

In this case, the output of the Viterbi decoder 180 is converted into parallel data by the shift register 210, and the parallel data is stored in the audio data input buffer 230 of the audio decoder 190. In addition, the audio decoder controller 220 determines the validity of the audio bitstream data received before the decoding process of the audio decoder 190 and outputs a control signal to the audio decoder 190. The audio decoder controller 220 accumulates the bit unit input of the shift register to set the CRC check range, and then outputs a signal for controlling the audio decoder 190 by CRC check on the bit unit data of the range. .

Here, the audio decoder controller 220 will be described in more detail. As shown in FIG. 3, the audio decoder controller 220 includes a counter 310, a CRC generator 320, a CRC buffer 330, and a CRC comparator. It consists of 34.

The CRC generator 320 generates a 16-bit CRC word by using the bitwise output of the shift register 210 as an input. CRC buffer 330 stores the 16-bit CRC word transmitted in the received DAB audio frame. The CRC comparator 340 compares the received 16-bit CRC word with the generated CRC word to generate an audio decoder control signal. The counter 310 accumulates the bitwise input of the shift register 210 to control the CRC generator, the CRC buffer, and the CRC comparator.

Here, the DAB audio frame header structure is shown in FIG. 4.

As shown in FIG. 4, the DAB audio frame includes a header, a cyclic redundancy code (CRC), bit allocation information, scale factor selection indicator (SCFSI), a scale factor, and a sub. Subband samples, stuff, n bytes extended program associated data (X-PAD), scale factor cyclic redundancy code (SCFCRC), and 2 bytes fixed PAD (F-PAD) are disposed in succession.

In addition, the header includes a sync field (syncword: 12 bits), an identifier field (ID: 1 bit), a layer field (layer 2 bits), a protection bit field (1 bit), and a bitrate index field (bitrate index: 4). Bit), sampling frequency field (2 bits), padding bit field (1 bit), private bit field (1 bit), mode bit field (2 bits), mode extended field (mode ext .: 2 bits), copy It is composed of a light field (copyright: 2 bits) and an emphasis field (2 bits), a total of 32 bits.

In this case, the CRC is applied from the third and fourth bytes of the 32-bit header to bit allocation information and scale factor selection indicator (SCFSI).

Here, the hierarchical field of the DAB audio frame header field is always fixed to "10 (binary number)", and the protection bit field is limited to "0". Also, since the decoding algorithm to be used for decoding the audio data is already determined by the identifier (ID) field, the sampling frequency field is always fixed to a value of "01". In addition, since the sampling frequency uses only 24 kHz and 48 kHz, the padding bit field value is also fixed to "0".

On the other hand, since the DAB audio decoder does not use de-emphasis, the emphasis field is also fixed to a value of "00", and the private field is not used. Accordingly, additional information may be allocated to the fixed bit field and the unused bit field as described above.

The audio encoder stage of the DAB transmitter inserts data length information to which the CRC is applied as 9-bit additional information into the DAB audio frame header. Then, when the CRC word generated by the CRC generator 320 is added to the audio bitstream and transmitted, the audio decoder 190 of the DAB receiver transmits the third and fourth bytes and bits of the DAB audio frame header based on this information. CRC check is performed on the allocation information and the size factor selection information. Accordingly, the validity of the received audio bit stream data is determined. That is, the data length information to which the CRC is applied is transmitted to a fixed bit and an unused bit area of a DAB audio frame, thereby performing a CRC check.

At this time, the CRC generator 320 of FIG. 3 generates a CRC word by updating the CRC word starting from the third byte of the DAB audio frame header to bit allocation information and size factor selection information. Further, at the start of operation of the CRC generator 320, the initial state is set to " 1111111111111111 ", and the generating polynomial and the detailed structure are described in detail in FIG. CRC buffer 330 also stores the received 16-bit CRC word located after the DAB audio frame header, i.e., in the 33rd bit. In addition, the received CRC word and the generated 16-bit CRC word are compared by the CRC comparator 340, and the audio decoder 190 is controlled according to the CRC check result. The above process is controlled by the counter unit 310 in the audio decoder controller 220.

If an error is detected as a result of the CRC check, an appropriate error concealment processing method such as playing or muting an audio sample of the previous frame without error without proceeding with the normal decoding process of the audio decoder 190 is performed. Apply.

As described above in detail, the present invention additionally inserts and transmits length information of data to which a CRC is applied in a specific bit field of a DAB audio frame header in an audio encoder of a DAB transmitter. In addition, an audio decoder controller is provided between the Viterbi decoder and the audio decoder of the DAB receiver to control the audio decoding process using the transmitted additional information. Therefore, the CRB check is performed in the DAB receiver stage before the audio decoder process, thereby preventing unnecessary decoding of the audio decoder.                     

That is, it is possible to selectively control the process of storing all the output bits of the Viterbi decoder in the audio data input buffer, and to prevent unnecessary decoding of the audio decoder, thereby reducing the computational burden of the audio decoder, Furthermore, the power consumption of the DAB receiver is reduced.

Although the present invention has been described in detail with reference to preferred embodiments, the present invention is not limited to the above embodiments, and various modifications may be made by those skilled in the art within the scope of the technical idea of the present invention. .

Claims (5)

A converter for converting an analog signal input from an antenna into a digital signal; A mode and sync detector for separating the digital signal into an I / Q signal; A fast Fourier transformer and a differential demodulator for demodulating the separated signal; A deinterleaver for deinterleaving the demodulated signal; A Viterbi decoder for channel decoding the deinterleaved signal; And An audio decoder for restoring the decoded signal to an audio signal: A shift register for converting bit stream data output from the Viterbi decoder into parallel data between the Viterbi decoder and the audio decoder; And an audio decoder controller configured to set a CRC check range by accumulating a bit unit input of the shift register, CRC check a bit unit data of a corresponding range, and output a control signal to the audio decoder. . The method of claim 1, wherein the audio decoder controller, A CRC generator for generating a 16-bit CRC word by inputting a bit-by-bit output of the shift register; A CRC buffer for storing the generated 16-bit CRC word in a DAB audio frame header, A CRC comparator for generating an audio decoder control signal by comparing the received 16-bit CRC word with the generated CRC word, and And a counter unit for accumulating a bit unit input of the shift register to control a CRC generator, a CRC buffer, and a CRC comparator. The method of claim 2, wherein the CRC buffer, And a CRC word having 16-bit parallel data received from the 33rd bit of the shift register according to the control signal of the counter unit. The method of claim 2, wherein the CRC comparator, And comparing the 16-bit CRC word received by the control signal of the counter with the 16-bit CRC word generated from the bitstream data to which the CRC is applied to control whether or not the audio decoder operates normally. Between the digital audio broadcasting (DAB) audio frame header having a fixed bit field and an unused bit field, the length information of a bit string to which a cyclic redundancy code (CRC) is applied is inserted so that the fixed bit field and the unused bit field are not used. A method of controlling a DAB receiver, wherein the audio decoder is controlled by assigning additional information to a bit field.

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