KR100560815B1 - Heterogeneous semiconductor substrate and method for forming the same - Google Patents

Abstract

The release semiconductor substrate disclosed herein includes a silicon substrate, a silicon-germanium epitaxial pattern formed on the silicon substrate, and a top planar silicon epitaxy formed on the silicon substrate and the silicon-germanium epitaxial substrate. It includes a seam layer. Such a release semiconductor substrate can be used as a base semiconductor substrate in various semiconductor manufacturing processes.

Epitaxial growth, semiconductor substrate, SOI, MEMS

Description

Heterogeneous semiconductor substrate and method for forming the same

1 is a perspective view schematically illustrating a release semiconductor substrate according to an exemplary embodiment of the present invention, and a portion of the release semiconductor substrate is removed to show its interior.

FIG. 2 is a perspective view schematically illustrating a release semiconductor substrate according to another exemplary embodiment of the present invention, and partially removed to show the inside thereof. FIG.

3 to 5 are cross-sectional views illustrating a method of forming a release semiconductor substrate in accordance with an embodiment of the present invention.

FIG. 6 is a cross-sectional view for describing a method of forming a release semiconductor substrate according to another exemplary embodiment of the present inventive concept.

7 through 11 are cross-sectional views illustrating an example of a method of manufacturing a semiconductor device using the release semiconductor substrate of FIG. 2.

* Explanation of symbols for the main parts of the drawings

100: release semiconductor substrate 01: first semiconductor layer

103: second semiconductor pattern 105: third semiconductor layer

107: trench 109: empty space

111: device isolation region 113: gate insulating film

115: gate electrode 17 source / drain

119: sidewall spacer

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor substrate used in a semiconductor device manufacturing process and a method for forming the same, and more particularly, to a release semiconductor substrate and a method for forming the same.

The development of solid state device technology since the invention of the transistor in 1948 depends not only on the development of device concepts but also on the development of materials. For example, it is no exaggeration to say that integrated circuit devices have been created today thanks to the breakthrough in the growth technology of pure, single-crystal silicon.

Typically, single crystal silicon substrates are widely used in the semiconductor device manufacturing process. Monocrystalline silicon ingots are formed through liquid-encapsulated Czochralski growth, a well known method, followed by mechanical processing and cutting to form single crystal silicon substrates.

However, recently, as semiconductor devices formed on a single crystal silicon substrate are continuously integrated with high performance, high speed, and economical viewpoints, various problems occur. For example, short channel effects such as punch-through that occur as the channel length of the transistor becomes shorter, increase of parasitic capacitance (junction capacitance) between the junction region and the substrate, increase leakage current, and the like. Problems are occurring. As a result, a reliable high performance, low power semiconductor device cannot be manufactured.

Efforts have been made to form a semiconductor device using a substrate of a new material to alleviate these problems. For example, a silicon-on-insulator (SOI) substrate is used in which an insulating film is placed on a silicon substrate. have. Techniques using SOI substrates have advantages such as suppressing junction leakage currents, reducing short channel effects, low operating voltages and effective device isolation. However, the semiconductor fabrication process technology using the SOI substrate has a so-called floating body effect in which heat generated during operation of the device does not escape or high energy hot carriers are accumulated. In addition, the SOI technology is unable to apply a back bias, causing a change in threshold voltage, thereby preventing a reliable device operation. In addition, the SOI substrate manufacturing process is complex and expensive.

Thus, there is a need for new semiconductor substrates to replace conventional silicon bulk substrates and SOI substrates.

Recently, micro electromechanical system (MEMS) technology, which manufactures a system that combines micro-scale mechanical and electrical structures with new functions by integrating electronic devices and mechanical parts into a microminiature. This is being actively researched. MEMS uses micro-fabrication technology to apply mechanical elements, sensors, actuators, and electronics to well-known silicon wafers to apply existing semiconductor manufacturing technology. It can be said to make.

Electronic devices are formed using conventional integrated circuit processes (eg CMOS, bipolar, BICMOS processes, etc.). Micromechanical components are formed through micromachining processes. Micromachining is the process of selectively etching a portion of a silicon wafer or forming a new structure to make a mechanical or electromechanical element. MEMS enables all structures to be fabricated on silicon wafers using micromachining technology, enabling the realization of systems-on-a-chip that allows the system to be fabricated on one chip.

Substrates of new materials or structures are required to apply new technologies that differ from traditional semiconductor manufacturing processes such as MEMS technology.

In view of the above, the present invention has been proposed, and a technical object of the present invention is to provide a new type of semiconductor substrate and a method for forming the same, which can be applied to various device manufacturing techniques as well as a conventional semiconductor manufacturing process.

In order to achieve the above technical problem, embodiments of the present invention provide a heterogeneous semiconductor substrate.

The release semiconductor substrate according to the embodiment of the present invention is composed of stacked semiconductor layers. The top surface of the top layer of the stacked semiconductor layers is flat. The release semiconductor substrate includes a first semiconductor layer, a second semiconductor pattern formed on the first semiconductor layer, and a third semiconductor layer formed on the first semiconductor layer and the second semiconductor pattern and having a flat upper surface. . The first semiconductor layer, the second semiconductor layer, and the third semiconductor layer are composed of Group 4 elements on the periodic table of elements such as silicon and germanium or their crystalline compounds such as silicon-germanium. Preferably, the first semiconductor layer and the third semiconductor layer are the same material, and the second semiconductor layer is a material having an electrochemical property different from that of the first semiconductor layer and the third semiconductor layer. Here, different electrochemical properties may include, for example, different carrier mobility or different etching rates for a particular etchant (only one layer is etched and the other is hardly etched). it means.

For example, the release semiconductor substrate may include a silicon substrate / silicon-germanium pattern / silicon layer, a silicon substrate / germanium pattern / silicon layer, a silicon-germanium substrate / silicon pattern / silicon-germanium layer, a silicon-germanium substrate / germanium pattern that are sequentially stacked / Silicon-germanium layer, germanium substrate / silicon pattern / germanium layer and the like. But what is listed here is merely illustrative.

Preferably, the release semiconductor substrate may be a silicon substrate formed by a conventional method, a silicon-germanium epitaxial pattern formed on the silicon substrate, and a flat top formed on the silicon substrate and the silicon-germanium epitaxial pattern. It may be composed of a silicon epitaxial layer. As a result, the release semiconductor substrate of the present invention is a single crystal silicon substrate having a silicon-germanium epitaxial pattern therein. Here, if the silicon-germanium pattern is a relaxed silicon-germanium pattern, the silicon epitaxial layer is strained silicon and thus may increase the mobility of carriers. .

Such silicon-germanium epitaxial patterns may remain in various shapes, be removed, or be removed and then replaced by other materials during the semiconductor manufacturing process, thus providing various functions suitable for device characteristics. There will be.

For example, when the release semiconductor substrate of the present invention is used in a conventional semiconductor device manufacturing process, problems such as floating body effects of SOI technology can be solved. When a channel and a source / drain for a transistor are formed in the epitaxial silicon layer, the epitaxial silicon layer (third semiconductor layer) and the silicon substrate (first semiconductor layer) are connected to each other, so that the floating body The effect and the accumulation of hot electrons are solved. In addition, a back bias can be applied through the first semiconductor layer, so that the potentials of the source (or drain) regions can be kept the same throughout the wafer, thereby maintaining a constant threshold voltage of the transistor. In addition, when the silicon-germanium epitaxial pattern (second semiconductor layer) is located under the source / drain region and is removed during the fabrication process, it is possible to minimize the junction leakage current between the source / drain and the substrate, The depth can be easily adjusted.

The release semiconductor substrate of the present invention is formed through an epitaxial growth technique. That is, an epitaxial layer is formed on the first semiconductor layer through epitaxial growth, and then patterned to form the second semiconductor pattern. The third semiconductor layer having a flat top surface is formed on the first semiconductor layer and the second semiconductor pattern through epitaxial growth. The third semiconductor layer having the flat top is formed through this step process.

In example embodiments, the upper surface of the third semiconductor layer may be epitaxially grown at a first temperature to form a first epitaxial layer covering the second semiconductor pattern and then higher than the first temperature. It can be formed by proceeding epitaxial growth at a second temperature to form a secondary epitaxial layer having a flat top. For example, the first temperature ranges from about 300 degrees Celsius to about 800 degrees Celsius, and the second temperature ranges from about 600 degrees Celsius to about 1200 degrees Celsius. Since the primary epitaxial layer grows at low temperatures in the range of about 300 degrees Celsius to about 800 degrees Celsius, it has an upper surface to which the surface shape by the first and second semiconductor patterns below is transferred. On the other hand, since the secondary epitaxy layer grows at a high temperature in the range of about 600 degrees Celsius to about 1200 degrees Celsius, the movement of the primary epitaxy layer occurs during epitaxial growth, and the second epitaxial layer is formed on the upper portion thereof. The axial layer grows and thus the secondary epitaxial layer has a flat top surface. On the other hand, since the second semiconductor pattern is covered and protected by the first epitaxial layer, the second semiconductor pattern does not move during the second epitaxial growth and maintains its original shape.

Alternatively, the third semiconductor layer having the flat top may be epitaxially grown at a first temperature to form an epitaxial layer covering the second semiconductor pattern, and then heat-treated at a second temperature higher than the first temperature. It can be formed by flattening the upper portion of the epitaxial layer. The heat treatment may be performed in a hydrogen gas atmosphere or an argon gas atmosphere. For example, the first temperature ranges from about 300 degrees Celsius to about 800 degrees Celsius, and when the heat treatment is performed in a hydrogen gas atmosphere, the second temperature ranges from about 600 degrees Celsius to about 1200 degrees Celsius. On the other hand, when the heat treatment is performed in an argon gas atmosphere, the second temperature has a temperature range of about 900 degrees Celsius to about 1200 degrees Celsius. Since the epitaxial layer grows at a low temperature in the range of about 300 degrees Celsius to about 800 degrees Celsius, the epitaxial layer has an upper surface on which the surface shape by the first and second semiconductor patterns below is transferred. On the other hand, since the heat treatment grows at a high temperature in the range of about 600 degrees Celsius to about 1200 degrees Celsius or about 900 degrees Celsius to about 1200 degrees Celsius, atomic migration occurs at the upper surface of the epitaxial layer and thus the epitaxy layer Will have a flat top surface.

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings. However, the present invention is not limited to the embodiments described herein and may be embodied in other forms. Rather, the embodiments introduced herein are provided so that the disclosure may be made thorough and complete, and to fully convey the spirit of the present invention to those skilled in the art. In the drawings, the thicknesses of layers and regions are exaggerated for clarity. In addition, where a layer is said to be "on" another layer or substrate, it may be formed directly on the other layer or substrate, or a third layer may be interposed therebetween. Like numbers refer to like elements throughout.

The present invention relates to a semiconductor substrate, and provides a heterogeneous semiconductor substrate composed of several layers of semiconductor layers having different electrochemical properties. Various active or passive electrical and electronic devices are formed on the release semiconductor substrate of the present invention. The semiconductor substrates thus far have been SOI substrates in which silicon is present on bulk silicon or an insulating film.

A release semiconductor substrate according to an embodiment of the present invention is composed of three semiconductor layers, and a second semiconductor layer interposed therebetween is composed of a plurality of semiconductor patterns having a predetermined pattern. Also the second semiconductor layer is above it. The electrochemical properties are different from those of the third semiconductor layer and the first semiconductor layer which exist below. Here, the surface of the release semiconductor substrate on which the various electric and electronic elements are formed is flat.

1 shows a release semiconductor substrate of such a structure. Referring to FIG. 1, a release semiconductor substrate 100 according to an embodiment of the present invention may include a first semiconductor layer 101, a second semiconductor pattern 103 formed on the first semiconductor layer 101, and the And a third semiconductor layer 105 formed on the first semiconductor layer 101 to cover the second semiconductor patterns 103. That is, the third semiconductor layer 105 and the first semiconductor layer 101 contact each other except for a region occupied by the second semiconductor patterns 103. The upper surface of the third semiconductor layer 105 is flat.

Various semiconductor devices are formed on the flat surface of the third semiconductor layer 105. For example, when a field effect transistor is formed on the third semiconductor layer 105, the third semiconductor layer 105 provides a channel region and a source / drain region for the field effect transistor. Meanwhile, the second semiconductor pattern 103 may be exposed and selectively removed during the semiconductor device manufacturing process, and an insulating material may be formed at the removed location. In this case, unlike the conventional SOI substrate, according to the present invention, the third semiconductor layer 105 is connected to the first semiconductor layer 101 so that problems such as floating body effects do not occur.

The first semiconductor layer 101, the second semiconductor patterns 103, and the third semiconductor layer 105 are made of a Group 4 element on the periodic table of elements or a crystalline compound thereof. For example, the first semiconductor layer 101 is a bulk silicon substrate manufactured by a conventional method, and the second semiconductor pattern 103 is a silicon-germanium epi formed on the silicon substrate by an epitaxial growth technique. And the third semiconductor layer 105 is a silicon epitaxial layer formed by an epitaxial growth technique on the silicon substrate and the silicon-germanium epitaxial patterns.

In addition, the release semiconductor substrate 100 may include a silicon substrate / silicon-germanium pattern / silicon layer, a silicon substrate / germanium pattern / silicon layer, a silicon-germanium substrate / silicon pattern / silicon-germanium layer, and a silicon-germanium substrate that are sequentially stacked. / Germanium pattern / silicon-germanium layer, germanium substrate / silicon pattern / germanium layer, and the like. However, these are merely exemplary and the present invention is not limited thereto.

The second semiconductor pattern 103 may have various shapes to suit the electrical and electronic device to be manufactured. Although the second semiconductor pattern 103 has a quadrangular shape in FIG. 1, it may have a line shape as shown in FIG. 2.

Hereinafter, a method of manufacturing the above-described release semiconductor substrate will be described with reference to FIGS. 3 to 7. First, referring to FIG. 3, a silicon-germanium epitaxial layer 103a is formed on the bulk silicon substrate 101 using an epitaxial growth technique. Epitaxial growth techniques use methods such as vapor-phase epitaxy, molecular-beam epitaxy, chemical vapor deposition (CVD), sputtering and the like, and SiH as source gas. ₄ , GeH ₄ gas is used. For example, when the silicon-germanium epitaxial layer is formed by the epitaxial growth method by CVD, the reaction temperature ranges from about 400 degrees Celsius to about 1000 degrees Celsius.

The silicon-germanium epitaxial layer 103a grows evenly over the entire surface of the bulk silicon substrate 101.

Next, photolithography is performed on the silicon-germanium epitaxial layer 103a to form a silicon-germanium epitaxial pattern 103 having a predetermined shape. As a result, a portion 104 of the bulk silicon substrate 101 is exposed. The silicon-germanium epitaxial pattern 103 has a side surface, an upper surface, and a bottom surface in contact with the bulk silicon substrate 101. Here, the silicon germanium epitaxial pattern 103 may have various shapes.

Referring next to FIG. 5, a primary silicon epitaxial layer 105a is formed on a portion 104 of the exposed bulk silicon substrate 101 and on the side and top surfaces of the silicon-germanium epitaxial pattern 103. Is grown using epitaxial growth techniques. In this case, the primary silicon epitaxial growth is performed at a temperature (low temperature) in which the shape of the silicon-germanium pattern 103 is maintained without being distorted. If the process temperature is too high, the silicon-germanium element of the silicon-germanium pattern 103 may be displaced and the shape of the pattern may be distorted. This is presumably because the silicon-germanium pattern is trying to be more stable at high temperature, that is, the surface is flat.

 Therefore, when primary silicon epitaxial growth proceeds at low temperature, the silicon single germanium pattern is evenly distributed on the side and the top surface of the silicon-germanium epitaxial pattern and a portion of the bulk silicon substrate to which the silicon single crystal is exposed. Done. Accordingly, the upper surface of the primary silicon epitaxial layer 105a to be formed has a surface shape (ie, the surface shape due to the bulk silicon substrate and the silicon-germanium epitaxial pattern) due to the underlying film quality. To bend and to bend.

The temperature of the primary silicon epitaxial growth is, for example, in the range of about 300 degrees Celsius to about 800 degrees Celsius. During the silicon epitaxial growth at such low temperatures, no distortion of the germanium-epitaxial pattern occurs.

Next, a silicon epitaxial layer 105 having a flat upper surface by planarizing the curved first silicon epitaxial layer 105a by performing a heat treatment process in a hydrogen gas atmosphere or an argon gas atmosphere with reference to FIG. 6. ). At this time, the temperature of the heat treatment process is the temperature (high temperature) at which the movement of the silicon elements constituting the primary silicon epitaxial layer 105a occurs and thus the surface of the primary silicon epitaxial layer 105a in the heat treatment process. The movement will take place. The movement of elemental silicon is probably due to the formation of silane (Si + 2H _2- > SiH ₄ ) and decomposition of the formed silane (SiH ₄ ) by the bonding of hydrogen gas and silicon of the primary silicon epitaxial layer during hydrogen atmosphere heat treatment. -> Si + 2H ₂ ) is constantly issued and it is assumed that the silicon element of the primary silicon epitaxial layer moves. It is also speculated that the silicon epitaxial layer is stable at a high temperature, that is, a property that the surface which is stable rather than the curved surface becomes flat. At this time, since the silicon-germanium pattern is already protected by the primary silicon epitaxial layer, elemental movement on the surface does not occur.

The temperature of the heat treatment process in a hydrogen gas atmosphere is, for example, in the range of about 600 degrees Celsius to about 1200 degrees Celsius. The temperature of the heat treatment process in an argon gas atmosphere is, for example, in the range of about 900 degrees Celsius to about 1200 degrees Celsius. The lower limit temperature of the heat treatment in the hydrogen atmosphere is lower than the heat treatment in the argon atmosphere because the hydrogen gas acts on the surface planarization as described above in the case of the heat treatment in the high temperature atmosphere and possibly the hydrogen atmosphere.

That is, according to this embodiment, an epitaxial layer having a flat top is formed on the curved lower surface through epitaxial growth at low temperature and heat treatment at high temperature.

Alternatively, after growing the primary silicon epitaxial layer 105a at a low temperature in FIG. 5, an additional secondary silicon epitaxial growth is performed to show a secondary epitaxial surface having a flat surface as shown in FIG. A tactile silicon layer 105 is formed. At this time, the secondary silicon epitaxial growth is performed at a temperature (high temperature) in which the shape of the primary epitaxial silicon layer 105a is distorted. If the process temperature is high, the silicon element of the primary silicon epitaxial layer 105a having the curved upper surface is moved, and the surface is gradually planarized, so that silicon growth occurs. Accordingly, the upper surface of the secondary silicon epitaxial layer 105 is flat. On the other hand, since the silicon-germanium epitaxial pattern 103 is already covered and protected by the primary silicon epitaxial layer 105a, the shape of the pattern is not distorted in the second silicon epitaxial growth. . For example, the temperature of secondary silicon epitaxial growth is, for example, in the range of about 600 degrees Celsius to about 1200 degrees Celsius.

An embodiment of forming a semiconductor device on a release semiconductor substrate formed by the above-described method will now be described with reference to FIGS. 8 to 11. 8 shows a release semiconductor substrate 100 formed by the method described above. Referring to FIG. 8, the release semiconductor substrate 100 includes a bulk silicon substrate 101, a silicon-germanium pattern 103, and a silicon epitaxial layer 105. The silicon-germanium pattern 103 is in the form of a line.

After the release semiconductor substrate 100 is prepared, an element isolation process is performed. Referring to FIG. 9, a portion of the release semiconductor substrate 100 is etched to form a trench 107 for device isolation. Here, the silicon epitaxial 105, the silicon-germanium epitaxial pattern 103, and a portion of the bulk silicon substrate are etched. Although not shown in the drawings, an etching mask defining an active region is formed on the silicon epitaxial layer, and then the exposed release semiconductor substrate 100 is etched using the etching mask.

Next, referring to FIG. 10, the exposed silicon-germanium epitaxial pattern is selectively removed. Accordingly, an empty space 109 is formed where the silicon-germanium epitaxial pattern 103 is removed. The empty space 109 may be connected to the trench 107 to be an isolation region.

Next, the device isolation region 111 is formed by filling the trench 107 with an insulating material with reference to FIG. 11. In this case, the empty space 109 may also be filled with an insulating material. According to the process, a thermal oxidation process may be performed before the trench 107 is filled with an insulating material, and a silicon nitride film, which is an antioxidant film, may be formed.

Subsequently, referring to FIG. 11, after the isolation region 111 is formed, the gate oxide film 113 is formed and the gate electrode 115 is formed. The gate electrode 115 is formed between the empty spaces 109. That is, the silicon epitaxial layer of the gate electrode 115 acts as a channel region and is connected to the bulk silicon substrate 101 to prevent the floating body effect of the conventional SOI substrate.

After forming the gate electrode 115, an ion implantation process is performed to form source / drain regions 117 on the silicon epitaxial layers on both sides of the gate electrode 115. In this case, the empty space 109 is located under the silicon epitaxial layer on both sides of the gate electrode. Thus, punchthrough is suppressed and the junction parasitic capacity is reduced. Subsequently, an insulating film space 119 is formed on both side walls of the gate electrode 115.

The gate electrode 115 may be formed on the empty space 109. In this case, the source / drain regions and the bulk silicon substrate are connected to each other.

The foregoing detailed description illustrates and describes the present invention. In addition, the foregoing description merely shows and describes preferred embodiments of the present invention, and as described above, the present invention can be used in various other combinations, modifications, and environments, and the scope of the concept of the invention disclosed in the present specification and writing Changes or modifications may be made within the scope equivalent to the disclosure and / or within the skill or knowledge of the art. The above-described embodiments are for explaining the best state in carrying out the present invention, the use of other inventions such as the present invention in other state known in the art, and the specific fields of application and uses of the present invention. Various changes are also possible. Accordingly, the detailed description of the invention is not intended to limit the invention to the disclosed embodiments. Also, the appended claims should be construed to include other embodiments.

The release semiconductor substrates of the present invention do not have the disadvantages of conventional bulk silicon substrates or SOI substrates and will be effectively used in next generation new semiconductor device fabrication processes.

Claims (17)

A first semiconductor layer having a flat surface comprising a Group 4 element on the periodic table of elements; A second semiconductor pattern including a Group 4 element on the periodic table of elements formed on the flat surface of the first semiconductor layer; And a third semiconductor layer formed on the flat surface of the second semiconductor pattern and the exposed first semiconductor layer and having a flat upper surface comprising a Group 4 element on the periodic table of elements. The method of claim 1, And wherein the first semiconductor layer is a single crystal silicon substrate, the second semiconductor pattern is a silicon-germanium epitaxial pattern, and the third semiconductor layer is a silicon epitaxial layer. The method according to claim 1 or 2, And the second semiconductor pattern has a line shape running parallel to each other apart from each other. The method according to claim 1 or 2, And the second semiconductor pattern has an island shape two-dimensionally arranged in a matrix. The method of claim 1, And the first semiconductor layer and the third semiconductor layer are made of the same element, and the second semiconductor layer has different electrochemical characteristics from the first semiconductor layer and the third semiconductor layer. Preparing a first semiconductor layer having a flat surface comprising a Group 4 element on the periodic table of elements; Forming a second semiconductor pattern including a Group 4 element on the periodic table of elements on a flat surface of the first semiconductor layer; And forming a third semiconductor layer having a flat upper surface comprising a group 4 element on the periodic table of elements on the flat surface of the second semiconductor pattern and the exposed first semiconductor layer. The method of claim 6, Forming the third semiconductor layer with the flat top surface is: The second semiconductor is first grown by growing a Group 4 element on the periodic table of elements at a first temperature at which the surface movement of the second semiconductor pattern does not occur on the surface of the second semiconductor pattern and the exposed surface of the first semiconductor layer. Forming a primary epitaxial layer covering the surface of the patterns; Forming a secondary epitaxial layer having a flat surface by secondly growing a Group 4 element on the periodic table of elements at a second temperature at which the surface movement of the primary epitaxial layer occurs on the primary epitaxial layer. A release semiconductor substrate forming method, comprising a. The method of claim 6, Forming the third semiconductor layer with the flat top surface is: On the surface of the second semiconductor pattern and on the flat surface of the exposed first semiconductor layer, a group 4 element on the periodic table of elements is grown at a first temperature at which the surface movement of the second semiconductor pattern does not occur. An epitaxial layer covering the gap; And heat-processing at a second temperature at which the surface movement of the epitaxial layer occurs to planarize the surface of the epitaxial layer. The method according to claim 7 or 8, And wherein the first temperature ranges from about 300 degrees Celsius to about 800 degrees Celsius, and the second temperature ranges from about 600 degrees Celsius to about 1200 degrees Celsius. The method of claim 8, The first temperature ranges from about 300 degrees Celsius to about 800 degrees Celsius, and the second temperature ranges from about 600 degrees Celsius to about 1200 degrees Celsius, and the heat treatment is performed in a hydrogen gas atmosphere. Substrate Forming Method. The method of claim 8, The first temperature ranges from about 300 degrees Celsius to about 800 degrees Celsius, the second temperature ranges from about 900 degrees Celsius to about 1200 degrees Celsius, and the heat treatment is performed in an argon gas atmosphere. Substrate Forming Method. The method of claim 9, The first semiconductor layer is a single crystal silicon substrate, Forming the second semiconductor patterns comprises growing and patterning a silicon-germanium epitaxial layer on the single crystal silicon substrate, And forming the third semiconductor layer comprises growing a silicon epitaxial layer on surfaces of the single crystal silicon substrate and the silicon-germanium epitaxial layer. Epitaxially growing silicon-germanium on a bulk silicon substrate to form a silicon-germanium pattern; Forming silicon on the silicon-germanium pattern and the exposed bulk silicon substrate at a first temperature at which no surface movement of the silicon-germanium pattern occurs; Forming a secondary silicon layer having a flat surface by growing silicon at a second temperature at which the surface movement of the primary silicon layer occurs on the primary silicon layer. The method of claim 13, And wherein the first temperature ranges from about 300 degrees Celsius to about 800 degrees Celsius, and the second temperature ranges from about 600 degrees Celsius to about 1200 degrees Celsius. Growing silicon-germanium on a bulk silicon substrate to form a silicon-germanium pattern; Forming a silicon layer by growing silicon at the first temperature at which no surface movement of the silicon-germanium pattern occurs on the silicon-germanium pattern and the exposed bulk silicon substrate; And heat-processing at a second temperature at which the surface movement of the silicon layer occurs to planarize the upper surface of the silicon layer. The method of claim 15, The first temperature ranges from about 300 degrees Celsius to about 800 degrees Celsius, and the second temperature ranges from about 600 degrees Celsius to about 1200 degrees Celsius, and the heat treatment is performed in a hydrogen gas atmosphere. Substrate Formation Method. The method of claim 15, The first temperature ranges from about 300 degrees Celsius to about 800 degrees Celsius, the second temperature ranges from about 900 degrees Celsius to about 1200 degrees Celsius, and the heat treatment is performed in an argon gas atmosphere. Substrate Forming Method.

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