KR100560504B1 - Driving method of plasma display panel and plasma display device - Google Patents

Abstract

In the plasma display device, the voltage rise time when the last sustain discharge pulse is applied to the scan electrode in the sustain period in which a plurality of sustain discharge pulses for sustain discharge are alternately applied to the scan electrode and the sustain electrode is applied to the rest of the sustain discharge pulse. It is made shorter than the voltage rise time at which is applied. In this way, shortening the voltage rise time of the last sustain discharge pulse causes a larger discharge to form more wall charges. Therefore, the address discharge delay can be shortened in the address period of the next subfield, resulting in more stable address discharge.

PDP, electrode, discharge, delay, address, sustain discharge pulse

Description

Driving method of plasma display panel and plasma display device {DRIVING METHOD OF PLASMA DISPLAY PANEL AND PLASMA DISPLAY DEVICE}

1 is a driving waveform diagram of a conventional plasma display panel.

2 is a partial perspective view of a plasma display panel according to an exemplary embodiment of the present invention.

3 is a diagram illustrating a plasma display device according to an exemplary embodiment of the present invention.

4 is a driving waveform diagram of a plasma display panel according to an exemplary embodiment of the present invention.

The present invention relates to a method for driving a plasma display panel (PDP).

In the plasma display panel, scan electrodes and sustain electrodes parallel to each other are formed on one surface thereof, and address electrodes are formed on the other surface in a direction orthogonal to these electrodes. The sustain electrode is formed corresponding to each scan electrode, and one end thereof is connected in common to each other.

1 is a driving waveform diagram of a conventional plasma display device.

As shown in FIG. 1, according to the method of driving a plasma display panel, each subfield includes a reset period, an address period, and a sustain period. The reset period of the first subfield consists of a rising period and a falling period, and the reset period of the second subfield consists of a falling period.

The reset period serves to erase the wall charges formed by the previous sustain discharge and to set up the wall charges in order to stably perform the next address discharge. The address period is a period in which a wall charge is accumulated in a cell (addressed cell) that is turned on by selecting a cell that is turned on and a cell that is not turned on in the panel. The sustain period is a period in which sustain discharge is performed to actually display an image in the addressed cell.

Referring to the driving waveform of FIG. 1, all the discharge cells are initialized in the reset period of the first subfield, and initialized for the discharge cells in which the sustain discharge has occurred in the first subfield in the reset period of the second subfield.

In the address period, a scan pulse having a VscL voltage and an address pulse having a Va voltage are applied to the scan electrode Y and the address electrode to select a cell to be turned on. Then, a discharge occurs between the scan electrode Y and the address electrode A to which the Va voltage is applied, so that the positive wall charges to the scan electrode Y, the address electrode A and the sustain electrode X, respectively (- ) Wall charges are formed.

In general, a discharge performed by applying a voltage between two electrodes is delayed in time than when a voltage is applied, thereby causing a discharge. However, since the address discharge has to be performed within a width of the constant scan pulse and the address pulse, a problem occurs that the discharge does not occur when the discharge delay time is longer than the width of the scan pulse and the address pulse.

SUMMARY OF THE INVENTION The present invention has been made in an effort to solve the above problems, and to provide a plasma display panel driving method and a plasma display apparatus capable of shortening an address discharge delay and causing stable address discharge.

According to an aspect of the present invention, a frame is formed in a plasma display panel including a plurality of first electrodes, a plurality of second electrodes, and a plurality of third electrodes formed in a direction crossing the first electrode and the second electrode. A method of driving by dividing into a plurality of subfields is provided. The driving method may include applying a sustain discharge pulse to the first electrode in a sustain period in which a plurality of sustain discharge pulses for sustain discharge are alternately applied to the first electrode and the second electrode. Increasing the voltage of the electrode, and applying a first voltage to the first electrode, wherein the voltage increase time of the last sustain discharge pulse applied to the first electrode is applied to the first electrode. Shorter than the voltage increase time of the sustain discharge pulse.

And after the first voltage is applied to the first electrode, decreasing the voltage of the first electrode, wherein the voltage increase time of the last sustain discharge pulse applied to the first electrode is increased. Shorter than the voltage reduction time of the last sustain discharge pulse applied to the first electrode.

In this case, the last sustain discharge pulse is applied to the first electrode in one subfield, the first electrode is a scan electrode, and the second electrode is a sustain electrode.

According to another aspect of the present invention, a plasma display panel in which a discharge cell is formed between a first electrode, a second electrode, and a third electrode, and for sustain discharge to the first electrode and the second electrode in a sustain period A plasma display device including a driving circuit for alternately applying a plurality of sustain discharge pulses having a first voltage is provided. In this case, the driving circuit may be shorter than the time of changing the last sustain discharge pulse applied to the first electrode to the first voltage from the remaining sustain discharge pulse applied to the first electrode. do.

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DETAILED DESCRIPTION Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art may easily implement the present invention. As those skilled in the art would realize, the described embodiments may be modified in various different ways, all without departing from the spirit or scope of the present invention. In the drawings, parts irrelevant to the description are omitted in order to clearly describe the present invention. Like parts are designated by like reference numerals throughout the specification.

A method of driving a plasma display panel and a plasma display device according to an exemplary embodiment of the present invention will now be described in detail with reference to the accompanying drawings.

First, a schematic structure of a plasma display device according to an exemplary embodiment of the present invention will be described in detail with reference to FIGS. 2 and 3.

2 is a partial perspective view of a plasma display panel according to an exemplary embodiment of the present invention, and FIG. 3 is a diagram illustrating a plasma display apparatus according to an exemplary embodiment of the present invention.

As shown in FIG. 2, the plasma display panel includes two glass substrates 1 and 6 facing each other apart. On the glass substrate 1, the scan electrode 4 and the sustain electrode 5 are formed in pairs and in parallel, and the scan electrode 4 and the sustain electrode 5 are covered with the dielectric layer 2 and the protective film 3. have. A plurality of address electrodes 8 are formed on the glass substrate 6, and the address electrodes 8 are covered with the insulator layer 7. The address electrode 8 and the partition 9 are formed on the insulator layer 7 between the address electrodes 8. In addition, the phosphor 10 is formed on the surface of the insulator layer 7 and on both sides of the partition wall 9. The glass substrates 1 and 6 are disposed to face each other with the discharge space 11 therebetween so that the scan electrode 4, the address electrode 8, the sustain electrode 5, and the address electrode 8 are orthogonal to each other. The discharge space 11 at the intersection of the address electrode 8 and the paired scan electrode 4 and the sustain electrode 5 forms a discharge cell 12.

3, a plasma display device according to an exemplary embodiment of the present invention includes a plasma display panel 100, a controller 200, an address electrode driver 300, a sustain electrode driver 400, and a scan electrode driver 500. Include.

The plasma display panel 100 includes a plurality of address electrodes A1 to Am extending in the column direction, and a plurality of sustain electrodes X1 to Xn and scan electrodes Y1 to Yn extending in pairs in the row direction. Include. The X electrodes X1 to Xn are formed corresponding to the respective Y electrodes Y1 to Yn, and generally have one end connected in common to each other. The plasma display panel 100 includes a glass substrate (not shown) in which the sustain and scan electrodes X1 to Xn and Y1 to Yn are arranged, and a glass substrate (not shown) in which the address electrodes A1 to Am are arranged. Is done. The two glass substrates are disposed to face each other so that the scan electrodes Y1 to Yn and the address electrodes A1 to Am and the sustain electrodes X1 to Xn and the address electrodes A1 to Am are orthogonal to each other. At this time, the discharge space at the intersection of the address electrodes A1 to Am and the sustain and scan electrodes X1 to Xn and Y1 to Yn forms a discharge cell.

The controller 200 receives an image signal from the outside and outputs an address electrode driving control signal, a sustain electrode driving control signal, and a scan electrode driving control signal. The controller 200 divides and drives one frame into a plurality of subfields, and each subfield is composed of a reset period, an address period, and a sustain period.

The address electrode driver 300 receives an address electrode driving control signal from the controller 200 and applies a display data signal for selecting a discharge cell to be displayed to each address electrode A. FIG.

The sustain electrode driver 400 receives the sustain electrode driving control signal from the controller 200 and applies a driving voltage to the sustain electrode X.

The scan electrode driver 500 receives a scan electrode driving control signal from the controller 200 and applies a driving voltage to the scan electrode Y.

Hereinafter, a driving waveform applied to the address electrodes A1 to Am, the sustain electrodes X1 to Xn, and the scan electrodes Y1 to Yn in each subfield will be described with reference to FIG. 4. The following description will be made based on the discharge cells formed by one address electrode, sustain electrode and scan electrode. In addition, the wall charges mentioned below refer to charges that are formed on the walls of the discharge cells (eg, dielectric layers) close to each electrode and accumulate in the electrodes. This wall charge is not actually in contact with the electrode itself, but here the wall charge is described as "formed", "accumulated" or "stacked" on the electrode. In addition, a wall voltage refers to the potential difference formed in the wall of a discharge cell by wall charge.

4 is a driving waveform diagram of a plasma display panel according to an exemplary embodiment of the present invention. In FIG. 4, only two subfields of the plurality of subfields are illustrated, and for convenience, two subfields are illustrated as first and second subfields, respectively. The reset period of the first subfield is shown as consisting of a rising period and a falling period, and the reset period of the second subfield is shown as being a falling period.

As shown in Fig. 4, the first subfield includes a reset period, an address period, and a sustain period, and the reset period includes a rising period and a falling period.

First, in the rising period of the reset period of the first subfield, a rising waveform that increases from the Vs voltage to the Vset voltage is applied to the scan electrode Y while the sustain electrode X is maintained at 0V. Then, a weak reset discharge occurs from the scan electrode Y to the address electrode A and the sustain electrode X, respectively, and negative wall charges are accumulated on the Y electrode, and the address electrode A and the sustain electrode X are accumulated. Positive wall charges accumulate at).

In the falling period of the reset period of the first subfield, a falling waveform of decreasing from the voltage Vs to the voltage Vnf is applied to the scan electrode Y while the sustain electrode X is maintained at the Ve voltage. Then, while the voltage of the scan electrode Y decreases, a weak reset discharge occurs between the scan electrode Y and the sustain electrode X and between the scan electrode Y and the address electrode A. The negative wall charges formed and the positive wall charges formed on the X and A electrodes are erased.

Next, in order to select a cell to be turned on in the address period of the first subfield, a scan pulse having a VscL voltage and an address pulse having a Va voltage are applied to the scan electrode Y and the address electrode A, respectively. The unselected scan electrode Y is biased to a VscH voltage higher than the VscL voltage, and a reference voltage is applied to the address electrode of the cell that is not turned on. Then, the address discharge occurs due to the difference between the address voltage Va and the scan voltage VscL and the wall voltage caused by the wall charges formed on the address electrode A and the scan electrode Y. As a result, a positive wall charge is formed at the scan electrode Y, and a negative wall charge is formed at the sustain electrode X. In addition, a negative wall charge is also formed on the address electrode A. FIG.

Subsequently, in the sustain period of the first subfield, the sustain discharge pulse of the Vs voltage is applied to the scan electrode Y and the sustain electrode X in order. Then, when the wall voltage is formed between the scan electrode Y and the sustain electrode X by the address discharge in the address period, the discharge is generated at the scan electrode Y and the sustain electrode X by the wall voltage and the Vs voltage. Happens. At this time, in the sustain period, the process of applying the sustain discharge pulse of the Vs voltage to the scan electrode Y and the process of applying the sustain discharge pulse of the Vs voltage to the sustain electrode X correspond to the weights indicated by the corresponding subfields. Repeat as many times.

According to the exemplary embodiment of the present invention, the Vs voltage rise time of the last sustain discharge pulse applied to the scan electrode Y in the sustain period is shortened. As the rise time is shortened, the rise slope becomes larger to cause a larger discharge, and the Vs voltage holding time of the last sustain discharge pulse of the scan electrode Y also becomes longer to form more wall charges.

In this manner, when the sustain period of the first subfield ends, the second subfield starts. The reset period of the second subfield consists only of the falling period, and in the reset period of the second subfield, the scan electrode is applied while the sustain discharge pulse of the Vs voltage is applied to the scan electrode Y in the sustain period of the first subfield. The voltage at (Y) is gradually reduced to the voltage Vnf.

At this time, when sustain discharge has occurred in the sustain period of the first subfield, negative (-) wall charges are formed on the scan electrode (Y), and positive (+) wall charges are formed on the sustain electrode (X) and the address electrode (A). When the discharge start voltage is exceeded with the wall voltage formed in the cell while the voltage of the scan electrode Y is gradually decreasing, the weak discharge occurs as in the falling period of the reset period of the first subfield. Since the final voltage Vnf of the scan electrode Y is the same as the final voltage Vnf of the falling period of the first subfield, the wall charge state of the cell after the falling period of the second subfield is the first subfield. It becomes substantially the same as the wall charge state after the falling period of.

When no sustain discharge has occurred in the sustain period of the first subfield, no address discharge occurs in the address period, so that the wall charge state of the cell remains in the state after the end of the falling period of the first subfield. Since the wall voltage formed in the cell after the fall period of the first subfield is formed near the discharge start voltage together with the applied voltage, no discharge occurs when the voltage of the scan electrode Y decreases to the Vnf voltage. Therefore, since no discharge occurs in the reset period of the second subfield, the wall charge state set in the reset period of the first subfield is maintained.

In this way, in the subfield having the reset period falling, reset discharge occurs when sustain discharge occurs in the immediately preceding subfield, and reset discharge does not occur when there is no sustain discharge. Therefore, if the first subfield is formed like the first subfield in one field and the other subfield is formed like the second subfield, when the zero gray scale (black gray scale) is displayed, the reset discharge (weak discharge) only in the reset period of the first subfield. This will happen.

As described above, the discharge performed by applying a voltage between the two electrodes is delayed in time than when the voltage is applied, the discharge occurs. In particular, since the address discharge has to be performed within the widths of the scan pulse and the address pulse, the address discharge is greatly influenced by the discharge delay time. Since the address discharge is determined by the wall voltage due to the wall charges formed in the discharge space after the end of the reset period, the address discharge delay is affected by the wall charge state after the end of the reset period. Since the wall charge state after the end of the reset period is determined according to the wall charge state since the last sustain discharge of the immediately preceding subfield, the address discharge delay is also affected by the wall charge state of the immediately preceding subfield.

Therefore, as in the embodiment of the present invention, by shortening the voltage rise time of the last sustain discharge pulse of the sustain period of the first subfield (the previous subfield), a larger discharge occurs than before, resulting in more wall charges. Will be. Therefore, even if the wall charge is erased through the reset period (falling period) of the second subfield, the reset period (falling period) of the second subfield is the same as that of the conventional driving waveform, and thus, the reset period of the second subfield is conventional. Assuming that the same amount of wall charge as in the drive waveform is erased, more wall charge remains after the end of the reset period than before. Therefore, the address discharge delay can be shorter than that of the conventional drive waveform in the address period, and thus more stable address discharge can be caused.

Although the preferred embodiments of the present invention have been described in detail above, the scope of the present invention is not limited thereto, and various modifications and improvements of those skilled in the art using the basic concepts of the present invention defined in the following claims are also provided. It belongs to the scope of rights.

As described above, according to the present invention, the address discharge time in the address period of the next subfield is shortened by shortening the Vs voltage application time of the last sustain discharge pulse applied to the scan electrode Y in the sustain period of the previous subfield. It can be shortened. As the address discharge time is shortened, there is an effect that can cause a stable address discharge.

Claims (7)

In a plasma display panel including a plurality of first electrodes, a plurality of second electrodes, and a plurality of third electrodes formed in a direction crossing the first electrode and the second electrode, a frame is driven by dividing a frame into a plurality of subfields. In the method, In a sustain period in which a plurality of sustain discharge pulses for sustain discharge are alternately applied to the first electrode and the second electrode, Applying a sustain discharge pulse to the first electrode, Increasing the voltage of the first electrode, and Applying a first voltage to the first electrode, And the voltage increase time of the last sustain discharge pulse applied to the first electrode is shorter than the voltage increase time of the remaining sustain discharge pulse applied to the first electrode. The method of claim 1, Reducing the voltage of the first electrode after the first voltage is applied to the first electrode, And the voltage increase time of the last sustain discharge pulse applied to the first electrode is shorter than the voltage decrease time of the last sustain discharge pulse applied to the first electrode. The method according to claim 1 or 2, And a last sustain discharge pulse is applied to the first electrode in the sustain period. The method of claim 3, Wherein the first electrode is a scan electrode and the second electrode is a sustain electrode. A plasma display panel in which discharge cells are formed between the first electrode, the second electrode, and the third electrode; and A driving circuit configured to alternately apply a plurality of sustain discharge pulses having a first voltage for sustain discharge to the first electrode and the second electrode in a sustain period, The drive circuit, And a time for changing the last sustain discharge pulse applied to the first electrode to the first voltage is shorter than a time for changing the remaining sustain discharge pulse applied to the first electrode to the first voltage. The method of claim 5, The drive circuit, Same time as changing the time from changing the sustain discharge pulse to the first voltage except the last sustain discharge pulse applied to the first electrode to the first voltage from the plurality of sustain discharge pulses applied to the second electrode. Plasma display device. The method according to claim 5 or 6, The first electrode is a scan electrode, and the second electrode is a sustain electrode.

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