KR100554368B1 - Gap Filler System and Method for Signal Processing with a Synchronization Gain Unit - Google Patents

Abstract

The present invention relates to a gap filler system having a synchronization acquisition device that detects synchronization data in a satellite broadcast signal and sorts the data based on the detected data, and a signal processing method thereof. In addition, the present invention provides a Ku-band antenna for receiving the TDM signal transmitted from the geostationary satellite (4) to serve the shadow area, the receiving circuit 20 for converting the TDM signal of the antenna into a baseband signal, and the TDM signal A synchronization acquisition means comprising a TDM demodulator 22 which performs QPSK demodulation and Forward Error Correction (FEC), and a TDM DeMUX 24 and a CDM modulator 26 which reconstruct the TDM signal of the TDM demodulator 22 ( 100 and a gap filler synchronization system and method comprising a transmission circuit 28 for converting and transmitting uplink signal data that can be used in the TDM DeMUX 24.

TDM demodulator, synchronization acquisition device, gap filler,

Description

Gap Filler System and Method for Signal Processing with a Synchronization Gain Unit             

1 is a configuration diagram of a conventional satellite broadcasting system

2 is a configuration diagram of a gap filler system having a synchronization acquisition device according to the present invention;

3 is a detailed configuration diagram of the TDM DeMUX of FIG.

4 is a block diagram of a TDM demodulator in FIG.

5 is a diagram illustrating a TDM DeMUX input data format structure

6 is a flowchart illustrating a UW synchronization acquisition apparatus when the lock state value is “0” according to the first embodiment of the present invention.

7 is a flowchart illustrating a UW synchronization acquisition apparatus when the lock state value is "1" according to the first embodiment of the present invention.

8 is a flowchart illustrating a UW synchronization acquisition apparatus when the lock state value is "0" according to the second embodiment of the present invention.

9 is a flowchart illustrating a UW synchronization acquisition apparatus when the lock state value is “1” according to the second embodiment of the present invention.

* Explanation of symbols for the main parts of the drawings *

4: geostationary satellite

20: receiving circuit

22: TDM demodulation unit

24: TDM DeMUX

26: CDM Modulator

28: transmitting circuit

100: synchronization acquisition device

The present invention relates to a gap filler synchronization system and method. More specifically, the present invention relates to a gap filler system having a synchronization acquisition device that detects synchronization data in a satellite broadcast signal and sorts the data based on the detected data, and a signal processing method thereof.

Satellite digital audio broadcasting in the recently proposed satellite broadcasting system

One of the key equipment to implement (DAB: Digital Audio Broadcasting) is a gap filler system that processes synchronization acquisition signals using a single frequency network. The TDM (Time Division Multiplexing) signal is modulated into a 2.6 MHz (S-band) Code Division Multiplexing (CDM) signal so that the satellite DAB terminal can receive it. That is, the broadcast satellite retransmits the signal of the terrestrial transmitting station for the satellite DAB service on the ground, and converts the broadcast signal so that the service subscribers can receive it smoothly through the mobile terminal.

An example thereof will be described with reference to FIG. 1.

1 is a view schematically showing the overall configuration of a conventional gap filler system.

The gap filler system illustrated in FIG. 1 is a system that receives and demodulates a TDM signal transmitted from a broadcast satellite, modulates it into a CDM signal, and then retransmits it. The satellite broadcasting system of FIG. 1 includes a satellite control station 1 of each broadcasting center, an earth station 2 for transmitting aptitude and edited program information from a broadcaster, and a program transmitted from the earth station 2 to a user. A stationary satellite (4) for the purpose, a gap filler device (6) for servicing a blocking / shadowing area in which no signal transmitted from the stationary satellite (4) is transmitted, and for the user to watch the program It consists of the user terminal 8. Here, the gap filler device 6 includes a wide area gap filler and a spot gap filler, and the user terminal 8 includes a portable receiving device, a fixed receiving device, a vehicle receiving device and various other types of devices.

In addition, as shown in FIG. 1, the communication signal band or band is 2.6 ㎓ (S-band) indicated by a solid line transmitted by a predetermined terminal 6 so as to be directly received, and a Ku band indicated by a dotted line (12.5-18 GHz). ) Is composed of a CDM signal transmitted for the gap filler which transmits the program to the satellite (4). That is, the transmission program having the communication band is transmitted in two modes in the satellite 4. One mode is coded and modulated so that the user can receive the program directly, and then it is transmitted as a signal of 2.6 GHz. The other mode is modulated by time division method to serve the shadow area and then transmitted to the Ku band. . In addition, the signal transmitted in the Ku band is changed by the time division modulated signal in the gap filler 6 into a code division modulation method, and then amplified and transmitted to the terminal 8.

The most important factor in such a gap filler system is the TDM DeMUX system, which detects the correct synchronization for the received TDM signal. The TDM DeMUX system has a simple structure of detecting UW data indicating the start of data among input data to perform detection, comparing the detected UW data with a set reference value, and then sorting the data. Therefore, in this TDM DeMUX system, UW data which is synchronous data of a gap filler system is detected by data comparison of a simple structure.

However, such a TDM DeMUX system cannot extract the check of the defects if there is a defect of the detected UW data, and thus the reliability is not sufficient.

Accordingly, the present invention complements the simple data comparison function used in the prior art in order to improve the disadvantages of the prior art to align the synchronous data UW data for each channel to accurately detect and extract the detected UW data to improve reliability An object of the present invention is to provide a gap filler system having a synchronization acquisition device and a signal processing method thereof.

With reference to the accompanying drawings, the gap filler synchronization system and method of the present invention for achieving the above object will be described as follows.

2 is a block diagram of a gap filler signal processing system having a synchronization acquisition device according to a preferred embodiment of the present technology.

In Fig. 2, a gap filler system for serving a shadow area includes a Ku-band antenna for receiving a TDM signal transmitted from a conventional broadcast satellite, i.e., the stationary satellite 4 of Fig. 1, and a baseband signal from the TDM signal of the antenna. A TDM demodulator 22 for performing QPSK demodulation and FEC (Forward Error Correction), and a TDM DeMUX 24 for reconstructing the TDM signal of the TDM demodulator 22. And a synchronization acquisition means (100) comprising a CDM modulator (26), and a transmission circuit (28) for converting and transmitting uplink signal data that can be used in the TDM DeMUX (24).

Here, the Ku band antenna receives a TDM signal transmitted from a conventional broadcast satellite, i.e., the stationary satellite 4 of FIG. 1, and the receiving circuit 20 converts the TDM signal of the Ku band antenna into a baseband signal.

In addition, the TDM demodulator 22 of the synchronization acquisition apparatus 100 converts the signal converted into the baseband into data that can be used in the TDM DeMUX 24.

In addition, the TDM DeMUX 24 of the synchronization acquisition apparatus 100 performs a process of rearranging the TDM data to generate data for modulating the data converted by the TDM demodulator 22 into a CDM signal. The rearranged data is modulated by the CDM modulator 26 into a CDM signal, and the modulated data is upconverted to 2.6 GHz by the transmission circuit 28 and then transmitted through a 2.6 GHz band antenna.

3 is a diagram illustrating a detailed configuration of a TDM DeMUX for searching for a synchronization signal by the synchronization acquisition device of FIG. 2.

As shown in FIG. 3, in the gap filler signal processing system, first, a signal converted into baseband by the receiving circuit 20 is input to the TDM demodulator 22. The TDM DeMUX 24 also detects the received TDM signal by the UW detector 30 and converts it into data for use in the TDM DeMUX 24 according to the detected signal, which is converted into data. Data is also transmitted to the address control unit 32 to modulate the CDM signal. In addition, the TDM DeMUX 24 performs a function of sorting data for each channel in order to modulate an input signal by a code division method.

The UW detector 30 performs a function of obtaining synchronization indicating the start of data when sorting the data.

In addition, the data demodulated in the DeMUX 24 is stored in the memory bank 34 together with the control data of the address control unit 32, and the data is re-arranged, and the rearranged data is transferred to the CDM modulation unit 26. By the CDM signal.

4 is a detailed configuration diagram of the TDM demodulator 22 shown in FIG. 2.

The synchronization acquiring means of the gap filler signal processing system requires synchronization of data between the transmitting side and the receiving side in order to extract a signal without error at the receiving side. At this time, the analog signal passing through the receiving circuit 20 is matched with a complex multiplier 44 to perform decoding after passing through the analog-to-digital converter 42 and the digital-to-analog converter 42 '. The filter 46 passes through a filter, a Viterbi decoder 48, a de-interleaver 50, and an RS decoder 52. The signal passing through the RS decoder 52 is transmitted to the TDM DeMUX 24 and the UW detector 30.

FIG. 5 is a detailed block diagram showing the channel format structure of the TDM DeMUX 24 shown in FIG. In FIG. 5, the format structure includes a pilot channel signal PS indicating a start of data, a unique word d1, a frame counter d2, and a plurality of data signals when the synchronization signal and data are aligned. Consists of another channel signal. When sorting the data for each channel, the TDM DeMUX 24 determines whether the structure of the unique word data d1 is equal to the structure as 0110 1010 1011 0101 0101 1001 1000 1010.

In accordance with this format structure, the TDM DeMUX 24 detects synchronization of matching data to the received TDM signal. The TDM DeMUX 24 also has a structure of detecting UW data in a format indicating the start of data among input data to perform detection, comparing the detected UW data with a set reference value, and then aligning the data. have. In addition, since the TDM DeMUX system detects UW data, which is the synchronization data of the gap filler system, by comparing the data of the structure described above, if there is a defect in the detected UW data, the defect is checked and the reliability is sufficiently secured.

Next, a synchronization method by a gap filler signal processing system having a synchronization acquisition device according to the present invention will be described.

FIG. 6 is a flowchart for performing a synchronization signal when the initial state and the lock state value are "0" in a signal processing method of a gap filler system having a synchronization acquisition device.

Initially, the lock state is input during data input when the lock state is set to a value of "0" (S 600) and the lock state is set to "0" in the setting step (S 600). In the case where the data is "X = B8", the synchronization signal is "HIGH", and the value of the frame lock is "0", it is determined (S 602) and the input data is determined and determined (S 602). If is generated, it is determined whether the input parity signal is "HIGH" (S604).

If the input parity signal is "HIGH" in the step of determining the input parity signal (S604), since the input signal is a signal of the data area, the number of data input when the input parity signal is "HIGH" Determine (S606).

If the number of input data is not 54144 in the step of determining the number of input data (S 606), the value of the byte counter for calculating the number of data is increased to “1” in the input byte counter (S 608). .

In step S602, when checking and determining the input data, it is determined whether the value of the frame lock state is "0" or "1", and the value of the frame lock state is determined. In operation S610, the controller operates in two modes as follows.

In step S602, when checking and determining the input data, it is determined whether the value of the frame lock state is "0" or "1", and the value of the frame lock state is determined. If the determination result in step S610 is that the value of the frame lock state is "1", it is measured whether the byte counter of the input data is a multiple of the frame data number (188 * N), If it is determined that the multiplier (S 628) and the number of the frame number is a multiplier (S 628), if the same number of frame data number multiple has a multiple, determining whether the frame counter value is "287" (S 630) and when the frame counter value is “287” in the step S630, the FRAME SYNC value is “0”, the byte counter value is “0”, and the frame counter value is “287”. 0 ”, rock After the operation is finished in the step S632 of setting the value of the LOCK STATE and the value of the lock counter to “0” and the setting of each value (S 632), the packet counter If the counter value is "8" in the step of determining whether the value is "8" (S 634) and the determination of the packet counter value (S 634), the packet counter value is set to "0" (S 636). If not, the step (S 610) includes a step S635 of adding and setting the packet counter value to " 1 ".

In the step S610 of determining the value of the frame lock state (S610), if the frame lock state is “0”, the process of determining whether synchronization data is acquired is performed. The synchronous data is compared with the input 8-byte data and UW data, and then the lock state is set as a value of "0" (S 600) and the input data set in step S600 and stored for a period of 8 bytes. If the input data and the UW data are the same in the step S612 of determining whether the UW data values set as the synchronization signal for the data and the TDM signal are the same (S612) and the step (S612) determining the values are the same, the lock is performed. In the storing of the counter (S 614) and the storing of the lock counter (S 614), the current number of biter counters determines whether the position value from which the UW data should be extracted is “16”. In step S 616 and determining the position value to be extracted (S 616), if the byte counter is not "16" which is the position of the UW data, increasing the value of the lock counter by "1" (S622) and Comparing the lock counter with a reference value set in step S622 of increasing the value of the lock counter by " 1 "; And setting the value of the lock state to "0" if it is larger than the reference value (S 626).

7 is to improve the reliability of the synchronization signal when the lock state value is "1" in the signal processing method of the gap filler system having a synchronization acquisition device and to determine the case where the lock state is not the lock state (LOCK STATE). This is a flow chart to perform.

First, when the LOCK STATE value is set to "1", both functions are performed simultaneously. In this performance, one performs a function of storing the input data in the order of input for a period of 8 bytes. The other operates the byte and frame counters to order the data.

The lock state is set to a value of "1" (S 700) and the input parity signal value is set to "1" in order to align the order of data after setting the lock state value in the setting step (S 700). If it is determined in step (S702) that the input parity signal value is "1", the lock counter value is increased by "1" (S721) and the lock counter value is "1". In the step of increasing (S 721), the lock counter value is increased by “1”, and it is determined whether the increased value of the lock counter is greater than the reference value (S724) and the value (S724). If it is determined that it is large, it is determined that synchronization is not obtained, and setting the lock state value to “0” and the frame lock state value to “0” (S 726). (S 702).

After determining whether the input parity signal value is "1" (S702), when the input parity signal value is "1", increasing the byte counter value by "1" (S704) and the byte counter value Determining whether the byte counter that has been incremented by "1" in step S704 is a multiple of frame data (188 * N) (S706) and determining whether it is a multiple of the frame data (S706) It is determined whether the counter is a multiple of the frame data (188 * N) and the frame counter value is "287" (S708).

In step S708, when the byte counter is a multiple of the frame data (188 * N) and the frame counter value is "287", the frame SYNC value is "1" and the byte counter value is determined. "0" and setting the frame counter value to "0" (S 710) and determining each packet value to determine whether the packet counter value is "8" (S 712); After the packet counter value determination step (S 712), if the packet counter value is "8", setting a packet counter value to "8" (S 714); and setting each value (S 710). Thereafter, in the case where the packet counter value is "0" (S 714), it is determined whether the byte counter is "16" which is a SYNC byte position value (S 716) and whether it is "16" which is the SYNC byte position value. In step S716, if the YNC byte position value is “16”, an 8 byte group is used. Step of storing in sequence for a while (S718),

After storing in the order (S718), the step of determining whether the stored data is the same as the UW data (S 720), and the step of determining whether the stored data is the same as the UW data (S 720) and the stored data and UW If the data is the same, the lock counter value is set to "0" (S722).

8 and 9 illustrate a case in which a method of measuring whether a data is equal to a correlation value when comparing input data accumulated by UW data size and UW data in a signal processing method of a gap filler system having a synchronization acquisition device is used. Since the overall operation is almost the same as in Figs. 6 and 7, detailed description is omitted.

However, while the present invention has been described in detail only with respect to the embodiments described, it will be apparent to those skilled in the art that various modifications and variations are possible within the technical spirit of the present invention, and such modifications and modifications belong to the appended claims. will be.

As described above, according to the gap filler system having the synchronous acquisition device of the present invention and the signal processing method of the system,
In order to match the frequency and phase of two or more oscillators by the synchronization acquisition device, UW data can be accurately detected and the UW data can be improved and the data alignment of TDM DeMUX can be performed more accurately and stably. do.

Claims (5)

delete In the signal processing method of the gap filler system, Initially, the lock state (LOCK STATE) is set to a value of "0" (S 600); In the setting step S 600, when the lock state is "0", the data input during data input is "X = B8", the synchronization signal is "HIGH", and the value of the frame lock is "0". Determining whether it is determined (S602); Determining whether the input parity signal is "HIGH" when the same case occurs in the step of checking and determining the input data (S 602) (S 604); If the input parity signal is "HIGH" in the step of determining the input parity signal (S604), since the input signal is a signal of the data area, the number of data input when the input parity signal is "HIGH" Determining (S606); When the number of input data is not 54144 in the determining of the number of input data (S 606), increasing the value of the byte counter for calculating the number of data to the input byte counter by “1” (S 608). ); In step S602, when checking and determining the input data, it is determined whether the value of the frame lock state is "0" or "1", and the value of the frame lock state is determined. If the determination result in step S610 is that the value of the frame lock state is "1", it is measured whether the byte counter of the input data is a multiple of the frame data number (188 * N), If it is determined that the multiplier (S 628) and the number of the frame number is a multiplier (S 628), if the same number of frame data number multiple has a multiple, determining whether the frame counter value is "287" (S 630) and when the frame counter value is “287” in the step S630, the FRAME SYNC value is “0”, the byte counter value is “0”, and the frame counter value is “287”. 0 ”, rock After the operation is finished in the step S632 of setting the value of the LOCK STATE and the value of the lock counter to “0” and the setting of each value (S 632), the packet counter If the counter value is "8" in the step of determining whether the value is "8" (S 634) and the determination of the packet counter value (S 634), the packet counter value is set to "0" (S 636). If not, including the step of adding to the packet counter value "1" and setting (S 635) (S 610); In the step S610 of determining the value of the frame lock state (S610), if the frame lock state is “0”, the process of determining whether synchronization data is acquired is performed. The synchronous data is compared with the input 8-byte data and UW data, and then the lock state is set as a value of "0" (S 600). Determining whether the values of the UW data set as the synchronization signal for the data and the TDM signal are the same (S612); Storing the lock counter when the input data and the UW data are the same (S 614) in determining whether the values are the same (S 612); In step S 614, storing the lock counter, determining whether the current number of biter counters is a position value of “16” from which UW data should be extracted (step S 616); Increasing the value of the lock counter by “1” when the byte counter is not “16” which is the location of the UW data in the step S 616 of determining the position value to be extracted (S 622); Comparing the lock counter with a reference value set in step S622 of increasing the value of the lock counter by " 1 "; And, And setting the value of the lock state to "0" (S 626) if the reference value is larger than the reference value. delete In the signal processing method of the gap filler system, The lock state is set to a value of “1” (S 700); In order to align the order of data after setting the lock state value in the setting step (S 700), first, it is determined whether the input parity signal value is “1”, and whether the input parity signal value is “1” (S 702). If it is determined in step (a) that the lock counter value is increased by "1" (S 721) and the lock counter value is increased by "1" (S 721), the lock counter value is increased by "1". If it is determined in step S724 of determining whether the increased value of the lock counter is greater than the reference value and in step S724 of determining the value, it is determined that synchronization is not obtained, and the lock state value is determined. Setting the frame lock state to “0” and setting the frame lock state to “0” (S 726); Determining whether the input parity signal value is "1" (S702), and then increasing the byte counter value by "1" when the input parity signal value is "1" (S704); Determining whether the byte counter increased by "1" in the step S704 of increasing the byte counter value is a multiple of the frame data (188 * N) (S706); Determining whether the byte counter is a multiple of the frame data (188 * N) and the frame counter value is "287" at step S 706 (S 708); In step S708, when the byte counter is a multiple of the frame data (188 * N) and the frame counter value is "287", the frame SYNC value is "1" and the byte counter value is determined. Setting the frame counter value to “0” and “0” (S710); Determining whether the packet counter value is “8” in the setting of the respective values (S 710) (S 712);  Determining a packet counter value as “8” when the packet counter value is “8” after the packet counter value determining step (S 712); Determining whether the byte counter is “16”, which is a SYNC byte position value, in step S 714 when the packet counter value is “0” after setting each value (S 710); If the YNC byte position value is “16” in the step of determining whether the SYNC byte position value is “16” (S716), storing the sequence sequentially for 8 byte periods (S718); Determining in step S720 whether the stored data is identical to the UW data after the storing in the order (S718); And, If the stored data and the UW data is the same in the step (S 720) of determining whether the stored data is the same as the UW data, the gap filler system comprising the step of setting the lock counter value to "0" (S 722) Signal processing method. delete

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