KR100553948B1 - Method for erasing and programming memory devices - Google Patents

Abstract

A method of programming and / or erasing an array of stacked gate memory devices such as EPROM and EEPROM devices of a NOR array is disclosed. In this method, program verification or erase verification is performed intermittently with programming of the device or erasing of the array. During the program verify period, negative V _CS is applied to the device excluded from the selection of the array, or negative V _BS is applied to both the selected device and the device excluded from the selection, or both conditions apply. It is efficient and accurate to run program verification or erase verification in this manner. During the programming phase, it is preferable that a negative V _CS is applied to a device excluded from the selection of the array, a negative V _BS is applied to a selected device of the array, or both conditions are applied. If there are any over erased devices in the array, applying a negative V _CS to the excluded device during the programming period, the presence of the over erased device will not adversely affect the programming of the device.

Description

Charge Change Process on the Floating Gate of Multiple Stacked Memory Devices in a Noah Array {METHOD FOR ERASING AND PROGRAMMING MEMORY DEVICES}

1 is a schematic diagram of a stacked gate EEPROM device.

2 is a schematic diagram of a NOR array of devices.

3 is an overview of a device programming process for verifying the charge of a floating gate during a programming period.

4 is an overview of a process for erasing a NOR array that verifies the charge on the floating gates of individual devices in the array during the erase period.

5 illustrates the body effect shift of a stacked gate memory device of a NOR array when the array is affected by four different values of negative V _BS (-0.5V, -1.0V, -1.5V and -2.0V). Histogram of the body effect shift.

The present invention relates to a method of erasing and programming electrically programmable read-only memory (EPROM and EEPROM) devices in a NOR architecture.

Nonvolatile memory is a type of memory that holds stored data even when power is removed. Read only memory (ROM), erasable programmable read only memory (EPROM) and electrically erasable programmable read only memory (EEPROM); There are several types of nonvolatile memory. These memories have an array of individual memory devices, which are called individual cells in the array. One device array is typically a subset of the total memory. The EPROM is erased using ultraviolet light and the EEPROM is erased using an electrical signal. Electrical signals are used to record EPROM and EEPROM. In a conventional flash EEPROM (“flash” indicates that all memory cells or sectors of a cell are erased simultaneously), memory cells are simultaneously erased to a low threshold voltage and then programmed individually or in small groups at a high threshold voltage. . EPROMs and EEPROMs are commonly used in data processing systems that require reprogrammable nonvolatile memory.

A typical device structure for an EEPROM cell is a floating gate polysilicon transistor. A typical floating gate structure is illustrated in FIG. As shown in FIG. 1, a floating gate 10 sandwiched between two insulating layers 20, 60 is between the substrate 30 and a typical select-gate electrode 40. The structure shown in FIG. 1 is a stacked gate memory cell in which " stacked " indicates that the floating gate 10 is stacked over the source 50 and drain 70 portions of the substrate. Another EEPROM structure is a split gate structure in which a floating gate is disposed only above the drain and no portion of the floating gate is disposed above the source. The split gate EPROM and EEPROM device structures are described in U.S. Hong, Hong, which is incorporated herein by reference. Patent No. 5,349,220. As a result, in EPROM and EEPROM, the select gate voltage must be capacitively coupled in series with the floating gate, rather than directly connected to the bottom channel.

There are n-channel and p-channel devices having the structure described above. In an n-channel device, the source and drain are doped with n-type dopant and the substrate is doped with p-type dopant. In p-channel devices, the source and drain comprise p-type dopants and the substrate comprises n-type dopants. In silicon based substrates such as silicon or silicon germanium (SiGe) alloys, boron is one example of a p-type dopant, and arsenic and phosphorus are examples of suitable n-type dopants.

EPROM and EEPROM are programmed by applying a set of bias voltages to the device shown in FIG. The voltage applied to the select gate (hereinafter referred to as the control gate) is V _C , the voltage applied to the drain is V _D , and the voltage applied to the source is V _S. The voltage applied to the substrate is referred to as V _B , and typically all cells in an array have the same voltage V _B applied to the cell. Programming as used herein is the addition of negative charges to the floating gate.

The voltage difference (commonly referred to as bias) between these various terminals can be expressed in the following manner, for example, V _CS = V _C -V _S and the like. In an n-channel device, the write bias is used to write a cell by introducing additional negative charge to the floating gate. However, if the charging state is selected as the "unrecorded" state, introducing additional negative charge to the floating gate will erase the cell. The bias condition used to introduce a more negatively charged state is different from the bias condition used to read a charged state or to create a more positively charged state.

These write biases are typically high control gate-source voltages V _CS and / or high drain-source voltages V _DS . These programming voltages are sufficient to allow electrons to transfer from the bulk of the region of the device (channel 80 and / or source 50 and / or drain 70) to the floating gate where they are trapped. The floating gate is thereby more charged with negative charge. The charge is trapped at the floating gate 10 because the floating gate is insulated from the select gate 40 by an insulating oxide layer 60 and from the drain-source-substrate by another thin oxide insulating layer 20. Because it becomes. The intention of trapping charge on the floating gate is to raise the threshold voltage V _TH to a predetermined predetermined level. In addition, these programming voltages are outside the range of normal read bias conditions, so that unintended writes do not occur during reading.

EPROMs and EEPROMs generally include an array of floating gate transistors. The V _TH of a given cell can be determined by the sense amplifier at the time of reading and decoded to its logic value. For example, in the conventional two-state memory, as described above, the high V _TH made by writing is decoded into logic one. Then, an intrinsic (intrinsic), V _TH (V _TH of the non-recorded by adding to the floating gate 10, a device with a negative charge) is decrypted to a logic zero. Because the floating gate is insulated, the cell can remain programmed or erased for a long period of up to 10 years or more. However, certain problems are encountered when erasing and writing stacked gate memory cells in an array of memory devices constructed of a general structure known as a NOR array. The NOR structure consists of multiple EPROM or EEPROM cells. In a NOR structure, at least four cells are arranged such that the sequence of cells exists in two directions. The sequence of cells in the first direction is called a row of cells, and the sequence of cells in the second direction is called a column of cells. NOR arrays require that there be at least two rows of cells and columns of at least two cells. Also, in a NOR array, each column of cells has its own dedicated bit line, and the drain of the cell in a given column is electrically connected to the same bit line. Moreover, each row of cells has its own dedicated word line, and the gates of the cells in a given row are all electrically connected to the same word line. The source is connected to a source voltage (V _S ) power supply. In a NOR array, more than one bit line can be selected at the same time, but only one word line is selected at a time.

Cells in the array are programmed and read individually. The cell is " selected " for program / read, where the program and read are made by applying arbitrary voltages to the word and bit lines connected to the selected cell. The applied voltage is different from the voltage applied to the remaining cells of the array. The remaining cells in the array are excluded from the selection. For example, the selected cell is read by applying a voltage to the word and bit lines of the selected device. Specifically, V _CS greater than the desired V _TH is applied to the word line and V _DS of about 1 volt is applied to the bit line of the selected device. Applying voltage to the remaining word lines and bit lines in the array results in applying V _CS = 0 and V _DS = 0 to the devices that are excluded from the selection. Then, V _S = 0 (but V _S may be greater than or equal to 0). When V _S = 0, V _CS = V _C (voltage applied to the word line) and V _DS = V _D (voltage applied to the bit line). Under such conditions, the selected cell is read. Also under normal reading conditions, V _BS is zero.

Before introducing charge into the floating gate of the cells in the NOR sub-array of the memory cell, all cells in the subarray are erased simultaneously. When the NOR array of memory cells is erased, the V _TH distribution of the memory will be about 2 volts wide. Thus, V _TH distribution requires careful control to avoid "over-erasing" of the cell. The cell is over erased when V _TH is lower than zero. Cells with V _TH lower than zero cannot be excluded from selection during reading. Such cells cannot be in this state because they adversely affect the operation of the array.

All cells of the programmed array to be excluded from selection by applying V _CS equal to zero must have V _TH much greater than zero. As used herein, V _TH represents the charge on the floating gate of a cell, and therefore V _TH determines the state of the cell. The following describes how the value of V _TH is decoded on or off by the sense amplifier. As used herein, V _TH is the voltage of the device that determines whether the device is read on or off by the sense amplifier.

In this specification, V _TH is defined such that the sense amplifier connected to the bit line reads the device on when V _C is greater than or equal to V _TH of the device and V _D is greater than zero. A sense amplifier connected to the bit line will read the device off when V _C is lower than the V _{TH of} the device. Thus, to the extent that a cell is over erased in a NOR array, the cell must be reprogrammed to V _TH greater than zero by a convergence technique. Such over erased cells are uncontrollable in writing using conventional channel hot electron injection techniques that introduce charge to the floating gate, because cells with V _TH less than zero cause large bit line leakage. Large bit line leakage makes it difficult to supply the V _DS needed to write a cell. Moreover, even if one or more of these over erased cells are written, the cells excluded from the selection may be written in the process. Thus, the presence of an over erased cell interferes with the programming of the devices in the array.

Programming, as defined herein, is the addition of negative charges to the floating gate such that the cell's V _TH is increased. Erasing is the removal of negative charge from the floating gate so that the V _TH of the cell is reduced. Programming is, a portion of the cell can be used to correct the over-erased state, the V _TH ≤0 by programming a rather low V _TH-TAR state corresponding to all the cells in the lowest logic states with the lowest V _TH. Other logic states can be programmed to higher V _TH-TAR values. For example, the conventional two-state memory (logic 0 and logic 1) has V _TH-TAR (0) and V _TH-TAR such that 0 <V _TH-TAR (0) <V _TH-TAR (1). Will have (1). The target threshold voltage V _{TH -TAR} (clear) during the erase phase will be below V _{TH -TAR} (0), and this selection will ensure that it is erased below the logic zero state before any programming stage. In the following, V _TH-TAR is the target threshold during a program or erase cycle, in which V _TH is increased to V _TH-TAR corresponding to any logic state or decreased to the erased threshold voltage, respectively. do.

In addition, it is desirable and sometimes necessary to verify that the NOR array is correctly programmed or correctly erased due to variations between individual devices, variations in sense amplifiers, uniformity of program convergence, changes in ambient temperature during programming, and the like. Such verification is often necessary to ensure that each device in the array has the desired amount of charge on the floating gate. However, the conditions used to verify the amount of charge on the floating gate of one selected device do not provide reliable information about the charge state of the selected device when there are over erased cells in the array. If the reading is not correct, it is not known whether the device has been properly programmed or whether it has been properly erased. Thus, a need exists for a method of programming or erasing the floating gate of an EEPROM device in a NOR array that is less susceptible to errors due to over erased cells. There is a need for a method of programming the floating gate of an EPROM and EEPROM device in a NOR array that can more accurately verify the charge on the floating gate.

The present invention relates to a process for programming or verifying a program or erase of a stacked gate memory device of a NOR array. Aspects of the present invention relating to programming and program verification are applicable to EPROM and EEPROM devices. Aspects of the present invention relating to erase and erase verify are applicable only to EEPROM devices. In this invention, the charge on the floating gate of the device is periodically verified during the programming or erase period. In order to correctly program a device, or to accurately or efficiently verify the charge on the floating gate of a device being programmed or erased, any conditions on other devices in the array so that other devices do not compromise the accuracy of programming or verification. This applies.

For ease of explanation, the present invention is described in terms of n-channel devices. In conclusion, all biases and inequalities (e.g., V _CS > 0) described below are for the n channel. Those skilled in the art will appreciate that for p-channel devices, all of the biases and inequalities expressed are opposite in sign to those expressed for the n-channel device, but the absolute values are the same.

For example, in the program cycle of the present invention, the cells of the array are selected by applying V _CS > 0 (via the word line for the selected cell) and V _DS > 0 (via the bit line for the selected cell). do. By applying a predetermined V _DS to two or more bit lines, two or more devices can be programmed simultaneously. In general, V _CS is above 0 volts and below 10 volts, and V _DS is above 0 volts and below 5 volts. V _BS applied to the entire array is less than or equal to zero. The other cells in the array are excluded from the selection by applying a V _CS that is less than or equal to zero (via the word line for the cell that is not selected). At least one of V _CS and V _BS is lower than zero.

In this invention, word lines and bit lines excluded from selection are word lines or bit lines not connected to the selected device. In embodiments where V _CS applied to a device excluded from selection is negative, V _CS may not be too loud, or pre-programmed cells in the array will be more susceptible to erroneous erasure (by tunneling). . In this regard, it is believed that V _{CS, which} is about -2 volts to less than zero volts, will be appropriate. Much over erased cells such that V _TH is less than zero or equal to zero may be excluded from selection when V _CS ≦ V _TH ≦ 0. Consequently, V _CS <0 reduces the chance of over erased cells causing false reads or programs.

When a device is programmed, the charge on the floating gate is periodically verified to determine if it is in or above a desired programming state for that device (ie, a condition for "reading" the charge on the floating gate is applied. ). The desired programming state is V _TH-TAR . In conclusion, the purpose of the program verification step is to determine whether V _TH of the selected cell is V _TH-TAR or whether it is very close to V _TH-TAR or not. Those skilled in the art will appreciate that it is advantageous for V _TH to be equal to V _TH-TAR although it is acceptable to have V _TH slightly above V _TH-TAR and still obtain adequate performance from the programmed memory. V _TH is the amount that may exceed the V _TH-TAR will depend on the operating tolerances of the particular device. In view of this, the V _TH is not desirable to lower than V _TH-TAR.

During the program-verify step, the V _CS that is applied to the selected device is equal to V _TH-TAR or higher than V _TH-TAR (but, lower than the V _CS used to program a device). During the program verify phase, at least one negative V _BS is continuously applied to the selected cell (typically a negative V _BS is applied to all devices in the array, not just the selected cell) and V _CS below zero is excluded from the selection. Is applied to V _CS . If the cell selected during the program-verify step V _TH is determined to be lower than V _TH-TAR, program \ program verify cycle continues. If during the program-verify step, the V _TH is determined to be equal to V _TH-TAR or higher than V _TH-TAR, is completed the programming of the particular cell. When reading a programmed array, the V _CS applied to the deselected devices, the same as the V _CS applied to the deselected devices during programming is desirable. If the V _BS for the program steps the same as the V _BS for the program-verify step it is also preferred.

Some devices are programmed by conditions that require the application of a negative substrate bias. Exemplary conditions for programming an EEPROM device using a negative V _BS are described in US Patent No. 5,569,504 to Bude et al. The same V _BS is applied to all devices in a given array, regardless of whether V _BS is less than or equal to zero.

When the device is programmed with a negative substrate bias (V _BS ), the negative substrate bias is also applied when reading the cell during the program verify step. Accurate program verification can be achieved by applying a negative substrate bias during program verification, thereby determining the V _TH− by the body effect shift (ie, the relationship between the substrate bias and the threshold voltage of the device determined by a given sensing scheme). Despite the fact that the _TAR is shifted, it is executed. The body effect shift is zero when V _BS is equal to zero. In the device array of the present invention, the shift of the V _TH-TAR due to the body effect shift does not substantially vary from cell to cell. Thus, once the body effect shift in V _TH-TAR is determined for one cell in a particular array, the program verify of V _TH-TAR is the V _CS for the same selected cell and the sum of V _TH-TAR and its body effect shift Is executed using The same body effect shift is used when verifying each cell. This is desirable because switching on the substrate bias for programming and switching off the substrate bias for program verification wastes both power and time. For this reason, a negative V _BS was not used during the program verify phase when a zero V _BS was used to program the device.

In an embodiment of the present invention for programming a device using a negative V _BS , program verification includes: 1.) a negative V _BS approximately equal to the V _BS applied to the device during programming, 2.) a V _TH-TAR and a body. 3. The control gate bias V _CS equal to the sum of the effect shifts, and 3.) is applied by applying a V _DS higher than zero to the selected device.

It is preferred that V _B and V _S during the program verify phase are approximately equal to V _B and V _S during the programming phase. Those skilled in the art will appreciate that the greater the difference between these values during the program and program verification steps, the greater the amount of power and time that program verification will require. It is desirable to keep these values approximately the same during programming and program verification to maintain the power and time required for program verification within acceptable limits.

In a second embodiment of the invention, a negative V _CS is applied to a word line of a device that is excluded from the selection of the array during programming, program verify, or erase verify period (i.e., a word line different from the word line of the selected device described above). It is advantageous if is applied. In the process of the present invention, it is advantageous to the cell using a negative V _BS program or when the cell is programmed using a V _BS equal to zero applied to the cell, except for the negative V _CS in the selection. For example, if the program condition for the selected cell is V _BS = 0, V _CS > 0, and V _DS > 0, then the condition applied to the cell excluded from the selection during programming is V _BS = 0 and V _CS < 0 and V _DS = 0. If the program verify condition is V _BS = 0, V _CS = V _TH-TAR, and V _DS > 0, the condition applied to the cells excluded from selection during program verify is V _BS = 0, V _CS <0, and V _DS = 0. In the above example, the device is programmed and programming is verified without using a negative V _BS .

If the program condition is V _BS <0, V _CS > 0, and V _DS > 0, the condition applied to the cell excluded from selection during programming is V _BS <0, V _CS <0 and V _DS = 0. If the program verify condition is V _BS <0, V _CS = V _TH-TAR + body effect shift, and V _DS > 0, the condition applied to the cells excluded from selection during the program verify period is V _BS <0, V _CS <0 and V _DS = 0. In the above example, the device is programmed using a negative V _BS and the programming is verified.

In another embodiment of the present invention, erase verification is performed to determine when erase is complete. Erasure is complete when all cells have V _TH ≦ V _{TH -TAR} for erasure. V _TH-TAR for erasure will generally be lower than V _TH-TAR for program. When the array is erased, the charge on each device's floating gate is first verified. Verification is performed using the conditions described above. Erase verify is also applied, or target threshold voltage (V _TH-TAR) and the sum controls the gate bias of the body effect (V _CS), that is, the cells, except for the negative V _CS from the selection to the device of a negative V _BS array It is executed by applying to, or in both cases. However, since the same power and time considerations for the program verify do not appear in the erase verify situation, V _B and V _S during the erase verify period need to be approximately equal to both V _B and V _S at the erase verify period, or accordingly There is no advantage.

Applying negative V _CS to a cell excluded from selection or applying a negative V _B to all cells prevents current from being supplied to the selected bit line through the device excluded from selection. By preventing such leakage from passing through the over erased device, errors in verifying the charge on the floating gate of the device are avoided.

The present invention relates to a process for programming and erasing a stacked gate device of a NOR array and verifying the charge on the floating gate of individual devices of the NOR array upon erasing or programming the device. The basic NOR array is illustrated in FIG. NOR array 100 has two columns 110, 120 and two rows 130, 140. Each column 110, 120 of the device has a bit line 150, 160 associated therewith, respectively. Each row 130, 140 of the device has word lines 170, 180 associated therewith, respectively. Devices in the array 100 have the symbols 181, 182, 183, 184. The drain of each device 181, 182, 183, 184 is connected to the bit line for the specific device. The gate of each device 181, 182, 183, 184 is connected to the drain line for a particular device. Devices 181, 182, 183, 184 have a common V _B and V _S.

In a conventional NOR array, a device is selected by applying an arbitrary voltage to one word line and one or more bit lines. For the sake of convenience in this description, the operation of a simple array is described where the voltage is applied to only one of the bit lines of the array at one time.

For example, referring to FIG. 2, the device 181 applies a voltage greater than zero on the word line 170 while maintaining the voltage on the bit line 160 and the word line 180 equal to zero. It is selected by applying a voltage greater than zero on the bit line 150. Accordingly, the device 181 at the intersection of the bit line 150 and the word line 170 is selected. The other three devices 182, 183, 184 are "excluded from selection."

In the process of the present invention, programming or erasing of a selected device is accomplished by periodically verifying the charge on the floating gate of the device when the device is programmed or erased. Program verify and during the erase verify step, the actual V _TH of the device program steps or erased whether or not V _TH-TAR of the device is determined during the step (a program of V _TH-TAR and erasing of V _TH-TAR for a while Are different and V _TH-TAR (program) ≥ V _TH-TAR (clear)). In conclusion, the verify phase is a read phase that is executed periodically during the programming or erasing period of the array of memory cells.

In the standard reading step, the cell is V _DS> 0 and, V _TH-TAR (erase) rather than the greater or the same V _TH-TAR (program) it is, the V _CS (that is, than the V _TH-TAR (erase) ≤ V _CS V _TH-TAR (program)) and V _BS = 0. In the process of the present invention, the conditions that enable the programming, program verify or erase verify steps to be executed effectively and accurately include the devices selected from the selected device or array of arrays during programming, program verify, erase verify, or the like, or This applies to both.

In one aspect of the present invention, a negative V _BS is, during the program-verify period for a program device using a negative V _BS to the case of verifying the charge on the floating gate, is used. Thus, verification can be performed more efficiently because there is no need to switch (consuming both time and energy) from the negative V _BS during the programming period to zero V _BS during the verification period. Since applying a negative V _BS causes a body effect shift in V _TH of the device, the V _CS applied to the selected device during the verification period is _equal to the V _TH-TAR and the body effect shift (denoted by γ (V _BS )). Must be sum Adjusting V _CS in this manner during the verification period yields accurate results when reading the memory array using a V _BS equal to zero during normal operation (as opposed to reading in the verify situation of a program or erase cycle).

In another aspect of the invention, a negative V _CS is applied to a device excluded from the selection of the array during programming, program verify or erase verify period. Applying a negative V _CS prevents errors in programming or verifying the V _TH-TAR of the selected cell. A summary of the conditions expected by the present invention is presented in Tables 1 and 2 below.

The V _DS applied to the selected cell during the program verify period is typically about 0.8V to 1.5V. The V _DS applied to the selected cell during programming is about 2.5V to about 6V. The V _CS applied to the selected cell during the programming period is typically about 2V to about 12V. V _BS-PROG is generally about -2V to about -3V.

V _CS , V _CD or V _CB during the erase period is, for example, about −15 to about −20V. Those skilled in the art will appreciate that the specific voltage applied to the array during the erase period depends on the connection between the floating gate and the control gate and the thickness of the gate oxide.

3 is a flow diagram of a programming cycle for one aspect of the present invention. The cycle, at the beginning, reads the selected cell to determine the threshold voltage (V _TH ) (ie, charge on the floating gate) and compares the threshold voltage with V _{TH -TAR} (program verify step 100). Program verification is performed by applying to the selected device a V _CS that is greater than or equal to the desired V _TH of the selected device. If during the program verify step (100), V _TH is lower than the determined V _TH-TAR, the conditions for programming a cell is applied (program step 110). During the programming period, the verify step is performed to check the charge on the floating gate. (1) cycle of the program verification, and (2) program is continued until the V _TH of the device is equal to the V _TH-TAR or exceeds V _TH-TAR. In step 120, it is determined during the program verify period that the device V _TH is _greater than or _equal to V _TH -TAR, and another cell for programming is selected.

The steps of the cycle described in FIG. 3 may be applied simultaneously to one or more cells on a given word line. However, the steps of the cycle cannot be executed simultaneously on cells on different word lines of the same array.

The condition under which the device is read during the cycle period described in FIG. 3 will depend on the programming conditions. If the device is programmed with V _CS and V _DS greater than zero and zero substrate bias (V _BS ), program verification is performed using V _CS equal to or greater than the desired V _TH . V _DS for the program-verify period is lower than would V _DS for programming _{(0 ≤V DS ≤1.5), V} BS is zero.

If the device is programmed with V _CS and V _DS greater than zero and a negative substrate bias (e.g., V _BS is less than -0.5V), the readout verification requires the desired V _TH and body effect shift (γ (V _BS). This is done using a larger V _CS than the sum of)). Body effect shift is a threshold voltage shift caused by a negative substrate bias as determined by a given sensing technique. Since this threshold voltage shift is uniform for all devices in the array, the device is read by applying a larger V _CS than the sum of V _TH and the body effect, where the same value of the body effect shift is used for all cells. The V _BS during the program verification period is the same as the V _BS during the programming period.

In some embodiments of the invention, it is advantageous to apply a negative V _CS to all other word lines of the array. Referring to the array shown in FIG. 2, a negative V _CS is applied only to the word line 180 to which the selected device 181 is not connected. The advantage provided by applying negative V _CS to a cell excluded from selection (ie, correct program or verification) is obtained regardless of whether V _BS is zero or negative.

In the flow diagram shown in FIG. 3, the device is read verified before programming. In an alternative embodiment, the device is not program verified until programmed for some selected time interval.

The flow diagram of the erase cycle of the present invention is illustrated in FIG. 4. The cycle begins by putting all the cells in the array under conditions that erase the charge from the floating gate, causing the floating gate to be more positively charged (step 200). Appropriate conditions for erasing an array of memory cells are summarized in Table 1. After the cells are erased, verify step 210 is performed separately for each cell to determine the charge on the floating gate.

In one embodiment of the erase verify cycle of the present invention, the verify step is performed by applying a negative V _BS to all cells (negative V _BS is not used to erase the array). If the verification is performed using a negative V _BS , the V _CS applied to the selected cell during the verification phase is equal to the sum of V _TH-TAR and γ (V _BS ). In this embodiment, during the read verify period, V _CS applied to the cell excluded from selection is zero. Applying a negative V _BS to the cells being read during the read verify period causes any over erased cells to be read "on" if those over erased cells are to be read "off". It won't provide as many bit line leakages as you can. Regardless of whether a negative V _BS is used to program the cell, the negative V _BS is applied during the erase verify period. Since the array is not erased one by one but all are erased at the same time, switching cells between an erase condition and a negative V _BS for erase verification does not consume much time and quantity (the cells are programmed without a negative V _BS and then As in the case of verification using negative V _BS ). In the second embodiment of the erase verify cycle, the same V _CS as V _TH-TAR (erasure) is applied to the device selected in the erase verify phase and a negative V _CS is applied to the device excluded from erasure during the erase verify phase. In the third embodiment, a negative V _BS is applied to both the selected cell and the cell excluded from the selection during the erase verify period, and the same V _CS as V _TH-TAR + γ (V _BS ) is applied to the selected device. V _{CS of} is applied to the device excluded from the selection.

During the erase verify step of the erase cycle, if it is determined that the one or more devices of the array V _TH is greater than V _TH-TAR (erase), an array is a little more erase. Periodically during the erase period, an erase verify step is performed to check the charge on the floating gate. In the (1) erase and (2) erase verify cycles, the V _TH of all devices in the array is V _TH-TAR (erased; in general, V _TH-TAR in the erase situation is lower than V _TH-TAR in the program situation. Continue until lower than). During the erase verify step, the V _TH of all of the cells in the array, the erase is completed when the same determines that the V _TH-TAR (erase). The erase cycle begins with erase followed by erase verification. In contrast to the programming cycle, the order of the erase and read verify steps is not actually reversed.

In the present invention, the V _TH-TAR used for erasure verification is not required to be the same as the V _TH-TAR for program verification. In some embodiments, V _TH-TAR (erasure) is at least 1 volt lower than V _TH-TAR (program). This guarantees a threshold voltage margin between the 0 and 1 states. In general, during a normal read operation (distinguish from the verify operation during the programming or erase period), V _CS will be approximately 1/2 of (V _TH-TAR (erase) + V _TH-TAR (write)). V _TH-TAR is always greater than zero.

Example 1

V _TH of individual devices in the array of stacked gate devices was determined. The array was 256 devices * 256 devices. The device is a stacked gate EEPROM device. The device has a channel length of 0.48 microns. Function as the V _TH of the substrate bias (V _TH (V _BS)) of each cell was measured as follows. First, the cells were read individually with V _BS = 0. A given cell was chosen to read by applying V _DS = 0.8 and with various values of V _CS (indexed to n, ie V _CS (n)) in 50 mV increments from 2V to 6V. V _TH (0) of a given cell was determined to be the lowest value of V _CS (n) in which the cell is read “on” by the sense amplifier connected to the selected bit line. When the V _BS of the cells of the array is -0.5V, -1V, -1.5V, -2V, the V _TH of each cell is again determined by the above-described procedure, so that V _TH (-0.5), V _TH (- 1), V _TH (-1.5) and V _TH (-2). The body effect shift γ (V _BS ) of the cell was determined as V _TH (V _BS ) -V _TH (0).

5 illustrates the number of cells in an array where a given body effect shift is 50 mV apart. The body effect shift voltages for all devices in the array with V _BS of -0.5V and -1V are within two 50mV intervals. The body effect shift voltages for both devices of the array to which V _BS of -1.5 V and -2 V are applied are within three 50 mV intervals. FIG. 5 shows that for a given negative V _BS , the body effect shift with respect to the threshold voltage of the device has little change between devices in the array of devices. Thus, Figure 5 (V _BS = 0 under the normal read V _TH-TAR in) when the V _TH of the cell to be read as V _BS <0 his V _TH is V _TH-TAR + γ (V _BS) ━ where γ (V _BS ) is determined by verifying that it is a single value selected for all cells of the entire array.

As described above, according to the present invention, the present invention provides a process for programming or verifying a program or erase of a stacked gate memory device of a NOR array.

Claims (28)

A process for changing charge on a floating gate of a plurality of stacked-gate memory devices of a NOR array, At least one device is a selected device of the device array, and other devices other than the selected device of the array are deselected devices, and for n-channel devices, V _BS of 0 or less for the selected device and the deselected device, A V _CS of 0 or less is applied to a device excluded from the selection, and at least one of the V _BS and V _CS is lower than 0, and a p channel device has a V _BS of 0 or more to the selected device and the device excluded from the selection. _Apply zero or more V _CS to a device excluded from the selection, wherein at least one of V _BS and V _CS is greater than zero, such that V _TH of one or more devices on a selected word line of the device array is greater than a target threshold voltage. Verifying high or low, If the V _TH of the device is lower or higher than the target threshold voltage, causing the selected device to comply with conditions that change the charge on the floating gate. The method of claim 1, Wherein the device is n-channel, V _BS is less than zero, V _CS that is applied to the device, except in the selection is equal to zero and the V _CS applied to the selected device during the verify period, the target threshold voltage with body effect Charge change process equal to the sum of the shifts. Claim 3 was abandoned when the setup registration fee was paid. The method of claim 2, Determining a body effect shift for a device in the device array. Claim 4 was abandoned when the registration fee was paid. The method of claim 1, The device is n-channel, the V _BS is zero, the V _CS applied to the device excluded from the selection is less than zero, and the V _CS applied to the selected device is equal to the target threshold voltage. The method of claim 1, Wherein the device is n-channel, the V _BS is less than zero, a V _CS that is applied to the device, except in the selection is less than zero, V _CS that is applied to the selected device during the verify period, the threshold voltage with body effect shift Charge change process equal to the sum of. The method of claim 2, The condition for changing the charge on the floating gate is a negative V _BS for the selected device and the device excluded from the selection, a V _CS greater than 0 for the selected device and a V equal to 0 for the device excluded from the selection. A programming condition comprising applying _CS , the programming condition being applied when V _TH of the device is below the target threshold voltage. Claim 7 was abandoned upon payment of a set-up fee. The method of claim 4, wherein The conditions for changing the charge on the floating gate are: V _BS equal to zero for the selected device and the device excluded from selection, V _CS greater than zero for the selected device, and lower than zero for the device excluded from the selection. Is a programming condition comprising applying V _CS , wherein the programming condition is applied when V _TH of the device is lower than the target threshold voltage. The method of claim 5, wherein Conditions for changing the charge on the floating gate include a negative V _BS for the selected device and the device excluded from selection, a V _CS greater than zero for the selected device, and a V lower than zero for the device excluded from the selection. A programming condition comprising applying _CS , the programming condition being applied when V _TH of the device is below the target threshold voltage. The method of claim 2, The memory device is an EEPROM device, the condition for changing the charge on the floating gate is an erase condition, and the erase condition is applied when V _TH of the device is greater than the target threshold voltage. Claim 10 was abandoned upon payment of a setup registration fee. The method of claim 4, wherein The memory device is an EEPROM device, the condition for changing the charge on the floating gate is an erase condition, and the erase condition is applied when V _TH of the device is greater than the target threshold voltage. Claim 11 was abandoned upon payment of a setup registration fee. The method of claim 5, wherein The memory device is an EEPROM device, the condition for changing the charge on the floating gate is an erase condition, and the erase condition is applied when V _TH of the device is greater than the target threshold voltage. In the process of changing the charge on the floating gate of a plurality of stacked memory devices of a NOR array, One device is a selected device of the device array, and other devices other than the selected device of the array are devices that are excluded from the selection, and for n-channel devices, a V _BS of less than zero is applied to the selected device and the devices that are excluded from the selection. And, for a p-channel device, applying V _BS higher than zero to the selected device and the device excluded from selection, thereby verifying that V _TH of one or more devices on the selected word line of the device array is above or below a target threshold voltage. To do that, If the V _TH of the device is lower or higher than the target threshold voltage, causing the selected device to comply with the condition of changing the charge on the floating gate. The method of claim 12, For an n-channel device, the method further includes applying a V _CS lower than zero to the device excluded from the selection, wherein the V _CS applied to the selected device during the verification period is the sum of the target threshold voltage and the body effect shift. Same charge change process as Claim 14 was abandoned when the registration fee was paid. The method of claim 13, Determining a body effect shift for the device of the device array. Claim 15 was abandoned upon payment of a registration fee. The method of claim 13, V _CS applied to the selected device is equal to the target threshold voltage. Claim 16 was abandoned upon payment of a setup registration fee. The method of claim 12, For a p-channel device, further comprising applying a V _CS equal to zero to the device excluded from the selection, wherein the V _CS applied to the selected device during the verification period is the sum of the target threshold voltage and the body effect shift. Same charge change process as Claim 17 was abandoned upon payment of a registration fee. The method of claim 16, Conditions for changing the charge on the floating gate are negative V _BS for the selected device and the device excluded from the selection, V _CS higher than 0 for the selected device, and V equal to 0 for the device excluded from the selection. A programming condition comprising applying _CS , the programming condition being applied when V _TH of the device is below the target threshold voltage. The method of claim 13, The conditions for changing the charge on the floating gate are negative V _BS for the selected device and the device excluded from the selection, V _CS higher than zero for the selected device, and V lower than zero for the device excluded from the selection. A programming condition comprising applying _CS , the programming condition being applied when V _TH of the device is below the target threshold voltage. The method of claim 13, The memory device is an EEPROM, the condition for changing the charge on the floating gate is an erase condition, and the erase condition is applied when V _TH of the device is higher than the target threshold voltage. Claim 20 was abandoned upon payment of a registration fee. The method of claim 16, The memory device is an EEPROM, the condition for changing the charge on the floating gate is an erase condition, and the erase condition is applied when V _TH of the device is higher than the target threshold voltage. In the process of changing the charge on the floating gate of a plurality of stacked memory devices of a NOR array, At least one device is a selected device of the device array, a device other than the selected device of the array is a device excluded from the selection, and for an n-channel device a V _CS of less than 0 is applied to the device excluded from the selection, and p Verifying, for a channel device, that V _TH of one or more devices on a selected word line of the device array is above or below a target threshold voltage by applying V _CS above zero to the device excluded from the selection; If the V _TH of the device is lower or higher than the target threshold voltage, causing the selected device to comply with the condition of changing the charge on the floating gate. The method of claim 21, For an n-channel device, further comprising applying a negative V _BS to all the devices of the array during the verifying step, wherein V _CS applied to the selected device during the verifying period is equal to the target threshold voltage and the body. Charge change process equal to the sum of the effect shifts. Claim 23 was abandoned upon payment of a set-up fee. The method of claim 22, Determining a body effect shift for the device of the device array. Claim 24 was abandoned when the setup registration fee was paid. The method of claim 21, For an n-channel device, further comprising applying a V _BS equal to zero to all the devices in the array during the verifying step, wherein V _CS applied to the selected device is equal to the target threshold voltage. The method of claim 22, The condition for changing the charge on the floating gate is a programming condition further comprising applying a negative V _BS to the selected device and a device excluded from selection and a V _CS higher than zero to the selected device, wherein the programming condition Is applied when the V _TH of the device is lower than the target threshold voltage. Claim 26 was abandoned upon payment of a registration fee. The method of claim 24, The condition for changing the charge on the floating gate is a programming condition further comprising applying a V _BS equal to 0 to the selected device and a device excluded from selection, and a V _CS higher than 0 to the selected device. Condition is applied when V _TH of the device is lower than the target threshold voltage. The method of claim 22, The memory device is an EEPROM, the condition for changing the charge on the floating gate is an erase condition, and the erase condition is applied when the V _TH of the device is higher than the target threshold voltage. Claim 28 was abandoned upon payment of a registration fee. The method of claim 24, The memory device is an EEPROM, the condition for changing the charge on the floating gate is an erase condition, and the erase condition is applied when the V _TH of the device is higher than the target threshold voltage.

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