KR100548780B1 - Metal pattern fabricating method and electric device fabricating method using thereof - Google Patents

Abstract

The pattern forming method according to the present invention comprises the steps of forming an etch target layer on a substrate, forming an amorphous indium tin oxide (ITO) layer on the etch target layer, and crystallizing a portion of the amorphous ITO layer And etching the amorphous ITO layer to form a crystallized ITO pattern, and etching the etching target layer while blocking the etching target layer with the crystallized ITO pattern.

Pattern, ITO, amorphous, crystal, etching, liquid crystal display, semiconductor device

Description

Pattern Forming Method and Manufacturing Method of Electric Device Using the Same {METAL PATTERN FABRICATING METHOD AND ELECTRIC DEVICE FABRICATING METHOD USING THEREOF}

1 (a) to 1 (f) show a conventional pattern formation method.

2 (a) to 2 (f) are views showing a pattern forming method according to the present invention.

3 (a) to 6 (f) is a method of manufacturing a semiconductor device to which the pattern forming method according to the present invention is applied.

4 is a plan view of a general liquid crystal display device

5 is a cross-sectional view taken along line II ′ of FIG. 6.

6 (a) to 6 (h) illustrate a method of manufacturing a liquid crystal display device to which a pattern forming method according to the present invention is applied.

7 is a cross-sectional view showing the structure of a liquid crystal display device manufactured by the method for manufacturing a liquid crystal display device according to the present invention.

Explanation of symbols on the main parts of the drawings

101 substrate 103 metal layer

107: mask 110: amorphous ITO layer

110: crystal state ITO pattern 353: TFT

354,454 gate electrode 356 source electrode

357: drain electrode 362, 462: gate insulating layer

359: pixel electrode 372: black matrix

374: color filter layer 380: liquid crystal layer

The present invention relates to a pattern forming method, and more particularly, to a pattern forming method and a method for manufacturing an electric device using the same, the process is simple and cost is reduced.

The patterning process of a semiconductor device is not only a factor in determining the characteristics of the device, but also an important factor in determining the performance and capacity of the device. In recent years, various efforts have been made to improve the performance of semiconductor devices. In particular, studies have been actively conducted to improve the performance of semiconductor devices by forming fine metal patterns (circuit patterns).

The pattern forming process is not only in the semiconductor device. The pattern forming process is essentially used in a printed circuit board, a liquid crystal display device, or a flat panel display device such as a plasma display panel (PDP).

Although many studies have been conducted to form a pattern, the most efficient pattern forming process known at present is a process using a photoresist, a photosensitive material, which is illustrated in FIGS. 1 (a) to 1 (f). have.

As shown in FIG. 1A, after the photoresist, which is a photosensitive material, is laminated on the metal layer 3 formed on the substrate 1 made of an insulating material such as glass or a semiconductor material, the photoresist layer 5 is formed. As shown in FIG. 1B, the photoresist layer 5 is baked. Subsequently, as shown in FIG. 1C, after placing a mask on the photoresist layer 5, light such as ultraviolet rays (UV) is irradiated. Typically, the photoresist includes a positive photoresist and a negative photoresist, but only the case where a negative photoresist is used for convenience of description will be described. As the ultraviolet rays are irradiated, the chemical structure of the photoresist in the region irradiated with ultraviolet rays is changed, and when the developer is applied, the photoresist in the region not irradiated with ultraviolet rays is removed, and the photoresist pattern as shown in FIG. (5a) is formed.

As shown in FIG. 1E, when an etching solution is applied while a part of the metal layer 3 is blocked with the photoresist pattern 5a, the remaining portions of the remaining portions except for the lower portion of the photorest pattern 5a may be applied. The metal is removed. Thereafter, as shown in FIG. 1F, when the photoresist pattern 5a is removed by applying a stripper, only the metal pattern 3a remains on the substrate 1.

In the method of forming a metal pattern using the photoresist as described above, the following problems exist.

First, the manufacturing process becomes complicated. As described above, the photoresist pattern is formed through photoresist coating, baking, exposure and development. Therefore, the manufacturing process is complicated. Furthermore, the process becomes more complicated because baking the photoresist requires a soft baking process performed at a specific temperature and a hard baking process performed at a temperature higher than the soft baking temperature.

Second, manufacturing costs will rise. In general, in an electric device process including a plurality of patterns (or electrodes), such as a transistor, a photoresist process is performed to form one pattern, and another photoresist process must be performed to form another pattern. This means that an expensive photoresist process line is required between each pattern line in the manufacturing line. Therefore, the manufacturing cost increases during the manufacture of the electric device. For example, in the manufacture of thin film transistors, the cost of the photoresist process accounts for about 40-45% of the total cost.

Third, it pollutes the environment. In general, since the application of the photoresist is performed by spin coating, many photoresists are discarded during application. The disposal of the photoresist not only increases the manufacturing cost of the electric device but also causes the environment to be contaminated by the discarded photoresist.

Fourth, the failure of electrical appliances. Formation of the photoresist layer by spin coating makes it difficult to control the exact thickness of the layer. Therefore, the photoresist layer is formed unevenly, so that non-stripped photoresist remains on the surface of the pattern when the pattern is formed, which causes a defect in the electric device.

SUMMARY OF THE INVENTION The present invention has been made in view of the above, and after crystallizing a part of amorphous ITO formed on an etch target layer to form a crystallized ITO layer, the pattern of the etch target layer is determined by the difference in etching selectivity between the amorphous state and the crystalline state. An object of the present invention is to provide a pattern forming method for forming a film.

Still another object of the present invention is to provide a method of manufacturing a liquid crystal display device which can simplify the manufacturing process and reduce the manufacturing cost by applying the pattern forming method.

Still another object of the present invention is to provide a method of manufacturing a semiconductor device which can simplify the manufacturing process and reduce the manufacturing cost by applying the pattern forming method.

In order to achieve the above object, the pattern forming method according to the present invention comprises the steps of forming an etching target layer on a substrate, forming an amorphous indium tin oxide (ITO) layer on the etching target layer, the amorphous state ITO Crystallizing a region of the layer, etching the amorphous ITO layer to form a crystallized ITO pattern, and etching the etching target layer while blocking the etching target layer with the crystallized ITO pattern. do.

The amorphous ITO layer is crystallized by rapid heat treatment by irradiating light such as ultraviolet rays, and the etching of the amorphous ITO layer is performed by an etching solution such as oxalic acid or an etching gas such as Cl ₂ gas or Cl ₂ mixed gas.

The etching target layer includes a metal layer, an insulating layer, and a semiconductor layer, and the ITO layer is formed in the same process as the etching target layer, thereby simplifying the manufacturing process and reducing the manufacturing cost.

The method of manufacturing a liquid crystal display device using the pattern forming method includes providing a substrate, forming a gate electrode on the substrate using an indium tin oxide (ITO) layer, and laminating a gate insulating layer on the substrate; Forming a semiconductor layer over the gate insulating layer, forming a source / drain electrode over the semiconductor layer, forming a protective layer over the entire substrate, and stacking a pixel electrode on the protective layer. It consists of.

The forming of the gate electrode may include forming a metal layer on a substrate, forming an amorphous ITO layer on the metal layer, crystallizing a portion of the amorphous ITO layer, and etching the amorphous ITO layer. Forming a crystalline state ITO pattern, and etching the metal layer using the crystalline state ITO pattern.

A semiconductor layer, a source / drain electrode, and a pixel electrode other than the gate electrode may also be formed by a method substantially similar to the above method.

The semiconductor device manufacturing method using the pattern forming method of the present invention includes the steps of laminating an insulating layer on a semiconductor substrate, forming a metal layer on the insulating layer, and an amorphous indium tin oxide (ITO) layer on the metal layer. Forming a crystal layer, forming a crystallized portion of the amorphous ITO layer, etching the amorphous ITO layer to form a crystalline state ITO pattern, and etching a metal layer using the crystalline state ITO pattern to form a gate Forming an electrode, and implanting ions into the semiconductor substrate to form a source / drain region.

In the present invention, a pattern is formed using a metal compound. In the present invention, a transparent metal compound is used instead of a conventional photoresist as a material for blocking the etching target layer to form a pattern. In other words, a desired pattern is formed by forming a metal compound pattern on the etching target layer and performing etching while masking a part of the etching target layer.

In particular, the present invention takes advantage of the properties of metal compounds that change from an amorphous state to a crystallize state as energy is applied. Since the etch selectivity is different with respect to a specific developer or developing gas, the crystalline metal compound and the amorphous metal compound can select an appropriate developer or developing gas to etch a desired substance.

As the metal compound, indium tin oxide (ITO) or indium zinc oxide (IZO) used as a transparent electrode of a flat panel display device is mainly used. In general, ITO (or IZO) maintains an amorphous state, but when energy is applied, it is converted into a crystalline state, especially a poly-cyrstalline state. Since the ITO in the amorphous state and the ITO in the crystalline state have different etching selectivity, it is possible to form a crystalline state ITO pattern or an amorphous ITO pattern by acting a developer having a specific characteristic, and etching using the obtained ITO pattern The target layer can be etched.

The pattern formation method of the present invention as described above can be used to pattern various thin films using an amorphous ITO or a crystalline ITO (in the present invention uses a crystalline ITO) as a masking layer. For example, various electrodes, wirings, insulating patterns, semiconductor patterns, pixel electrodes, etc. of the semiconductor device and the display device may be manufactured by the pattern forming method of the present invention. In this case, the term masking layer means an ITO layer that masks a part of the etching target layer.

Hereinafter, a method of forming a metal pattern according to the present invention will be described in detail with reference to the accompanying drawings.

2 (a) to 2 (f) are views showing a pattern forming method according to the present invention. In this case, the pattern will be described using a metal pattern as an example. Although the pattern actually formed varies, such as a metal pattern, a semiconductor pattern, an insulation pattern, etc., such as an electrode, the figure demonstrates the metal pattern formation method by the example.

As shown in FIG. 2A, a metal layer 103 is formed on a substrate 101 made of an insulating material or a semiconductor material such as glass, and then a metal compound layer 110 such as ITO is formed thereon. The ITO layer 110 is an amorphous layer formed by evaporation or sputtering, and is formed in the same equipment and process (the same conditions and the same atmosphere) as the metal layer 103. Subsequently, as shown in FIG. 2 (b), the rapid thermal annealing is performed by applying light such as ultraviolet rays in a state in which the remaining regions except for the region where the metal pattern is to be formed are blocked by the mask 107. Activation energy is applied to convert the amorphous state into the crystalline state (substantially polycrystalline state), and eventually the ITO layer 110a in the crystalline state is formed in the region where the metal pattern is to be formed as shown in FIG. Is formed.

Thereafter, as shown in FIG. 2 (d), the amorphous ITO layer 100b is removed to form a crystalline state ITO layer 110a, that is, an ITO pattern having a specific shape. Removal of the amorphous ITO layer 100b is performed by a wet etching process or a dry etching process. In the wet etching method, oxalic acid is mainly used as an etchant. Since the etch selectivity of amorphous ITO with respect to oxalic acid is much larger than that of crystalline ITO, amorphous ITO is etched with oxalic acid and is crystallized on metal layer 103 as shown in FIG. 2 (d). Only the state ITO pattern 110a remains.

When using the dry etching method, Cl ₂ gas and the Cl ₂ Since the selection etching of the crystal state ITO for the gas mixture ratio is much lower compared to the etch selectivity of amorphous ITO etching gas is mainly the Cl ₂ gas and the Cl ₂ gas mixture use.

Subsequently, when the metal layer 103 is etched by a wet etching method or a dry etching method, the crystalline state ITO pattern 110a blocks an etching solution (in the case of a wet etching method) or an etching gas (in the case of a dry etching method). As shown in FIG. 2E, the remaining metals except for the metal under the crystalline state ITO pattern 110a are removed. Subsequently, as shown in FIG. 2F, the crystal state ITO pattern 110a is etched to form a desired metal pattern 103a.

In this case, the crystal state ITO pattern 110a may also be etched by a wet etching method and a dry etching method. Although the etch selectivity of the crystalline ITO is lower than that of the amorphous ITO, the crystalline ITO pattern 110a can also be removed by using oxalic acid or Cl ₂ gas, so that the desired metal pattern 103a can be formed. It becomes possible.

As described above, in the pattern formation method of the present invention, the pattern can be formed by the difference in the etching selectivity between the amorphous state ITO and the crystalline state ITO. However, the process of the amorphous state ITO and the crystalline state ITO is mainly performed in a vacuum chamber, and the process of most semiconductor devices or display elements is also performed in the vacuum chamber. Therefore, the processing of the amorphous state ITO and the crystalline state ITO can be performed in the process of the semiconductor element, thereby simplifying the manufacturing process and reducing the cost thereof.

As described above, the pattern forming method based on the difference in etching selectivity between the amorphous state and the crystalline state of ITO has the following advantages over the conventional pattern forming method using a photoresist.

First, the manufacturing process is simplified. In the pattern formation method using the photoresist, baking process (soft baking and hard baking) is required after applying the photoresist, and an ashing process is required even when removing the photoresist, but the amorphous state ITO and the crystalline state In the pattern formation method using ITO, such a process is not necessary and the manufacturing process is simplified.

Second, manufacturing costs are reduced. The photoresist process is a process separate from the process for forming each pattern (for example, a metal pattern, an insulation pattern, and a semiconductor pattern). Therefore, expensive equipment (eg, spin coater) for the photoresist process is required for each process of the electric device manufacturing line. On the other hand, the pattern forming process using the amorphous state ITO and the crystalline state ITO may be performed in the same process as the process of the electric device. For example, when forming a metal pattern, the metal layer, which is an etch target, and the amorphous ITO layer may be formed by the same method (deposition or sputtering) in the vacuum chamber, so that no separate equipment is required. Therefore, the manufacturing cost is greatly reduced as compared with the conventional pattern formation method using the photoresist.

Third, environmental pollution can be reduced. In general, the photoresist is applied to spin coating. By the way, the spin coating method inevitably produces photoresist that is discarded, and the environmental pollution is generated by discarding the photoresist. Moreover, the disposal of the photoresist acts as a cause of raising the manufacturing cost. On the other hand, in the pattern formation method using the amorphous state ITO and the crystalline state ITO, since the disposal of the photoresist as described above does not occur, environmental pollution can be prevented in advance.

The pattern forming method as described above may be used to form all patterns such as metal patterns, insulating patterns, semiconductor patterns, and the like. In addition, this method can be applied to various electric devices, for example, display devices such as semiconductor devices and liquid crystal display devices.

Hereinafter, a method of manufacturing an electric device by applying the pattern forming method of the present invention will be described.

First, a semiconductor device manufacturing method to which a new pattern forming method is applied will be described with reference to FIG. 3.

As shown in FIG. 3A, an insulating layer 262a is stacked on a semiconductor substrate 260 such as a semiconductor wafer, and then a polycrystalline semiconductor layer 254a such as polysilicon (p-Si) is formed thereon. Subsequently, an ITO layer 210 in an amorphous state is formed on the polycrystalline semiconductor layer 254a.

Thereafter, as shown in FIG. 3B, a portion of the amorphous ITO layer 210 is blocked with a mask 207 to irradiate light such as ultraviolet rays to rapidly expose the amorphous ITO layer 210. Heat treatment crystallizes the ITO in the irradiated region to form ITO in a crystalline state (polycrystalline state). An etching solution such as oxalic acid or an etching gas such as Cl ₂ gas or Cl ₂ mixed gas is applied to the amorphous ITO layer 210. Upon action, the amorphous ITO is removed, leaving only the crystalline ITO pattern 210a on the polycrystalline semiconductor layer 254a, as shown in FIG.

When the polycrystalline semiconductor layer 254 is blocked with the crystalline state ITO pattern 205a, an etching solution is applied to etch the insulating layer 262a and the polycrystalline semiconductor layer 254a, and the crystalline state ITO pattern 205a is removed. As shown in FIG. 3D, only the gate insulating layer 262 and the gate electrode 254 thereon remain on the semiconductor substrate 260. Subsequently, as illustrated in FIG. 3E, when the ion is implanted into the semiconductor substrate 260 while the semiconductor substrate 260 is blocked by the gate electrode 254, the semiconductor substrate 260 may be implanted in FIG. As shown in f), the source region 256 and the drain region 257 are formed to complete the semiconductor device.

Meanwhile, the insulating layer 262a and the polycrystalline semiconductor layer 254a may be etched at the same time but may be etched by separate processes. In addition, the insulating layer 262a may be etched after implantation of ions. In this case, the insulating layer 262a serves as a buffer layer to prevent the semiconductor substrate 260 from being affected by ion implantation.

As described above, in the present invention, a semiconductor device is formed by applying a pattern forming method using an etching selectivity difference between an amorphous state and a crystal state of ITO. By applying such a pattern forming method, the overall manufacturing process of the semiconductor device can be simplified and the manufacturing cost thereof can be reduced.

In addition, the pattern formation method of the present invention can be applied to a display device such as a liquid crystal display device, which will be described in detail as follows.

BACKGROUND ART In general, liquid crystal display devices are transmissive flat panel display devices, and are widely applied to various electronic devices such as mobile phones, PDAs, and notebook computers. Such liquid crystal display devices are light and small in size, and can realize high image quality. Therefore, many practical use is being made compared to other flat panel display devices. In addition, as the demand for digital TVs, high-definition TVs, and wall-mounted TVs increases, studies on large-area liquid crystal display devices applicable to TVs are being actively conducted.

In general, the liquid crystal display device can be divided into several methods depending on the method of operating the liquid crystal molecules, but at present the active matrix thin film transistor liquid crystal mainly because of the fast reaction speed and low afterimage Display elements are mainly used.

4 illustrates a structure of the panel 360 of the thin film transistor liquid crystal display. As shown in the figure, the liquid crystal panel 350 has a plurality of gate lines 351 and data lines 352 arranged vertically and horizontally to define a plurality of pixels. Generally, such pixels are formed by N gate lines 351 and M data lines 352, but only one pixel is shown in the figure for convenience of description.

 As shown in the figure, a thin film transistor 353 is disposed in each pixel. The thin film transistor 353 is a gate electrode 354 connected to the gate line 351 and a semiconductor layer 355 formed on the gate electrode 354 and activated when a scan signal is applied to the gate electrode 354. And a source electrode 156 and a drain electrode 357 formed on the semiconductor layer 355. As the semiconductor layer 355 is activated in the display area of the pixel as the semiconductor layer 355 is activated, an image signal is applied through the source electrode 356 and the drain electrode 357 to form a liquid crystal (not shown). An operating pixel electrode 359 is formed, and a black matrix 372 is formed to prevent light from leaking near the thin film transistor 353 and near the gate line 351 and the data line 352. It is.

Hereinafter, the structure of the liquid crystal display device will be described in more detail with reference to FIG. 5.

As shown in the figure, a gate electrode 355 made of metal is formed on the lower substrate 360 made of a transparent insulating material such as glass, and the gate is formed over the entire substrate 360 on which the gate electrode 355 is formed. The insulating layer 362 is laminated. A semiconductor layer 355 is formed on the gate insulating layer 362, and a source electrode 356 and a drain electrode 357 made of metal are formed thereon. A passivation layer 364 is formed over the entire lower substrate 360 on which the source electrode 356 and the drain electrode 357 are formed. A pixel electrode 359 made of a transparent metal such as indium tin oxide (ITO) is formed on the passivation layer 364 to form a TFT 353 through a contact hole 365 formed in the passivation layer 364. It is electrically connected to the drain electrode 357.

In addition, a black matrix 372 is formed on the upper substrate 370, which is a light blocking layer for preventing light from being deteriorated due to leakage of light into an image non-display area of the pixel, that is, between the pixel and the pixel and the TFT area. The color filter layer 374 for real color is formed in the display area. Although not shown, a common electrode made of a transparent metal such as ITO is formed on the color filter layer 374.

As described above, the liquid crystal layer 380 is formed between the lower substrate 360 on which the TFT 353 is formed and the upper substrate 370 on which the color filter layer 374 is formed, thereby completing the liquid crystal display device.

In order to fabricate the liquid crystal display device having the above structure, the process of forming the gate electrode 354, the process of forming the semiconductor layer 355, the process of forming the source electrode 356 and the drain electrode 357, and the formation of the contact hole 365 are performed. A total of five mask processes are required, such as a process of forming a protective film 364 and a process of forming a pixel electrode 359. Therefore, when using a conventional manufacturing method using a photoresist, between the gate metal stacking process and the semiconductor stacking process, between the semiconductor stacking process and the source metal stacking process, between the source metal stacking process and the protective film forming process, the protective film forming process and the pixel electrode A photo process is required between the metal lamination processes and the metal lamination process for pixel electrodes, respectively. Therefore, the manufacturing process becomes complicated and the manufacturing cost increases.

In the present invention, a liquid crystal display device is fabricated by using the pattern forming method shown in Figs. 2 (a) to 2 (f). That is, each pattern is formed by using an etching selectivity between an amorphous state and a crystalline state of a metal oxide such as ITO in each photolithography process. At this time, although ITO can be used entirely to form each pattern, a photoresist and ITO can also be mixed and used. Therefore, in the following description, all the patterns of the liquid crystal display device are formed using ITO, but this is for convenience of description. In the liquid crystal display device manufacturing method of the present invention, substantially all the patterns of the liquid crystal display device are formed using ITO. It may be formed or only a part of the pattern may be formed of ITO, and the rest may be formed using a photoresist.

A method of manufacturing a liquid crystal display device applying the new pattern forming method as described above will be described in detail with reference to FIGS. 6 (a) to 6 (h).

First, as shown in FIG. 6A, a metal layer 354a is formed by stacking a metal such as Al, Al alloy, or Cu on a lower substrate 360 made of a transparent material such as glass, and thereafter, an amorphous state thereon. ITO layer 310 is formed. Subsequently, after the mask 307 is positioned on the ITO layer 310 and subjected to rapid heat treatment by irradiating light such as ultraviolet rays, the amorphous state of the heat-treated region is crystallized. Subsequently, when an etching solution (for example, oxalic acid) or an etching gas (Cl ₂ gas or Cl ₂ mixed gas) is applied, amorphous ITO is removed, and the metal layer 354a is shown in FIG. 6 (b). Likewise, only the ITO pattern 310a in the crystal state remains.

When the etchant is applied while the metal layer 354a is blocked with the crystalline state ITO pattern 310a as described above, the metal layer 354a in the remaining regions except for the blocked region is removed, and the oxalic acid or Cl ₂ gas is used. When the crystalline state ITO pattern 310a is etched, the gate electrode 354 is formed on the lower substrate 360. Subsequently, as shown in FIG. 6C, the gate insulating layer 362 is formed over the entire lower substrate 360 by the chemical vapor deposition (CVD) method, and the semiconductor layer 355a is stacked thereon. The amorphous ITO layer 316 is again formed on the semiconductor layer 355a. When the amorphous ITO layer 316 is blocked using the mask 308 and subjected to rapid heat treatment by irradiating light such as ultraviolet rays, ITO in the heat-treated region is crystallized.

Next, as shown in FIG. 6 (d), when an etching liquid such as oxalic acid or an etching gas such as Cl ₂ or Cl ₂ mixed gas is applied to the ITO layer 306 in which a partial region is crystallized, the semiconductor layer layer 355a Only the ITO pattern 316a in the crystalline state remains. Subsequently, the semiconductor layer 355a is etched with an etching gas while the part of the semiconductor layer 355a is blocked with the crystalline ITO pattern 316a. When the state ITO pattern 316a is removed, the semiconductor layer 355 remains only on the gate electrode 354, as shown in FIG. 6E.

Thereafter, as shown in FIG. 6 (f), a TFT is formed on the semiconductor layer 355 by forming a source electrode 356 and a drain electrode 357 made of metal such as Cr, Mo, Al, Al alloy, and Cu. To complete. Although not shown in the drawing, the source electrode 356 and the drain electrode 357 are also formed by the same process as the gate electrode 354. In other words, the amorphous state ITO is rapidly thermally crystallized, the amorphous state ITO is etched to form a crystalline state ITO pattern, and then the source electrode 356 and the drain electrode 357 are formed by the crystalline state ITO pattern.

As described above, a protective layer 364 is formed on the lower substrate 360 on which the TFT is formed, as shown in FIG. 6G, and a transparent metal is stacked thereon to form a pixel electrode 359. In this case, the pixel electrode 359 is electrically connected to the drain electrode 357 of the TFT through the contact hole 365 formed in the protective layer 364. Patterning of the contact hole 365 and the pixel electrode 359 of the protective layer 364 is also performed by a photolithography process using ITO.

ITO is used as the pixel electrode 359. Accordingly, the pixel electrode 359 made of the crystalline state ITO may be formed by stacking the amorphous state ITO on the protective layer 364 having the contact hole 364 and crystallizing it and then removing the amorphous state ITO. Therefore, no other masking layer is necessary to form the pixel electrode 359.

Subsequently, as shown in FIG. 6 (h), after forming the black matrix 372 made of Cr / CrOx or black resin and forming the color filter layer 374 on the upper substrate 370, the lower substrate 360 is formed. And the upper substrate 370 are bonded together to form a liquid crystal layer 380 therebetween to complete the liquid crystal display device.

As described above, in the present invention, the liquid crystal display device is manufactured by applying the pattern forming method using the etching selectivity of the amorphous state ITO and the crystalline state ITO. By applying such a pattern forming method, the overall manufacturing process of the liquid crystal display device can be simplified and the manufacturing cost thereof can be reduced.

ITO, on the other hand, has conductivity. In particular, when ITO is crystallized, its conductivity is improved. Therefore, in manufacturing the liquid crystal display device, no abnormality occurs in the application or transmission of the signal even without removing the crystal state ITO formed on the metal layer (eg, the gate electrode, the source electrode, and the drain electrode).

7 is a diagram showing the structure of a liquid crystal display device in which the crystal state ITO is not removed. As shown in the figure, a crystallized first ITO layer 474 used as a masking layer is formed on the gate electrode 454 of the TFT, and a crystallized second ITO layer 475 is formed on the semiconductor layer 455. have. In addition, a crystallized third ITO layer 476 is formed on the source electrode 456 and the drain electrode 457. The liquid crystal display device having such a structure is almost the same as the manufacturing method of the liquid crystal display device shown in Figs. 6 (a) to 6 (h), except that it does not remove the crystalline state ITO layer used as the masking layer. It's different. This means that the step of removing the crystalline state ITO layer is omitted in the manufacture of the liquid crystal display device, thus simplifying the manufacturing method of the liquid crystal display device and reducing the manufacturing cost.

In this case, the crystalline state ITO layers 474, 475, 476 need not be formed on the gate electrode 454, the semiconductor layer 455, and the source / drain electrodes 456, 457, and the gate electrode 454, the semiconductor layer 455, It may be formed on one or two patterns of the source / drain electrodes 456 and 457. That is, the desired number of crystal state ITO layers are left as necessary during the manufacturing process of the liquid crystal display device.

As described above, the pattern forming method of the present invention can be usefully used for forming various patterns of a display device or a semiconductor device such as a liquid crystal display device. In addition, although not disclosed in the description, the method of forming a pattern of the present invention may be applied to all electric devices using a metal pattern, an insulation pattern, or the like.

As described above, the pattern forming method according to the present invention uses a metal oxide such as ITO instead of using a conventional photoresist, so that the following effects can be obtained.

First, the manufacturing process is simplified. In the pattern forming method using a photoresist, a baking process (soft baking and hard baking) is required after the photoresist is applied, and an ashing process is required even when the photoresist is removed. In this case, such a process is not necessary and the manufacturing process is simplified.

Second, manufacturing costs are reduced. The photoresist process is a process separate from the process for forming each pattern (for example, a metal pattern, an insulation pattern, and a semiconductor pattern). Therefore, expensive equipment (eg, spin coater) for the photoresist process is required for each process of the electric device manufacturing line. On the other hand, the pattern forming process of the present invention can be carried out in the same process as the process of the electrical device. For example, in the case of forming the metal pattern, the metal layer and the ITO layer, which are food objects, may be formed by the same method (deposition or sputtering) in the vacuum chamber, so that no separate equipment is required. Therefore, the manufacturing cost is greatly reduced as compared with the conventional pattern formation method using the photoresist.                     

Third, environmental pollution can be reduced. In general, the photoresist is applied to spin coating. By the way, the spin coating method inevitably produces photoresist that is discarded, and the environmental pollution is generated by discarding the photoresist. Moreover, the disposal of the photoresist acts as a cause of raising the manufacturing cost. On the other hand, in the present invention, since the disposal of the photoresist as described above does not occur, environmental pollution can be prevented in advance.

Fourth, it is possible to prevent the failure of the electrical element. Photoresists applied by spin coating have difficulty controlling their thickness accurately. Therefore, when the photoresist is unevenly applied, unremoved photoresist remains during the stripping process of the photoresist, which causes pattern defects during the pattern forming process. On the other hand, in the pattern formation method of the present invention, since ITO is laminated by vapor deposition or sputtering, the thickness thereof can be precisely controlled, thereby preventing occurrence of such a pattern defect.

Claims (35)

Forming an etching target layer on the substrate; Forming an amorphous indium tin oxide (ITO) layer on the etching target layer; Crystallizing a portion of the amorphous ITO layer; Etching the amorphous ITO layer to form a crystallized ITO pattern; And And etching the etch target layer in a state in which the etch target layer is blocked with the crystallized ITO pattern. The method of claim 1, wherein the crystallizing of the amorphous ITO layer comprises rapid thermal treatment of a portion of the amorphous ITO layer. The method of claim 2, wherein the rapid heat treatment is performed by irradiating light. The method of claim 3, wherein the light comprises ultraviolet rays. The method of claim 2, wherein the amorphous state of ITO is converted into a polycrystalline state by the rapid heat treatment. The method of claim 1, wherein the etching of the amorphous ITO layer comprises applying an etching solution of oxalic acid to the amorphous ITO layer. The method of claim 1, wherein the etching of the amorphous ITO layer comprises applying an etching gas containing Cl ₂ gas to the amorphous ITO layer. The method of claim 1, wherein the etching of the amorphous ITO layer comprises applying an etching gas including a Cl ₂ mixed gas to the amorphous ITO layer. The method of claim 1, wherein the etching target layer comprises a metal layer, an insulating layer, and a semiconductor layer. The method of claim 1, wherein the amorphous ITO layer is formed in the same process as the etching target layer. The pattern forming method of claim 1, further comprising removing the crystallized ITO pattern. The method of claim 11, wherein removing the crystallized ITO pattern comprises applying oxalic acid to the crystallized ITO pattern. The method of claim 11, wherein removing the crystallized ITO pattern comprises applying a Cl ₂ gas or a Cl ₂ mixed gas to the crystallized ITO pattern. Providing an etching target layer; Forming an amorphous metal compound layer on the etching target layer; Crystallizing a portion of the amorphous metal compound layer to form a crystalline metal compound layer; Etching the amorphous metal compound layer; And Etching the etching target layer using a crystalline state metal compound layer. The method of claim 14, wherein the metal compound layer is made of indium tin oxide (ITO) or indium zinc oxide (IZO). The method of claim 14, wherein etching the amorphous metal compound comprises applying an etching solution or an etching gas to the amorphous metal compound. The method of claim 16, wherein an etching selectivity of the etching liquid or the etching gas with respect to the amorphous metal compound is greater than that of the crystalline metal compound layer. Providing a substrate; Forming a gate electrode on the substrate using an indium tin oxide (ITO) layer as a mask; Stacking a gate insulating layer on the substrate; Forming a semiconductor layer over the gate insulating layer; Forming a source / drain electrode on the semiconductor layer; Forming a protective layer over the substrate; And And forming a pixel electrode on the passivation layer. The method of claim 18, wherein the forming of the gate electrode comprises: Forming a metal layer on the substrate; Forming an amorphous ITO layer on the metal layer; Crystallizing a portion of the amorphous ITO layer; Etching the amorphous ITO layer to form a crystalline ITO pattern; And And etching the metal layer using the crystal state ITO pattern. The method of claim 18, wherein the forming of the semiconductor layer comprises: Stacking a semiconductor layer over the gate insulating layer; Forming an amorphous ITO layer on the semiconductor layer; Crystallizing a portion of the amorphous ITO layer; Etching the amorphous ITO layer to form a crystalline ITO pattern; And And etching the semiconductor layer using the crystal state ITO pattern. The method of claim 18, wherein the forming of the source / drain electrode comprises: Forming a metal layer over the semiconductor layer; Forming an amorphous ITO layer on the metal layer; Crystallizing a portion of the amorphous ITO layer; Etching the amorphous ITO layer to form a crystalline ITO pattern; And And etching the metal layer using the crystal state ITO pattern. The method of claim 18, wherein the forming of the pixel electrode comprises: Forming an amorphous ITO layer over the protective layer; Crystallizing a portion of the amorphous ITO layer; And A method of manufacturing a liquid crystal display device, comprising the step of etching an amorphous ITO layer. 22. The method of any one of claims 19 to 21, further comprising removing the crystalline state ITO pattern. 23. The method of any one of claims 19 to 22, wherein the crystallizing the amorphous ITO layer comprises rapidly heat treating the amorphous ITO layer. 25. The method of claim 24, wherein the rapid heat treatment is performed by irradiation of light. 23. The method of any one of claims 19 to 22, wherein etching the amorphous ITO layer comprises acting oxalic acid on the amorphous ITO layer. 23. The method of any one of claims 19 to 22, wherein etching the amorphous ITO layer comprises applying a Cl ₂ gas or a Cl ₂ mixed gas to the amorphous ITO layer. Stacking an insulating layer on the semiconductor substrate; Forming a metal layer on the insulating layer; Forming an amorphous indium tin oxide (ITO) layer on the metal layer; Crystallizing a portion of the amorphous ITO layer; Etching the amorphous ITO layer to form a crystalline ITO pattern; Etching a metal layer using the crystal state ITO pattern to form a gate electrode; And Forming a source / drain region by implanting ions into the semiconductor substrate. 29. The method of claim 28, wherein crystallizing the amorphous ITO layer comprises rapidly heat treating the amorphous ITO layer. 30. The method of claim 29, wherein the rapid heat treatment is performed by irradiation of light. 29. The method of claim 28, wherein etching the amorphous ITO layer comprises applying oxalic acid to the amorphous ITO layer. The method of claim 28, wherein etching the amorphous ITO layer comprises applying a Cl ₂ gas or a Cl ₂ mixed gas to the amorphous ITO layer. 29. The method of claim 28, wherein ions are implanted through an insulating layer formed on the semiconductor substrate. 29. The method of claim 28, wherein the insulating layer is etched simultaneously with the metal layer. 35. The method of claim 34, wherein ions are implanted directly into the semiconductor substrate.

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