KR100548539B1 - High-speed low-voltage sense amplifier - Google Patents

Abstract

The present invention relates to a sense amplifier capable of high-speed operation by generating a normal amplified signal even in a low voltage condition with a low power supply voltage by presetting the PMOS transistor of the sense amplifier in advance before the sense amplifier operates.

According to an aspect of the present invention, there is provided a sense amplifier capable of generating a normal amplified signal even at a low voltage, and capable of high-speed operation, comprising: a first sense amplifier configured to generate a first output signal by sensing and amplifying an input signal; A second sense amplifier comprising a PMOS transistor and an NMOS transistor to sense and amplify an input signal to generate a second output signal; A third sense amplifier for amplifying the output signals of the first and second sense amplifiers again; And presetting means for presetting the PMOS transistors of the plurality of sense amplifiers before operation of the plurality of sense amplifiers.

Description

High-speed low-voltage sense amplifier

1 is a circuit diagram of a conventional current mirror type sense amplifier,

2 is a circuit diagram of a current mirror type sense amplifier according to an embodiment of the present invention;

3A and 3B are diagrams for simulating an output voltage when a power supply voltage is 1.5 volts and 1.3 volts, respectively, in a conventional current mirror type sense amplifier.

4A and 4B are diagrams for simulating output voltages when the power supply voltages are 1.5 volts and 1.3 volts in the current mirror type sense amplifier of the present invention.

(Name of the code for the main part of the drawing)

10, 20, 30: sense amplifier 40: preset means

P1, ..., P8: PMOS transistor N1, ..., N12: NMOS transistor

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a sense amplifier, and more specifically, by presetting a transistor used as a load element of a sense amplifier in a pre-operation state to a high speed even in a low voltage state with a low power supply voltage. A sense amplifier is operable.

Recently, memory devices have been pursued to enable high-speed operation while using low voltage. In particular, in the case of a sense amplifier that senses and amplifies two voltage differences, a sensed minute voltage difference is detected and a signal having a large voltage difference is output. It is required to perform a sense amplification operation normally even in a low voltage state with a low power supply voltage. have. However, a general sense amplifier may not perform an amplification operation properly at a voltage lower than 1.5 volts.

1 illustrates a conventional current mirror type sense amplifier. Referring to FIG. 1, a conventional current mirror type sense amplifier includes first and second sense amplifiers 10 and 20 for firstly sensing and amplifying an input signal sai and saib and the first amplified signal sa1o. , sa1ob) consists of a third sensing amplification unit 30 for amplifying secondarily.

The first sensing amplifier 10 includes current mirror type first and second PMOS transistors P1 and P2 having a source connected to a power supply voltage, and a drain of the PMOS transistors P1 and P2. A drain is connected to the first and second NMOS transistors N1 and N2 connected to the drain, and a source of the NMOS transistors N1 and N2, and a source is connected to ground, so that the first sense amplifier enable signal pse1i is connected. It consists of the 3rd NMOS transistor N3 which makes into an input. When the first sense amplifier enable signal pse1i is applied in a high state, the first sense amplifier 10 generates an output signal sa1o to the drain of the second NMOS transistor N2 by performing an amplification operation. .

The second sense amplifier 20 has the same configuration and operation as the first sense amplifier 10 and outputs the signal sa1ob at the drain of the NMOS transistor N4 that receives the first input signal sai as an input. Will occur).

Output signals sa1o and sa1ob of the first and second sense amplifiers 10 and 20 are fifth PMOSs for controlling output signals sa1o and sa1ob of the first and second sense amplifiers 10 and 20. The first sense amplifier enable signal pse1i is connected to a gate of the fifth PMOS transistor P5. The first sense amplifier enable signal pse1i is connected to the drain and the source of the transistor P5, respectively. At this time, when the first sense amplifier enable signal pse1i is applied in a low state, the fifth PMOS transistor P5 is turned on to output the output signals of the first and second sense amplifiers 10 and 20. When the first sense amplifier enable signal pse1i is applied in a high state by equalizing, the fifth PMOS transistor P5 is turned off so that the amplification operation is not performed. The signal amplified by the sense amplifiers 10 and 20 is provided to the third sense amplifier 30.

The third sensing amplifier 30 has current mirror type sixth and seventh PMOS transistors P6 and P7 having a source connected to a power supply voltage, and a drain connected to drains of the PMOS transistors P6 and P7, respectively. The seventh and eighth NMOS transistors N7 and N8 receiving the output signals sa1o and sa1ob of the first and second sense amplifiers 10 and 20 and the drains of the sources of the NMOS transistors N7 and N8. Is connected, the source is connected to ground, and is made up of a ninth NMOS transistor N9 having the second sense amplifier enable signal pse2i as an input. When the second sense amplifier enable signal pse2i is applied in a high state, the third sense amplifier 30 turns on the ninth NMOS transistor N9 to perform an amplification operation and performs an amplification operation. The output signal sa2o is generated as the drain of N8).

The output signal sa2o of the third sense amplifier 30 is connected to the drain of the eighth PMOS transistor P8 for controlling the output signal of the third sense amplifier 30, and a ground power source is connected to the source. The second sense amplifier enable signal pse2i is applied to the gate. When the second sense amplifier enable signal pse2i is applied in a high state, the eighth PMOS transistor P8 is turned off to output an amplified signal from the third sense amplifier 30 and a second sense. When the amplifier enable signal pse2i is applied in a low state, the eighth PMOS transistor P8 is turned on to output a power supply voltage in a high state, thereby preventing amplification.

However, in the sense amplifier as described above, when the power supply voltage is operated at a low voltage of 1.5 volts or less, the output signal is delayed or the output signal is properly generated and malfunctions are often caused.

3A and 3B show output waveforms when the power supply voltage is 1.5 volts and 1.3 volts in the conventional sense amplifier. 3A and 3B illustrate a case in which the first input signal sai decreases with a slope of about 10 mV / ns among the first and second input signals sai and saib.

Referring to FIG. 3A, the first and second input signals sai and saib differ by about 20 mV at 31 ns when the first sense amplifier enable signal pse1 transitions to a high state. In the initial stage of the sense amplification by the first sense amplifier enable signal pse1, the output signal sa1o of the first sense amplifier 10 swings at a relatively low voltage, and the second sense amplifier ( The output signal sa1ob of 20 swings at a relatively high voltage.

The output signal sa2o of the third sense amplifying unit 30 that receives the output signals sa1o and sa1ob falls with a delay time of about 9 ns (40 ns-31 ns), which is the second sense amplification. It is determined according to the time when the output signal sa1ob of the unit 20 rises. This is because the third sense amplifier only after the output signals of the first and second sense amplifiers 10 and 20 rise above the threshold voltages of the NMOS transistors N7 and N8 of the third sense amplifier 30. This is because the amplification operation is performed at 30.

On the other hand, the output signal sa1ob of the second sense amplifier 20 is raised when the third and fourth PMOS transistors P3 and P4 are turned on. That is, the output signal sa1ob rises when the gate signals Vgp of the third and fourth PMOS transistors P3 and P4 become Vcc-Vtp or less. Vtp is the threshold voltage of the PMOS transistor.

Accordingly, in order to reduce the delay time and output the output signal sa2o of the third sense amplifier 30 at high speed, the PMOS transistors P1, ..., ... of the first and second sense amplifiers 10 and 20 are output. It is necessary to turn on P4) quickly.

Figure 3b shows the output waveform of a conventional sense amplifier when the power supply voltage is 1.3 volts. Referring to FIG. 3B, the rise time of the output signal sa1ob of the second sense amplifier 20 is slowed, so that the output signal sa2o of the third sense amplifier 30 fails to output low data. You can see that.

SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and the object of the present invention is to provide a high speed low voltage sense amplifier capable of high speed operation even at low voltage and no malfunction by presetting the gate of the PMOS transistor of the sense amplifier.

In order to achieve the above object of the present invention, the present invention is characterized in that it comprises a preset means for presetting the gate of the PMOS transistor constituting the sense amplifier before operation of the sense amplifier to the operating state in advance.

The preset means includes a plurality of NMOS transistors configured to receive a preset input signal before the sense amplifier operates to preset a gate of the PMOS transistor of the sense amplifier, and the NMOS in the same structure as a common current source of the sense amplifier. And a current source connected to the source of the transistor.

Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.

2 illustrates a sense amplifier according to an embodiment of the present invention. Referring to FIG. 2, the apparatus may further include preset means 40 for presetting PMOS transistors of a plurality of sense amplifiers in a conventional current mirror type sense amplifier.

The preset means 40 is configured to preset the NMOS transistors N10 and N11 of the PMOS transistors P1,..., And P4 of the first and second sense amplifiers 10 and 20 according to a preset input signal Vgset. ) And an NMOS transistor N12 connected to the sources of the NMOS transistors N10 and N11 in the same structure as the current sources N3 and N6 of the first and second sense amplifiers 10 and 20. In this case, the twelfth NMOS transistor N12 is configured to have the same structure as the current source of the sense amplifier. When the structure of the current source of the sense amplifier is changed, the structure of the NMOS transistor N12 is also changed accordingly. In the above, the preset means are shown in the current mirror type sense amplifier shown in FIG.

4A and 4B show an output waveform when the power supply voltage is 1.5 volts and 1.3 volts in the sense amplifier according to the embodiment of the present invention, respectively.

Referring to FIG. 4A, a preset input signal Vgset is applied as a pulse prior to the operation of the sense amplifier, so that the gates Vgp and Vgpb of the PMOS transistor of the sense amplifier drop by a threshold voltage Vtp = about 0.8 volts, thereby providing 1.5 volts. You can see that it is preset to 0.8 volts = 0.7 volts.

Therefore, when the first sense amplifier enable signal pse1i transitions to a high state, the PMOS transistors P1,..., P4 of the sense amplification unit are turned on immediately, and the second sense amplifier 20 The output signal sa1ob can be operated at a high speed by turning on the NMOS transistor N8 of the third sensing amplifier 30 faster than the conventional sense amplifier (9 ns) (6.2 ns).

When the power supply voltage is 1.3 volts, the conventional sense amplifier has a slow rise time of the output signal sa1ob of the second sense amplifier 20 so that the normal amplification is not performed in the third sense amplifier 30. As a result, the output of the low state data has failed, but referring to FIG. 4B, in the sense amplifier of the present invention, the PMOS transistors P1,..., P4 of the first and second sense amplifiers 10, 20 are provided. It can be seen that the third sense amplifier 30 generates a normal amplified signal sa2o in a low state even when the voltage is preset to a low voltage of 1.5 volts or less. In particular, FIG. 4B shows that the output signal sa2o occurs only after 10.7 ns after the first sense amplifier enable signal pse1i transitions to a high state.

As described in detail above, according to the high speed low voltage sense amplifier of the present invention, by presetting the PMOS transistor of the sense amplifier before the sense amplifier performs an amplification operation, an output signal is generated at a high speed, and the power supply voltage is 1.5. It will output normal amplified signal even at low voltage below volt.

Hereinafter, this invention can be implemented in various changes in the range which does not deviate from the summary.

Claims (3)

A sense amplifier for sensing and amplifying an input signal and outputting the same, A first sense amplifier 10 comprising a PMOS transistor and an NMOS transistor for sensing and amplifying an input signal to generate a first output signal sa1o; A second sense amplifier 20 comprising a PMOS transistor and an NMOS transistor to sense and amplify an input signal to generate a second output signal sa1ob; Amplifying the output signals sa1o and sa1ob which are connected to the first and second sense amplifiers 10 and 20 and applied from the first and second sense amplifiers 10 and 20. Third sensing amplifier for 30 and, Connected to the first and second sense amplifiers 10 and 20, and before the first and second sense amplifiers 10 and 20 operate, the first and second sense amplifiers 10 and 20 A high speed low voltage sense amplifier, comprising preset means (40) for presetting PMOS transistors (P1, P2) (P3, P4). The method according to claim 1, wherein the preset means (40) A drain is connected to each gate of the PMOS transistors P1, P2, P3, and P4 constituting the first and second sense amplifiers 10 and 20, respectively, and receives a preset input signal to sense the first and second senses. NMOS transistors N10 and N11 for presetting the PMOS transistors P1 and P2 (P3 and P4) before the amplifiers 10 and 20 operate; A high speed and low voltage connected to the sources of the NMOS transistors N10 and N11 and having the same structure as that of the current sources of the first and second sense amplifiers 10 and 20 and always being turned on. Sense amplifier. 3. The current source of the preset means 40 according to claim 2, wherein In the case of the current mirror sense amplifier, The drain is connected to the source of the NMOS transistors N10 and N11 of the preset means 40 for presetting the PMOS transistors P1 and P2 (P3 and P4) of the first and second sense amplifiers 10 and 20. , The source is connected to ground power, A high speed low voltage sense amplifier, characterized in that the gate consists of an NMOS transistor (N12) connected to the supply voltage and always turned on.

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