KR100546287B1 - Manufacturing method of semiconductor device having copper pad - Google Patents

Manufacturing method of semiconductor device having copper pad Download PDF

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KR100546287B1
KR100546287B1 KR1019990010803A KR19990010803A KR100546287B1 KR 100546287 B1 KR100546287 B1 KR 100546287B1 KR 1019990010803 A KR1019990010803 A KR 1019990010803A KR 19990010803 A KR19990010803 A KR 19990010803A KR 100546287 B1 KR100546287 B1 KR 100546287B1
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copper
layer
semiconductor substrate
semiconductor device
material layer
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KR1019990010803A
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Korean (ko)
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KR20000061632A (en
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권동철
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삼성전자주식회사
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76886—Modifying permanently or temporarily the pattern or the conductivity of conductive members, e.g. formation of alloys, reduction of contact resistances
    • H01L21/76889—Modifying permanently or temporarily the pattern or the conductivity of conductive members, e.g. formation of alloys, reduction of contact resistances by forming silicides of refractory metals
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material

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  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

본 발명은 반도체 기판 상에 콘택홀을 갖는 층간 절연막을 형성한 후, 상기 콘택홀에 매몰되는 구리층을 형성한다. 상기 구리층이 형성된 반도체 기판의 전면에 상기 구리층과 반응하여 합금을 형성할 수 있게 알루미늄 또는 실리콘으로 이루어진 물질층을 형성한다. 상기 구리층 상에 물질층이 형성된 반도체 기판을 어닐링을 실시하여 Al2Cu 또는 구리 실리사이드로 이루어진 구리 합금으로 보호층을 형성한다. 상기 층간 절연막 상에 형성된 물질층을 제거하여 상기 구리층 및 보호층으로 이루어진 구리 패드를 형성한다. 이와 같이 제조되는 본 발명의 반도체 소자의 구리 패드는 표면에 보호층이 형성되어 산화를 방지할 수 있다.The present invention forms an interlayer insulating film having a contact hole on a semiconductor substrate, and then forms a copper layer buried in the contact hole. A material layer made of aluminum or silicon is formed on the entire surface of the semiconductor substrate on which the copper layer is formed to react with the copper layer to form an alloy. The semiconductor substrate having the material layer formed on the copper layer is annealed to form a protective layer using a copper alloy made of Al 2 Cu or copper silicide. The material layer formed on the interlayer insulating film is removed to form a copper pad made of the copper layer and the protective layer. In the copper pad of the semiconductor device of the present invention manufactured as described above, a protective layer is formed on a surface thereof to prevent oxidation.

Description

구리 패드를 갖는 반도체 소자의 제조방법{Manufacturing method of semiconductor device having copper pad}Manufacturing method of semiconductor device having copper pad

도 1은 본 발명에 의해 제조된 구리 패드를 갖는 반도체 소자를 설명하기 위하여 도시한 단면도이다.1 is a cross-sectional view for explaining a semiconductor device having a copper pad manufactured by the present invention.

도 2 내지 도 4는 본 발명에 의한 구리 패드를 갖는 반도체 소자의 제조 방법을 설명하기 위하여 도시한 단면도들이다.2 to 4 are cross-sectional views illustrating a method of manufacturing a semiconductor device having a copper pad according to the present invention.

본 발명은 반도체 소자의 제조 방법에 관한 것으로, 보다 상세하게는 구리 패드를 갖는 반도체 소자의 제조방법에 관한 것이다. The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method for manufacturing a semiconductor device having a copper pad.

일반적으로, 반도체 소자 중에서 높은 속도가 요구되어지는 로직 소자를 중심으로 해서 비저항이 낮고 EM(electromigration)특성을 개선시킬 수 있는 구리 금속을 배선층으로 이용하는 방법이 연구되고 있다. 그런데, 상기 구리 금속을 이용하여 배선층을 형성할 경우, 구리 금속의 부식으로 인한 구리 금속의 식각 어려움 때문에 콘택홀의 매몰과 구리 배선층을 동시에 형성하는 소위, "다마슨(Damascene)" 공정을 이용하여 구리 배선층을 형성한다. In general, a method of using a copper metal as a wiring layer, which has a low specific resistance and can improve EM (electromigration) characteristics, focusing on a logic device requiring a high speed among semiconductor devices. However, when the wiring layer is formed using the copper metal, copper is formed by using a so-called “Damascene” process in which a buried contact hole and a copper wiring layer are simultaneously formed due to the difficulty of etching the copper metal due to the corrosion of the copper metal. A wiring layer is formed.

또한, 상기 구리 금속을 배선층으로 이용할 경우 구리 금속층이 산화하는 문제점이 있다. 즉, 구리 금속층은 일반적으로 사용되는 알루미늄층과는 달리 산화가 계속적으로 일어난다. 특히, 전기적 특성 분석을 위하여 반드시 오픈되어 있는 구리 패드가 산화되면 여러 가지 전기적 특성 뿐만 아니라 EM측정시 많은 오차가 발생할 가능성이 있다. 따라서, 반도체 소자의 구리 패드의 산화를 방지하는 기술이 필요하다. In addition, when the copper metal is used as a wiring layer, there is a problem that the copper metal layer is oxidized. That is, the copper metal layer is continuously oxidized unlike the aluminum layer generally used. In particular, if the copper pad, which is necessarily open for electrical characterization, is oxidized, there are possibilities of many errors in EM measurement as well as various electrical characteristics. Therefore, a technique for preventing oxidation of the copper pad of the semiconductor element is needed.

따라서, 본 발명이 이루고자 하는 기술적 과제는 산화를 방지할 수 있는 구리 패드를 갖는 반도체 소자의 제조 방법을 제공하는 데 있다. Accordingly, an object of the present invention is to provide a method for manufacturing a semiconductor device having a copper pad capable of preventing oxidation.

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상기 기술적 과제를 달성하기 위하여, 본 발명의 반도체 소자의 제조방법은 반도체 기판 상에 콘택홀을 갖는 층간 절연막을 형성하는 단계와, 상기 콘택홀에 매몰되는 구리층을 형성하는 단계와, 상기 구리층이 형성된 반도체 기판의 전면에 상기 구리층과 반응하여 합금을 형성할 수 있게 알루미늄 또는 실리콘으로 이루어진 물질층을 형성하는 단계와, 상기 구리층 상에 물질층이 형성된 반도체 기판을 어닐링을 실시하여 Al2Cu 또는 구리 실리사이드로 이루어진 구리 합금으로 보호층을 형성하는 단계와, 상기 층간 절연막 상에 형성된 물질층을 제거하여 상기 구리층 및 보호층으로 이루어진 구리 패드를 형성하는 단계를 포함하여 이루어진다. 상기 물질층은 알루미늄 또는 실리콘을 이용하여 100∼200Å의 두께로 형성할 수 있다.
이상과 같은 본 발명의 반도체 소자의 구리 패드는 표면에 보호층이 형성되어 산화를 방지할 수 있다.In order to achieve the above technical problem, a method of manufacturing a semiconductor device of the present invention comprises the steps of forming an interlayer insulating film having a contact hole on the semiconductor substrate, forming a copper layer buried in the contact hole, and the copper layer to the front semiconductor substrate having a step, and a material layer on the copper layer to form a layer of a material consisting of aluminum or silicon can be formed the alloy reacts with the copper layer on the formed semiconductor substrate subjected to the annealing Al 2 Forming a protective layer from a copper alloy made of Cu or copper silicide, and removing a material layer formed on the interlayer insulating film to form a copper pad made of the copper layer and the protective layer. The material layer may be formed to a thickness of 100 ~ 200Å using aluminum or silicon.
In the copper pad of the semiconductor device of the present invention as described above, a protective layer is formed on a surface thereof to prevent oxidation.

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이하, 첨부 도면을 참조하여 본 발명의 실시예를 상세히 설명한다.Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.

도 1은 본 발명에 의해 제조된 구리 패드를 갖는 반도체 소자를 설명하기 위하여 도시한 단면도이다. 1 is a cross-sectional view for explaining a semiconductor device having a copper pad manufactured by the present invention.

구체적으로, 본 발명에 의해 제조된 반도체 소자는 반도체 기판(1) 상에 콘택홀을 갖는 층간 절연막(3)이 형성되어 있다. 상기 콘택홀에는 매몰되는 구리 패드가 형성되어 있다. 그런데, 본 발명의 구리 패드는 구리층(5)과 그 상부 표면에 형성된 보호층(9)으로 구성된다. 본 실시예에서, 상기 보호층(9)은 Al2Cu 또는 구리 실리사이드로 구성한다. 특히, 본 발명에 의해 제조된 반도체 소자의 구리 패드는 상기 보호층(9)으로 인하여 산화를 방지할 수 있다.Specifically, in the semiconductor device manufactured by the present invention, an interlayer insulating film 3 having a contact hole is formed on the semiconductor substrate 1. Copper pads are buried in the contact holes. By the way, the copper pad of this invention consists of the copper layer 5 and the protective layer 9 formed in the upper surface. In this embodiment, the protective layer 9 is composed of Al 2 Cu or copper silicide. In particular, the copper pad of the semiconductor device manufactured by the present invention can prevent oxidation due to the protective layer (9).

도 2 내지 도 4는 본 발명에 의한 구리 패드를 갖는 반도체 소자의 제조 방법을 설명하기 위하여 도시한 단면도들이다. 2 to 4 are cross-sectional views illustrating a method of manufacturing a semiconductor device having a copper pad according to the present invention.

도 2는 반도체 기판(1) 상에 다마슨 공정을 이용하여 구리층(5)을 형성하는 단계를 나타낸다.FIG. 2 shows a step of forming a copper layer 5 on a semiconductor substrate 1 using a damason process.

구체적으로, 반도체 기판(1), 예컨대 실리콘 기판 상에 콘택홀을 갖는 층간 절연막(3)을 형성한다. 이어서, 상기 층간 절연막(3)이 형성된 반도체 기판(1)의 전면에 구리층을 형성한 후 평탄화하여 콘택홀에 매몰되는 구리층(5)을 형성한다.Specifically, an interlayer insulating film 3 having a contact hole is formed on the semiconductor substrate 1, for example, a silicon substrate. Subsequently, a copper layer is formed on the entire surface of the semiconductor substrate 1 on which the interlayer insulating film 3 is formed and then planarized to form a copper layer 5 embedded in a contact hole.

도 3은 구리층(5) 상에 반응층(7)을 형성하는 단계를 나탄낸다.3 illustrates the step of forming the reaction layer 7 on the copper layer 5.

구체적으로, 상기 구리층(5)이 형성된 반도체 기판(1)의 전면에 상기 구리층(5)과 반응하여 합금을 형성할 수 있는 물질층(7)을 형성한다. 본 실시예에서는 상기 물질층(7)은 알루미늄 또는 실리콘을 이용하여 100∼200Å의 두께로 형성한다.Specifically, a material layer 7 capable of reacting with the copper layer 5 to form an alloy is formed on the entire surface of the semiconductor substrate 1 on which the copper layer 5 is formed. In this embodiment, the material layer 7 is formed to a thickness of 100 ~ 200Å by using aluminum or silicon.

도 4는 어닐닝을 실시하는 단계를 나타낸다.4 shows a step of annealing.

구체적으로, 상기 구리층(5) 상에 물질층(7)이 형성된 반도체 기판(1)을 350∼450℃의 온도에서 수십분동안 어닐링을 실시한다. 이렇게 되면, 상기 구리층(5)과 물질층(7)의 반응으로 인하여 보호층(9)이 형성된다. 본 실시예에서는 상기 보호층(9)으로써 Al2Cu 또는 구리 실리사이드가 형성된다.Specifically, the semiconductor substrate 1 having the material layer 7 formed on the copper layer 5 is annealed at a temperature of 350 to 450 ° C. for several tens of minutes. In this case, the protective layer 9 is formed by the reaction of the copper layer 5 and the material layer 7. In the present embodiment, Al 2 Cu or copper silicide is formed as the protective layer 9.

다음에, 상기 보호층(9)이 형성된 반도체 기판(1)을 습식세정하여 상기 보호층(9) 및 층간 절연막(3) 상에 형성된 물질층(7)을 제거하한다. 이렇게 되면, 도 1에 도시한 바와 같이 반도체 기판(1)에 구리층(5) 및 보호층(9)이 순차적으로 형성된 구리 패드가 형성된다. 따라서, 본 발명의 구리 패드는 상기 구리층(5) 상에 남아있는 보호층(9)으로 인하여 구리층(9)의 산화를 방지할 수 있다. Next, the semiconductor substrate 1 on which the protective layer 9 is formed is wet-washed to remove the material layer 7 formed on the protective layer 9 and the interlayer insulating film 3. In this case, as shown in FIG. 1, the copper pad in which the copper layer 5 and the protective layer 9 were formed sequentially is formed in the semiconductor substrate 1. Therefore, the copper pad of the present invention can prevent oxidation of the copper layer 9 due to the protective layer 9 remaining on the copper layer 5.

이상, 실시예를 통하여 본 발명을 구체적으로 설명하였지만, 본 발명은 이에 한정되는 것이 아니고, 본 발명의 기술적 사상 내에서 당 분야에서 통상의 지식으로 그 변형이나 개량이 가능하다. As mentioned above, although this invention was demonstrated concretely through the Example, this invention is not limited to this, A deformation | transformation and improvement are possible with the conventional knowledge in the art within the technical idea of this invention.

상술한 바와 같이 본 발명에 의해 제조된 반도체 소자의 구리 패드는 표면에 보호층이 형성되어 산화를 방지할 수 있다. 이에 따라, 전기적 특성 분석을 위하여 반드시 오픈되어 있는 구리 패드의 산화를 방지하여 여러 가지 전기적 특성 뿐만 아니라 EM측정시 많은 오차가 발생 가능성을 줄일 수 있다.As described above, the copper pad of the semiconductor device manufactured according to the present invention may have a protective layer formed on a surface thereof to prevent oxidation. Accordingly, by preventing the oxidation of the copper pad that is necessarily open for electrical characteristics analysis, it is possible to reduce the possibility of a lot of errors in the EM measurement as well as various electrical characteristics.

Claims (6)

삭제delete 삭제delete 반도체 기판 상에 콘택홀을 갖는 층간 절연막을 형성하는 단계;Forming an interlayer insulating film having a contact hole on the semiconductor substrate; 상기 콘택홀에 매몰되는 구리층을 형성하는 단계;Forming a copper layer buried in the contact hole; 상기 구리층이 형성된 반도체 기판의 전면에 상기 구리층과 반응하여 합금을 형성할 수 있게 알루미늄 또는 실리콘으로 이루어진 물질층을 형성하는 단계;Forming a material layer made of aluminum or silicon on the front surface of the semiconductor substrate on which the copper layer is formed to react with the copper layer to form an alloy; 상기 구리층 상에 물질층이 형성된 반도체 기판을 어닐링을 실시하여 Al2Cu 또는 구리 실리사이드로 이루어진 구리 합금으로 보호층을 형성하는 단계; 및 Annealing the semiconductor substrate on which the material layer is formed on the copper layer to form a protective layer from a copper alloy made of Al 2 Cu or copper silicide; And 상기 층간 절연막 상에 형성된 물질층을 제거하여 상기 구리층 및 보호층으로 이루어진 구리 패드를 형성하는 단계를 포함하여 이루어지는 것을 특징으로 하는 반도체 소자의 제조방법.And removing a material layer formed on the interlayer insulating film to form a copper pad made of the copper layer and the protective layer. 삭제delete 제3항에 있어서, 상기 물질층은 100∼200Å의 두께로 형성하는 것을 특징으로 하는 반도체 소자의 제조방법.The method of claim 3, wherein the material layer is formed to a thickness of 100 to 200 GHz. 삭제delete
KR1019990010803A 1999-03-29 1999-03-29 Manufacturing method of semiconductor device having copper pad KR100546287B1 (en)

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