KR100546155B1 - Microprocessor System and Its Driving Method - Google Patents

Abstract

The present invention relates to a microprocessor system and a method of driving the same, and to detect a bad opcode in data of a memory and perform a re-fetch or a halt-fetch to prevent a fatal error. It starts.

To this end, the present invention provides a memory for storing data, an opcode detection unit for patching the opcode of the data by the opcode patch signal to detect whether the opcode is defective and to output a bad opcode detection signal; A control unit that is controlled by the opcode patch signal and selectively outputs the data, a center for generating an address corresponding to the data and the opcode patch signal, and repeatedly performing a patch according to the bad opcode detection signal. It is characterized by including a processing unit.

Description

Microprocessor system and operating method thereof

1 is a block diagram of a microprocessor system according to the prior art.

2 is an operation timing diagram of the microprocessor system of FIG.

3 is a block diagram of a microprocessor system according to an embodiment of the present invention.

4 is an exemplary format of the opcode of FIG.

5 is a flowchart illustrating a method of driving the microprocessor system of FIG. 3.

FIG. 6 is a flowchart illustrating a method of performing a halt-fetch when a bad opcode occurs in the microprocessor system of FIG. 5.

7A and 7B are operational timing diagrams of the microprocessor system of FIG.

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a microprocessor system and a method of driving the same, and is a technology for preventing a fatal error by detecting a bad opcode among data in a memory and performing a re-fetch or a halt-fetch. .

1 is a block diagram of a microprocessor system according to the related art.

A conventional microprocessor system includes a memory 1, a central processing unit (CPU) 2, and a peripheral circuit unit 3.

The memory 1 receives the system clock signal SCLK and the address ADD and outputs data corresponding to the address ADD.

The central processing unit 2 generates an address ADD, receives data from the memory 1, synchronizes with the system clock signal SCLK, and outputs a control signal CTRL for controlling the peripheral circuit unit 3.

The peripheral circuit unit 3 is a peripheral device such as a monitor, a keyboard, and a speaker, and is driven by receiving the address ADD and the control signal CTRL.

2 is an operation timing diagram of the microprocessor system of FIG. 1.

When the system clock signal SCLK is regularly enabled, the central processing unit 2 performs an execution operation when data DATA composed of an opcode and an operand is input.

By the way, in the conventional microprocessor system having such a configuration, noise is applied from the outside during the data input / output operation, and the noise causes a defect in the opcode.

Therefore, an error occurs in the operation of the microprocessor system due to a bad opcode, and problems such as congestion occur.

The present invention was created to solve the above problems, and more specifically, a fatal error is generated by detecting a bad opcode among data in a memory and performing a re-fetch or a halt-fetch. The purpose is to stabilize the system by preventing the damage.

The microprocessor system of the present invention for achieving the above object is, the memory for storing the data, and the opcode of the data by patching the opcode patch signal to detect whether the opcode is defective by detecting a bad opcode detection signal An opcode detection unit for outputting, a selector for selectively outputting the data controlled by the opcode patch signal, an address corresponding to the data and the opcode patch signal, and generating the bad opcode detection signal It characterized in that it comprises a central processing unit for repeating the patch according to.

In addition, a method of driving a microprocessor system of the present invention includes a first step of outputting data in accordance with a system clock signal, a second step of controlling an opcode patch signal to patch an opcode from the data, and the patch. A third step of detecting whether a defective opcode is defective, a fourth step of repeatedly performing a patch if the patched opcode is defective, and a corresponding opcode if the patched opcode is not bad And a fifth step of operating using the data.

The above and other objects and features and advantages of the present invention will become more apparent from the following detailed description taken in conjunction with the accompanying drawings.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

3 is a schematic diagram of a microprocessor system according to an exemplary embodiment of the present invention.

The microprocessor system includes a memory 10, an opcode detector 11, a multiplexer 12, a central processing unit (CPU) 13, and a peripheral circuit unit 14.

The memory 10 receives the address ADD output from the central processing unit 13 and outputs data DATA corresponding to the address ADD according to the system clock signal SCLK.

The opcode detecting unit 11 receives the data DATA and the address ADD according to the opcode patch signal FETCH and detects a bad state of the opcode. As a result, when the opcode is detected as a bad opcode, a high level opcode detection result signal DET is output.

The multiplexer 12 receives the data DATA and the opcode data OP_DATA and is controlled by the patch signal FETCH output from the central processing unit 13 to selectively output the data DATA and the opcode data OP_DATA.

The central processing unit 13 generates an opcode patch signal FETCH for patching the opcode and a control signal CTRL for controlling the peripheral circuit unit 14. When the central processing unit 13 receives the bad opcode detection signal DET from the opcode detecting unit 11, the central processing unit 13 outputs from the multiplexer 12 after refetching or halt-fetching. Normal operation is continued using the data SDATA.

Here, as shown in FIG. 5, if a bad opcode is detected, the refetch operation ignores the cycle of the corresponding address ADD and repeats the patch operation for the current address in the next cycle. Continue operation.

In addition, as shown in Fig. 6, the holt operation temporarily stops the system clock signal SCLK and the opcode patch signal FETCH when a bad opcode is detected, and then resumes normal operation when the bad opcode returns to normal.

On the other hand, when the central processing unit 13 receives the low-level opcode patch signal FETCH from the opcode detecting unit 11, the bad opcode is not detected, and thus the patch continues.

The peripheral circuit unit 14 performs an operation corresponding to the address ADD using the control signal CTRL and the address ADD output from the central processing unit 13. At this time, the peripheral circuit unit 14 recognizes the information on the bad opcode by receiving a bad opcode detection signal DET.

4 is an exemplary view illustrating the format of the opcode of FIG. 3.

The opcode of FIG. 4 has an instruction number of 64 or less and is an example of 8-bit data. Here, the upper six bits are bits B for performing actual decoding and the lower two bits are bits A indicating a bad state.

TABLE 1

CODE 7 CODE 6 Address 0 0 0000h to 0fffh 0 One 1000h to 1fffh One 0 2000h to 2fffh One One 3000h to 3fffh

Table 1 shows data information and address information of bit A indicating the bad state of FIG. That is, as there is a memory area in which the bit B to be actually decoded is to be stored, a memory area in which a bee A indicating a bad state is to be stored is set. Therefore, if the bit A indicating a bad state is "00", it is allocated to the addresses "000h to 0fffh" of the memory.

The opcode detecting unit 11 stores information on the bit A indicating the bad state of the opcodes in Table 1, and compares the information of the lower two bits of the opcodes patched by the opcode patch signal FETCH. If it does not match, it is determined as a bad opcode.

In addition, the opcode detecting unit 11 receives the address ADD from the central processing unit 13 and compares it with the address information of the bit A indicating the bad state of the opcodes in Table 1, and determines that the opcode is a bad opcode. .

5 and 7B, a method of normal operation by detecting a bad opcode of the microprocessor system of the present invention will be described.

5 is a flowchart illustrating a method of driving the microprocessor system of FIG. 3.

First, data DATA corresponding to the address ADD output from the central processing unit 13 is output (S100).

Thereafter, the central processing unit 13 generates the opcode patch signal FETCH, and the opcode detecting unit 11 is controlled by the opcode patch signal FETCH to patch the opcode from the data DATA (S101).

The opcode detection unit 11 detects whether the patched opcode is defective (S102). At this time, the opcode detection unit 11 outputs a high level bad opcode detection signal DET when the opcode is bad, and outputs a low level bad opcode detection signal DET when the opcode is normal.

As a result of the detection of the step (S102), if the patched opcode is bad, it performs a re-fetch (halt-fetch) or (halt-fetch) (S103).

As a result of the detection of the step (S102), if the patched opcode is not bad, the data corresponding to the opcode is output (S104).

At this time, the patch ignores the current patch cycle and re-patches the current address in the next cycle. As shown in Fig. 7A, the system clock signal SCLK is regularly enabled, and the opcode patch signal FETCH outputs a constant pulse.

Thereafter, when a bad opcode is detected from the data DATA and the bad opcode detection signal DET is enabled, the opcode is patched by enabling a new opcode patch signal FETCH within the current cycle. Therefore, in normal operation, the execution should be performed in the C part, but it can be seen that the execution is performed in the D part due to a delay due to a bad opcode.

FIG. 6 is a flowchart illustrating a method of performing a halt-fetch when a bad opcode occurs in the microprocessor system of FIG. 5.

In the holt patch after the bad opcode is detected, the central processing unit 13 temporarily stops the system clock signal SCLK and the opcode patch signal FETCH to maintain the patch state (S200).

The opcode detection unit 11 continuously detects the opcode during the cycle in which the patch state is maintained and detects whether the opcode detection returns to the normal opcode (S201).

If the normal opcode is detected by the opcode detecting unit 11, the central processing unit 13 outputs the system clock signal SCLK and the opcode patch signal FETCH normally (S202).

The timing of operation during such a halt-fetch is shown in FIG. 7B.

As shown in Fig. 7B, the system clock signal SCLK is regularly enabled, and the opcode patch signal FETCH outputs a constant pulse.

Thereafter, when a bad opcode is detected from the data DATA and the bad opcode detection signal DET is enabled, the patch state is maintained by maintaining the enable state of the system clock signal SCLK and the opcode patch signal FETCH.

In this way, the patch status is continued and patching of opcodes is continued. When a normal opcode is detected, the system clock signal SLCK and opcode patch signal FETCH are disabled to continue normal operation.

As described above, the present invention has an effect of improving the stability of the system by detecting or performing a patch or hold patch when a bad opcode is generated by external noise.

In addition, a preferred embodiment of the present invention is for the purpose of illustration, those skilled in the art will be able to various modifications, changes, replacements and additions through the spirit and scope of the appended claims, such modifications and changes are the following claims It should be seen as belonging to a range.

Claims (12)

A memory for storing data; An opcode detection unit for patching the opcode of the data by an opcode patch signal to detect whether the opcode is defective and to output a bad opcode detection signal; A selection unit controlled by the opcode patch signal to selectively output the data; And A central processing unit generating an address corresponding to the data and the opcode patch signal and repeatedly performing a patch according to the bad opcode detection signal; Microprocessor system, characterized in that configured to include. The method of claim 1, And a peripheral circuit unit controlled by the central processor and configured to recognize the bad opcode detection signal and perform an operation corresponding to the address. The method of claim 1, wherein the central processing unit, And if the bad opcode detection signal is enabled, ignore the current patch cycle and perform the patch for the current address again in the next cycle. The method of claim 1, wherein the central processing unit, When the bad opcode detection signal is enabled And suspending the opcode patch signal to maintain a patch state to continue patching the opcode so that normal operation continues when the opcode returns to normal. The microprocessor system of claim 1, wherein the selector is a multiplexer. The method of claim 1, wherein the opcode detection unit, The normal bit information of the opcode and the address information where the bit information is to be stored are stored in advance, and it is determined whether or not the defect is compared with the bit information and the address information storing the bit information and the address information of the patched opcode. Characterized in a microprocessor system. The method of claim 1, wherein the opcode is, And a plurality of bits representing a plurality of data bits and a bad state of the opcode. A first step of outputting data in accordance with a system clock signal; A second step of controlling an opcode patch signal to patch the opcode from the data; Detecting whether the patched opcode is defective; A fourth step of repeatedly performing a patch when the patched opcode is defective; And A fifth step of operating using data corresponding to the opcode when the patched opcode is not bad; Data output method of a microprocessor system comprising a. The method of claim 8, wherein the third step, The normal bit information of the opcode and the address information where the bit information is to be stored are stored in advance, and it is determined whether or not the defect is compared with the bit information and the address information storing the bit information and the address information of the patched opcode. A data output method of a microprocessor system, The method of claim 8, wherein the fourth step, A method of outputting data of a microprocessor system, wherein the microprocessor system ignores the current patch cycle and re-patches the current address in the next cycle. The method of claim 8, wherein the fourth step, Pausing the system clock signal and the opcode patch signal to maintain a patch state; Continually patching the opcode during a cycle in which the patch status is maintained to detect whether it is returned to a normal opcode; And Normally outputting the system clock signal and the opcode patch signal when the opcode returns to normal; Data output method of a microprocessor system comprising a. The method of claim 8, wherein the opcode And a plurality of bits indicating a plurality of data bits and a bad state of the opcode.

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