KR100545582B1 - Output drive circuit using voltage level controlled boot-strap circuit - Google Patents

Abstract

The present invention maintains constant voltage driving regardless of external environment change by using a bootstrap circuit with a controlled voltage level, thereby reducing parasitic components to increase input / output speed and reducing power consumption and circuit area. The present invention relates to an external driving circuit using a voltage level control bootstrap circuit.

According to the present invention, in the open-drain transistor type external driving circuit, predetermined input data and a reference voltage are input, feedback voltages of the output voltage of the open-drain transistor are input, and their voltage levels are detected to output a predetermined control voltage. Level detecting means; Buffer means for buffering and outputting a control voltage output from said level detecting means; Bootstrap circuit means for receiving the input data input to the level detection means and the control voltage output from the buffer means for applying a drive signal of a voltage level controlled to the gate of the open drain transistor. It is done.

Description

Output drive circuit using voltage level controlled boot-strap circuit

Figure 1 is an embodiment of an external drive circuit according to the prior art.

Figure 2 is a block diagram of an external drive circuit using a voltage level control bootstrap circuit according to the present invention.

3 is a block diagram of a voltage level control bootstrap circuit according to the present invention;

4 is a block diagram of a voltage level detection circuit according to the present invention;

Figure 5 is a view comparing the output voltage swing value and the output voltage swing value according to the prior art according to the present invention.

<Description of the symbols for the main parts of the drawings>

20.Voltage level detector

24 ... charge pump

Buffer comparator

50 ... Bootstrap Circuit

Q ... open drain transistor

MP1 ... first p-channel transistor

MN1 ... first n-channel transistor

The present invention maintains constant voltage driving regardless of external environment change by using a bootstrap circuit with a controlled voltage level, thereby reducing parasitic components to increase input / output speed and reducing power consumption and circuit area. The present invention relates to an external driving circuit using a voltage level control bootstrap circuit.

As is well known to those skilled in the art, in general, in order to send and receive signals between a chip and a chip, an external driving circuit for transmitting a signal and a receiving circuit for properly receiving a signal are required. Among them, the external driving circuit is a circuit for converting and transmitting data inside the chip into a state easily accessible from the outside, and the magnitude of the external voltage swing becomes an important factor. In other words, if the driving voltage swing is too small, the noise margin is too small when receiving at the receiving circuit, and the error rate is increased. This increases the integrity of the signal. Therefore, an appropriate amount of external voltage swing may be necessary to lower the bit error rate (BER) of a high speed transmission / reception system.

However, there is a problem that the voltage swing width is greatly changed in accordance with the change of the external environment. That is, no matter how well the width is adjusted in the design, if the external environment, the process, the supply voltage, and the temperature (PVT) are different, the amount of current in the driving circuit transistor is different, and eventually the magnitude of the voltage going out is changed to compensate for this. Circuitry is necessary.

An example of an open drain type external driving circuit for compensating for changes in the external environment according to the prior art is shown in FIG. 1. Referring to FIG. 1, when a low voltage is applied to the input data from the digital control circuit unit D, the transistors are all turned off and the voltage applied to the outside becomes Vtt. On the contrary, the input is high. When the transistors are turned on, the external voltage changes to (Vtt-R _T * I). At this time, since the driving current I of the transistors is changed according to the external environment, in order to compensate for this and to have a constant voltage swing, the circuit according to the related art drives the driving current I by adjusting the transistor's W / L (width / length) through a binary control method. The size of is adjusted to have the desired value. However, in order to adjust the current size using the binary method, a complicated digital control circuit is required, which causes a large power and area consumption.

Therefore, the technical problem to be achieved by the present invention is to maintain a constant voltage driving regardless of the external environment changes by using a bootstrap circuit with a controlled voltage level can reduce the parasitic components compared to the conventional circuit to increase the input and output speed and power It is an object of the present invention to provide an external driving circuit using a voltage level control bootstrap circuit that can reduce consumption and area of a circuit.

In order to achieve the above object, the external driving circuit using the voltage level control bootstrap circuit according to the present invention, in the open drain transistor type external driving circuit, receives predetermined input data and a reference voltage, and outputs the output voltage of the open drain transistor. A level detecting means for receiving the feedback input, detecting the voltage levels thereof, and outputting a predetermined control voltage; Buffer means for buffering and outputting a control voltage output from said level detecting means; Bootstrap circuit means for receiving the input data input to the level detection means and the control voltage output from the buffer means for applying a drive signal of a voltage level controlled to the gate of the open drain transistor. It is done.

In a preferred embodiment of the present invention, the bootstrap circuit means,

An inverter which receives the data signal and inverts it and outputs the data signal; A first p-channel transistor and a first n-channel transistor, a second p-channel transistor and a second n-channel transistor receiving the output signal of the inverter, respectively; A third n-channel transistor whose drain terminal is commonly connected to each of the drain terminals of the first p-channel transistor and the first n-channel transistor, and a predetermined control voltage is applied to the gate terminal; A third p-channel transistor having a drain terminal connected to the source terminal of the second p-channel transistor, and having a drain terminal of the second p-channel transistor and a gate terminal commonly connected to the source terminal of the second n-channel transistor; And a capacitor interposed between the third n-channel transistor, the second p-channel transistor, and the third p-channel transistor.

In a preferred embodiment of the invention, the level detecting means,

A comparator configured to receive the reference voltage and the output voltage of the open-drain transistor, invert a predetermined clock signal, and output positive and negative output signals; Two AND gates receiving the comparator's positive and negative output signals, respectively, and receiving the data signal and outputting an up signal and a down signal, respectively; Charge pump means for receiving an up signal and a down signal from the AND gates to charge pump a predetermined capacitor; And a capacitor to be charge pumped by the charge pump means.

Hereinafter, a preferred embodiment of an external driving circuit using the voltage level control bootstrap circuit according to the present invention will be described in detail with reference to the accompanying drawings. In the following description of the present invention, when it is determined that detailed descriptions of related well-known technologies or configurations may unnecessarily obscure the subject matter of the present invention, the detailed description will be omitted. Terms to be described later are terms defined in consideration of functions in the present invention, and may be changed according to intentions or customs of users or operators. Therefore, the definition should be made based on the contents throughout the specification.

2 is a block diagram of an external driving circuit using a voltage level control bootstrap circuit according to the present invention, FIG. 3 is a block diagram of a voltage level control bootstrap circuit according to the present invention, and FIG. 4 is a voltage diagram according to the present invention. A diagram of the level detection circuit is shown. 5 is a view comparing the output voltage swing value according to the present invention with the output voltage swing value according to the prior art.

2, the external driving circuit using the voltage level control bootstrap circuit according to the present invention receives input data and a reference voltage Vref, and receives a feedback input of the output voltage Vo of the open drain transistor Q. A level detector 20 for detecting these voltage levels and outputting a control voltage Vctrl, a comparator 30 and a capacitor C1 for buffering and outputting the control voltage Vctrl output from the level detector 20. An open-drain transistor (Vdrv = Va) for receiving a driving voltage (Vdrv = Va) whose voltage level is controlled by receiving the buffer unit configured to include the buffer unit, the input data input to the level detector unit 20, and the control voltage Vctrl output from the buffer unit. A bootstrap circuit section 50 is applied to the gate of Q).

In the configuration of the present invention, the bootstrap circuit unit 50 includes: an inverter (IV) for receiving input data and inverting it; A first p-channel transistor MP1 and a first n-channel transistor MN1, a second p-channel transistor MP2 and a second n-channel transistor MN2 respectively receiving the output signal of the inverter IV; A third n-channel transistor MN3 having a drain terminal thereof commonly connected to the drain terminals of the first p-channel transistor MP1 and the first n-channel transistor MN1 and having a predetermined control voltage applied to the gate terminal thereof; A drain terminal connected to the source terminal of the second p-channel transistor MP2, and having a drain terminal of the second p-channel transistor MP2 and a gate terminal commonly connected to the source terminal of the second n-channel transistor MN2. 3 p-channel transistor MP3; The capacitor Cv is interposed between the third n-channel transistor MN3, the second p-channel transistor MP2, and the third p-channel transistor MP3.

In addition, in the configuration of the present invention, the level detector 20 receives the output voltage of the reference voltage Vref and the open-drain transistor Q, and inverts the predetermined clock signal CLKB to receive positive (+), A comparator 22 for outputting a negative output signal out + and out-; The two comparators 22 receive the output and the negative output signal out + and out-, respectively, and receive the input data and output the up signal and the down signal UP, respectively. AND gate AND1 (AND2); A charge pump 24 that receives the up signal UP and the down signal DOWN from the AND gates AND1 and AND2, respectively, and charges a predetermined capacitor to a predetermined capacitor; And a capacitor CP charged by the charge pump 24.

The operation of the external driving circuit using the voltage level control bootstrap circuit according to the present invention configured as described above will be described with reference to FIGS. 2 to 5.

First, the invention background of the external driving circuit using the voltage level control bootstrap circuit according to the present invention is as follows. In the prior art, if a binary control method is selected to implement an external driving circuit having a constant voltage swing width regardless of environmental changes, a digital control circuit for controlling these binary signals is required, which causes unnecessary power and area consumption. This is as described above. By the way, in order to change the value of the drive current I of a transistor, you may change the W / L value of a transistor as mentioned above, but it changes in a current value similarly, even if it changes the gate voltage when a transistor is turned on. Therefore, the present invention is to have a constant voltage swing by adjusting the gate voltage value of the transistor according to the change of external environmental conditions.

On the other hand, in order to enable high-speed transmission and reception, focusing on the smaller parasitic capacitance value of the pin, it is advantageous for the transmission and reception. In the present invention, the external driving transistor Q using the voltage level control bootstrap circuit 50 is used. Increasing the driving voltage of) increases the external parasitics by allowing a large amount of current to be driven even with a small transistor size.

Referring to FIG. 2, this is an open-drain type external driving circuit using a voltage level control bootstrap circuit according to the present invention, in which the input data varying from 0 volts to Vdd volts passes through the level detector 20. The driving voltage (Vdrv = Va) is changed to a predetermined voltage Va determined by the detector 20. At this time, when the input is high, the output Vo of the open-drain transistor Q is fed back to the level detector 20 to determine whether to increase or decrease the driving voltage Va in comparison with the reference voltage Vref. . If Va is high, the driving voltage is low, and if Va is low, the driving voltage is high. Therefore, even if the external environmental conditions change, the output voltage of this drive circuit can be kept constant at all times.

3 shows a bootstrap circuit 50 whose voltage level is controlled. When a low signal is input to the input in FIG. 3, the output voltage Vdrv becomes the sink voltage Vss by the second n-channel transistor MN2, so that the node ND2 is freed with the drain voltage Vdd. -Pre-charged. In this case, when high is applied to the input, the value of the node ND1 is determined according to the resistance ratio of the first p-channel transistor MP1 and the third n-channel transistor MN3. At this time, since the DC path disappeared from the node 2 (ND2), the drain voltage Vdd, which was previously maintained, has the value added by the voltage supplied from the node ND1, and thus a random voltage value between the drain voltages Vdd and 2Vdd. Becomes At this time, the output voltage Vdrv is driven through this value through the second p-channel transistor MP2. In this case, the value drives the output voltage Vdrv through the second p-channel transistor MP2. At this time, this voltage value is determined by Vctrl. When the value of Vctrl is increased, the value of node ND1 is lowered, so the value of Vdrv is also lowered, and conversely, when Vctrl is lowered, the value of Vdrv is also increased.

FIG. 4 shows a detailed configuration of the level detector 20 (FIG. 2). As described above, the level detector 20 uses the output voltage Vo when the driving transistor Q is on as the reference voltage Vref. Compared with), the driving voltage Va of the transistor Q is changed. The output voltage Vo and the reference voltage Vref are compared in the comparator 22 to give an UP signal and a DOWN signal, respectively. At this time, the up and down signals UP and DOWN become inputs of the charge pump circuit 24, and the Vctrl value stored in the capacitor CP becomes high, and when the down signal comes in, the Vctrl value decreases. At this time, after the output voltage Vo is sufficiently stabilized, the clock CLKB that enters the comparator 22 is used by inverting the external clock synchronized with the data in order to compare with the reference voltage Vref.

FIG. 5 is a diagram showing a simulation result of an output voltage swing width when the circuit of FIG. 2 is changed in conditions such as a process, a supply voltage temperature, and the like. Compared to the output voltage swing width when only one transistor is used to drive the voltage in the prior art, the driving circuit of FIG. 2 according to the present invention produces a constant output voltage insensitive to changes in external environmental conditions. Able to know.

As described above, the external driving circuit using the voltage level control bootstrap circuit according to the present invention uses a bootstrap circuit whose voltage level is controlled to maintain a constant voltage driving regardless of an external environment change. By reducing parasitic components, I / O speed can be increased, and power consumption and circuit area can be reduced.

On the other hand, the present invention can provide a constant output voltage while reducing the effects of environmental changes in the CMOS full swing drive circuit as well as the open-drain external drive circuit, providing an advantage that can be useful in high-speed graphics DRAM or interface circuits can do.

Although a preferred embodiment of the present invention has been described in detail above, those skilled in the art to which the present invention pertains, various embodiments of the present invention without departing from the spirit and scope of the invention defined in the appended claims It will be appreciated that modifications or variations may be made. Therefore, changes in the future embodiments of the present invention will not be able to escape the technology of the present invention.

Claims (3)

In the open-drain transistor type external drive circuit, Level detection means for receiving predetermined input data and a reference voltage, receiving a feedback input of an output voltage of the open-drain transistor, detecting their voltage levels, and outputting a predetermined control voltage; Buffer means for buffering and outputting the control voltage output from the level detecting means; Bootstrap circuit means for receiving the input data input to the level detecting means and the control voltage output from the buffer means for applying a drive signal of a voltage level controlled to the gate of the open drain transistor, The level detecting means may include: a comparator receiving the reference voltage and the output voltage of the open-drain transistor, inverting a predetermined clock signal, and outputting a positive and negative output signals; Two AND gates that receive the positive and negative output signals of the comparator and receive the data signal and output an up signal and a down signal, respectively; Charge pump means for receiving an up signal and a down signal from the AND gates to charge pump a predetermined capacitor; An external drive circuit using a voltage level control bootstrap circuit, characterized in that it comprises a capacitor charged by the charge pump means. The method of claim 1, wherein the bootstrap circuit means, An inverter that receives the data signal and inverts it and outputs the data signal; A first p-channel transistor and a first n-channel transistor, a second p-channel transistor and a second n-channel transistor receiving the output signal of the inverter, respectively; A third n-channel transistor whose drain terminal is commonly connected to each of the drain terminals of the first p-channel transistor and the first n-channel transistor, and a predetermined control voltage is applied to the gate terminal; A third p-channel transistor having a drain terminal connected to the source terminal of the second p-channel transistor and having a gate terminal commonly connected to the drain terminal of the second p-channel transistor and the source terminal of the second n-channel transistor; And an capacitor interposed between the third n-channel transistor, the second p-channel transistor, and a third p-channel transistor. delete

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