JP4912037B2 - Semiconductor integrated circuit device - Google Patents

Description

  The present invention relates to a semiconductor integrated circuit, and more particularly to a semiconductor integrated circuit device equipped with an internal power supply voltage generation circuit.

  Conventionally, for example, a system in which, for example, a microprocessor (MPU), a circuit having a moving image processing function, a memory, and the like are connected to each other on a system board formed of separate chips to form one system is common. However, in recent years, SOC (system on chip) that integrates these functions on the same chip has come to be adopted for reasons such as downsizing of equipment, simplification of wiring, high speed, and low power consumption. I came. The state-of-the-art semiconductor process is used in such an SOC. However, as the miniaturization progresses, the ratio of the threshold voltage of the transistor to the power supply voltage is increasing, and it is necessary to supply the power supply voltage with high accuracy. ing.

  In order to satisfy such a demand, a device in which a highly accurate internal power supply voltage generation circuit is mounted in the same chip has attracted attention. In addition, there is a demand for a semiconductor integrated circuit device that can be driven with low power consumption in order to be mounted on a device using an SOC device, for example, a mobile device such as a mobile phone on the premise of battery driving. In the device, the normal operation (normal mode) has low power consumption, and the power supply inside the chip that is in the low power consumption mode is locally shut down, causing the function to be completely stopped. Deep power down mode may be provided.

Conventionally, various low power consumption modes have been proposed in order to reduce power consumption, and when the power supply voltage supplied to the highly accurate internal power supply voltage generation circuit is shut off, the low power consumption mode is changed to the normal mode. In the case of recovery, there is a problem that it takes time for the internal power supply voltage to return to the target normal voltage level value. Patent Documents 1 to 3 propose a method for quickly recovering the internal power supply voltage to a normal voltage level value when recovering from the low power consumption mode to the normal mode.
JP 2000-242347 A JP 2002-373490 A JP 2003-133935 A

  However, since the high-accuracy internal voltage generation circuit includes a high-impedance circuit with low driving capability, there is a problem that it takes longer to recover the internal state of the circuit than a low-impedance circuit (for example, 200 μs). This point is not described at all in Patent Documents 1 to 3.

  For example, in the case of a mobile device such as a mobile phone, when the information is transmitted from the device to the user, for example, when an incoming mail is notified, the recovery time is not a problem. When the mobile phone receives information from the base station and the process needs to be completed before the next information is received, information transmission between the function IPs is required inside the device, and the recovery time is If it is late, it can be a serious problem.

  The present invention has been made to solve the above problem, and is a semiconductor integrated circuit capable of recovering an internal power supply voltage to a normal voltage level more quickly when recovering from a low power consumption mode to a normal mode. An object is to provide an apparatus.

  A semiconductor integrated circuit device according to the present invention is a semiconductor integrated circuit device having a normal mode and a low power consumption mode, an internal circuit for receiving a voltage and executing a predetermined operation, and a first external power supply An internal power supply voltage generating circuit for receiving the voltage and a second external power supply voltage lower than the first external power supply voltage and supplying the internal power supply voltage to the internal circuit. The internal power supply voltage generation circuit is connected to the first and second external power supply voltages to generate a reference voltage serving as a reference for generating the internal power supply voltage, and based on the reference voltage, And a voltage generation circuit for generating a power supply voltage. The reference voltage generation circuit includes a first current cut-off switch for cutting off an operation current of the reference voltage generation circuit in the low power consumption mode, and a reference voltage when generating the reference voltage in the normal mode in the low power consumption mode. And a state holding unit for holding a voltage level of at least one internal node set based on an operating current in the voltage generation circuit. A second current cut-off switch for cutting off an operating current of the voltage generation circuit in the low power consumption mode;

  Another semiconductor integrated circuit device according to the present invention is a semiconductor integrated circuit device having a normal mode and a low power consumption mode, and a plurality of internal circuits for receiving a voltage and executing a predetermined operation, respectively, Internal power supply voltage connected to the first external power supply voltage and the second external power supply voltage lower than the first external power supply voltage to supply a plurality of different internal power supply voltages to the plurality of internal circuits. And a generation circuit. The internal power supply voltage generation circuit receives a first external power supply voltage and a second external power supply voltage, generates a plurality of reference voltages serving as a reference for generating a plurality of internal power supply voltages, and a plurality of reference And a plurality of voltage generation circuits for generating a plurality of internal power supply voltages based on the generation of the voltage. The reference voltage generation circuit includes a constant current generation circuit that receives the first and second external power supply voltages and generates a common constant current, and a voltage generation unit that generates a plurality of reference voltages based on the constant current, respectively. . A first current cut-off switch for cutting off the operating current of the reference voltage generation circuit in the low power consumption mode, and operates in the reference voltage generation circuit when generating the reference voltage in the normal mode in the low power consumption mode A state holding unit for holding a voltage level of at least one internal node set based on the current. A second current cut-off switch for cutting off an operating current of each voltage generation circuit in the low power consumption mode;

  A semiconductor integrated circuit device according to the present invention includes first and second current cut-off switches for cutting off an operating current between a reference voltage generation circuit and a voltage generation circuit included in an internal power supply voltage generation circuit, and in a low power consumption mode. By cutting off the operating current and reducing power consumption, and providing a state holding unit that holds the voltage level of the internal node in the reference voltage generation circuit, it is possible to speed up when shifting from the low power consumption mode to the normal mode. The reference voltage generation circuit can be restored.

  The semiconductor integrated circuit device according to the present invention includes first and second current cut-off switches that cut off an operating current between a reference voltage generation circuit included in the internal power supply voltage generation circuit and the plurality of voltage generation circuits. In the power consumption mode, the operating current is cut off to reduce the power consumption, and the state holding unit that holds the voltage level of the internal node in the reference voltage generation circuit is provided to shift from the low power consumption mode to the normal mode. In this case, the reference voltage generating circuit can be restored at high speed. Furthermore, since a common reference voltage generation circuit is provided for a plurality of voltage generation circuits, the number of components of the internal power supply voltage generation circuit can be reduced and the layout area can be reduced.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. In the drawings, the same or corresponding parts are denoted by the same reference numerals and description thereof will not be repeated.

(Embodiment 1)
FIG. 1 is a schematic diagram of a semiconductor integrated circuit device 1 according to the first embodiment of the present invention.

  Referring to FIG. 1, semiconductor integrated circuit device 1 according to the first embodiment of the present invention shows a configuration in which a logic circuit such as a processor and a memory circuit are integrated on the same semiconductor chip.

  Here, as an example, a case where three types of memory circuits MEM1 to MEM3, logic circuits LGC1 and LGC2, and an analog circuit ANG are integrated on one semiconductor chip is shown. A plurality of external pads PD are provided. Here, for example, the type of the memory circuit may include a configuration in which DRAM (Dynamic Random Access Memory), SRAM (Static Random Access Memory), nonvolatile RAM (Random Access Memory), and the like are integrated. It is assumed that various control signals, an external power supply voltage, and the like are supplied to the semiconductor integrated circuit device 1 through the external pad PD.

  The logic circuit is equipped with various IP (Intellectual Property) depending on applications such as CPU (Central Processing Unit), image processing, network processing, etc. The analog circuit includes an analog-digital converter, a digital-analog converter, Interface circuits, PLL / DLL (Phase / Delay Locked Loop) circuits, and the like are provided. Although not shown, the circuit units are connected to each other as necessary. For example, the memory circuit holds data supplied from the logic circuit, or the data held in the memory circuit is output to the logic circuit.

  Corresponding to each circuit block, internal power supply voltage for generating an internal power supply voltage by receiving the supply of high-side and low-side external power supply voltage VDD and external power supply voltage GND (hereinafter also referred to as ground voltage) from external pad PD Internal power supply voltage generation units VCRT1 to VCRT6 (hereinafter collectively referred to as internal power supply voltage generation unit VCRT) having generation circuits are provided.

  Internal power supply voltage generating unit VCRT includes an internal power supply line and internal ground lines VL and GL that receive external power supply voltages VDD and GND from external pad PD, and is electrically connected to internal power supply line VL and internal ground line GL. In combination, the external power supply voltage is supplied to generate an internal power supply voltage necessary for the internal circuit.

  Hereinafter, as an example, a part of the configuration of the internal power supply voltage generator VCRT1 that generates an internal power supply voltage for the DRAM integrated as the large-capacity memory circuit MEM1 will be described. As will be described later, internal power supply voltage generation for supplying external power supply voltages from the external pads PDa to PDc directly as internal power supply voltages to the memory circuit MEM1 as necessary, separately from the internal power supply voltage generation unit VCRT1. Section VCRT # is provided. Here, the case where the external power supply voltage VDD, the external power supply voltage GND, and the external power supply voltage VDDL supplied to the external pads PDa to PDc are supplied to the internal power supply voltage generator VCRT # is shown.

  FIG. 2 is a schematic block diagram illustrating internal power supply voltage generation unit VCRT according to the first embodiment of the present invention.

  Referring to FIG. 2, internal power supply voltage generation unit VCRT according to the first embodiment of the present invention includes a reference voltage generation circuit unit 10 and an active voltage generation circuit unit 20.

  The reference voltage generation circuit unit 10 includes a constant current generation circuit 200 that generates a constant current and a plurality of current-voltage conversion circuits that perform current-voltage conversion based on the constant current generated by the common constant current generation circuit 200. It includes a current / voltage conversion circuit group 4 and a buffer circuit group 6 including a plurality of buffer circuits that receive voltage signals that have undergone current / voltage conversion by each current / voltage conversion circuit. A reference voltage for generating an internal power supply voltage from each buffer circuit is input to the active voltage generation circuit unit 20. Here, as an example, reference voltages VREFP, VREFB, and VREFS are generated from the reference voltage generation circuit unit 10 via each buffer circuit and supplied to the active voltage generation circuit unit 20. In this example, a case where three types of reference voltages are mainly generated will be described. However, the present invention is not limited to this, and a configuration in which a plurality of reference voltages are further provided is naturally possible.

  The active voltage generation circuit unit 20 includes a boost voltage detection circuit 12, a boost pump circuit 15, a negative voltage detection circuit 14, a negative voltage pump circuit 16, a voltage drop circuit (VDC) circuit 17, and a push-pull circuit 18. including.

  The boosted voltage detection circuit 12 detects the voltage level of the internal power supply voltage VPP based on the comparison between the internal power supply voltage VPP, which is the boosted voltage, and the reference voltage VREFP, and instructs the boost pump circuit 15 to instruct a pumping operation. The signal OUTP is output. The boost pump circuit 15 receives the control signal OUTP from the boost voltage detection circuit 12 and executes a pumping operation to generate an internal power supply voltage VPP which is a desired boost voltage.

  The negative voltage detection circuit 14 detects the voltage level of the internal power supply voltage VBB based on the comparison between the internal power supply voltage VBB which is a negative voltage and the reference voltage VREFB, and instructs the pumping operation in the negative voltage pump circuit 16. A control signal OUTB is output. The negative voltage pump circuit 16 receives the control signal OUTB from the negative voltage detection circuit 14 and executes a pumping operation to generate an internal power supply voltage VBB that is an intended negative voltage.

  The VDC circuit 17 detects the voltage level of the internal power supply voltage VDDS based on the comparison between the internal power supply voltage VDDS and the reference voltage VREFS, and generates the internal power supply voltage VDDS that is the intended voltage level.

  The push-pull circuit 18 receives the supply of the internal power supply voltage VDDS output from the VDC circuit 17 and generates an internal power supply voltage VBL that is a ½ times internal power supply voltage.

  Although not shown, the internal power supply voltage VPP is used as a boosted voltage supplied to a so-called DRAM word line. Here, as an example, an internal power supply of 2.7 V, which is twice the reference voltage VREFP of 1.35 V, is used. A case where the voltage VPP is set is shown. The internal power supply voltage VBB is used as a substrate voltage of a DRAM semiconductor device. Here, as an example, the internal power supply voltage VBB is a voltage level that drops from a voltage level of a reference voltage VREFB of 1.0 V to a voltage level that is -2 times. The case where the internal power supply voltage VBB is set to 0.0 V is shown. The internal power supply voltage VDDS is used as a high-side drive voltage for a circuit constituting the DRAM, for example, a sense amplifier circuit. Here, as an example, a case where the internal power supply voltage VDDS is set to 1.2 V is shown. Yes. Further, the internal power supply voltage VBL is shown as a case where the bit line precharge voltage of the DRAM is set to 0.6 V, which is 1/2 of the internal power supply voltage VDDS.

  FIG. 3 is a diagram for explaining the relationship between the mode type of the semiconductor integrated circuit device according to the first embodiment of the present invention and the internal power supply voltage.

  Referring to FIG. 3, here, as a mode type, a normal mode including an active mode and a standby mode, and a low power consumption mode including two types of power down modes of an external direct connection power down mode and a deep power down mode, Is shown. The active mode is a mode in which, for example, operations such as data writing and data reading are executed in the DRAM. The standby mode indicates a command input waiting mode in which the above operation is not executed, or an external clock. It is assumed that the mode is such that the signal CLK is stopped or deactivated inside the chip. The external direct-coupled power-down mode is a mode that reduces power consumption by electrically coupling with the external power supply voltage, and the deep power-down mode reduces power consumption by cutting off the electrical connection with the external power supply voltage. This is a mode to reduce. Here, switching of each mode is controlled by inputting a mode instruction signal corresponding to each mode from the outside of the chip so that the corresponding mode is executed, for example, to the memory circuit MEM1, although not shown. .

  Here, in the active mode and standby mode, the internal power supply voltages VPP, VBB, VDDS, and VBL are set to 2.7 V, −1.0 V, 1.2 V, and 0.6 V, respectively, as described above. Has been.

  In the external direct connection power down mode, the external power supply voltage VDDH which is 2.5 V is supplied as the internal power supply voltage VPP which is a boosted voltage. Further, the ground voltage GND which is 0V is supplied as the internal power supply voltage VBB. An external power supply voltage VDDL of 1.2V is supplied as the internal power supply voltage VDDS. Further, a ground voltage GND of 0V is supplied as the internal power supply voltage VBL. In this external direct connection power down mode, in response to an instruction, external power supply voltage VDDH, ground voltage GND, and external power supply voltage VDDL are supplied from internal power supply voltage generation circuit VCRT # to the above-described internal power supply voltages VPP, VBB, VDDS, and VBL. Shall be supplied as Internal power supply voltage generation unit VCRT # is activated in response to an instruction of external direct connection power down mode, and is inactive in other normal mode and deep power down mode.

  In the deep power down mode, the power supply voltage supplied to the internal power supply voltage generation circuit VCRT is cut off as will be described later, so that the signal lines that transmit the internal power supply voltages VPP, VBB, VDDS, and VBL are in a high impedance state. Shall be set to

  The average current in the active mode is about 100 mA, and the average current in the standby mode is about 1 mA due to charge / discharge current and the like. The average current in the external direct connection power down mode is about 10 μA. The average current in the deep power down mode is about 1 μA. As will be described later, the time required for recovery (return) takes about 20 μs in the case of the external direct connection power-down mode, but about 0.1 μs in the case of the deep power-down mode. In the present invention, the low power consumption mode that is the deep power down mode will be mainly described below.

FIG. 4 is a circuit configuration diagram of the reference voltage generation circuit according to the first embodiment of the present invention.
Here, a reference voltage generation circuit that generates the reference voltage VREFS is shown as an example.

  Referring to FIG. 4, the reference voltage generation circuit according to the first embodiment of the present invention is included in constant current generation circuit 200, current-voltage conversion circuit 300 included in current-voltage conversion circuit group 4, and buffer circuit group 6. Buffer circuit 400.

  Constant current generating circuit 200 includes transistors 201, 202, 204, 205, 206, 207 and 208, capacitors 209 and 210, and a resistor 203. As an example, the transistors 201, 202, 204, 207, 208 are P-channel MOS transistors. As an example, the transistors 205 and 206 are N-channel MOS transistors.

  The transistor 201 is arranged between an external power supply voltage VDDH (hereinafter referred to as power supply voltage VDDH) supplied via the internal power supply line VL and an internal node N0 (hereinafter also simply referred to as node), and its gate is connected to the control signal PWRDWN. Receive input. Note that the transistor 201 forms a switch SW1 that cuts off the supply of the power supply voltage VDDH. Control signal PWRDWN is set to “L” level in the normal mode (active mode and standby mode), and set to “H” level in the low power consumption mode (deep power down mode). Shall be. The control signal PWRDWN is input from the outside of the chip together with the input of the mode instruction signal corresponding to each mode.

  Transistor 202 is arranged between nodes N0 and N1, and has its gate electrically coupled to node N1. Transistor 205 is arranged between node N1 and ground voltage GND, and has its gate electrically coupled to node N2. Resistor 203 and transistor 204 are arranged between nodes N0 and N2, and the gate of transistor 204 is electrically coupled to node N1. Transistor 206 is arranged between node N2 and ground voltage GND, and has its gate electrically coupled to node N2.

  Transistor 207 is arranged between nodes N1 and N3, and its gate receives the input of PWRDWN. Capacitor 209 is connected between power supply voltage VDDH and node N3. Transistor 208 is arranged between nodes N2 and N4, and has a gate receiving control signal / PWRDWN. Capacitor 210 is arranged between node N4 and ground voltage GND.

  The constant current generation circuit 200 receives the power supply voltage VDDH (2.5 V) and generates intermediate voltages ICONST (≈VDDH−Vthp) and BIASL (≈Vthn). Here, Vthp is a threshold voltage of the transistors 202 and 204 of the constant current generating circuit 200, and Vthn is a threshold voltage of the transistors 205 and 206. This intermediate voltage BIASL is input to the gate of a transistor 406 of the buffer circuit 400 described later.

  In the normal mode, control signals PWRDWN and / PWRDWN are set to “L” level and “H” level, respectively. Accordingly, the transistor 201 is turned on, and the power supply voltage VDDH is supplied to the constant current generation circuit 200 to generate the constant current i. The constant current i is adjusted according to the resistance value of the resistor 203. The resistor 203 is a high-resistance resistor, and a constant current i having a low high-impedance current flows through the transistors 202 and 205. Similarly, a constant current i flows through the resistor 203 and the transistors 204 and 206.

  Note that in the normal mode, since the transistors 207 and 208 are on, the node N1 and the node N3 are electrically coupled, and charges corresponding to the voltage level of the node N1 are accumulated in the capacitor 209. Further, the node N2 and the node N4 are electrically coupled, and charges according to the voltage level of the node N2 are accumulated in the capacitor 210. Capacitor 209 constitutes state holding unit CU1 that holds the state of node N1 or node N3 in the low power consumption mode. Capacitor 210 constitutes state holding unit CU2 that holds the state of node N2 or node N4 in the low power consumption mode. Note that here, for example, a configuration is described in which the electrical connection between the node N1 and the node N3 connected to the capacitor 209 is controlled using the transistor 207, but the electrical connection can be controlled without being limited to the transistor. Any simple switch can be used. The same applies to other cases.

  Power supply voltage conversion circuit 300 includes a transistor 301, a plurality of serially connected transistors 302, a transistor 303, and a capacitor 304. The transistor 302 functions as an effective long channel transistor (hereinafter also referred to as a long channel transistor 302), but the number of connections for each chip even after the chip is molded by adjusting the number of connections using a fuse element or the like. By adjusting the voltage level, it is possible to adjust the voltage level by adjusting the value of the channel resistance described later. As an example, the transistors 301 and 302 are P-channel MOS transistors, and the transistor 303 is an N-channel MOS transistor.

  Transistor 301 is arranged between nodes N0 and N5, and has its gate electrically coupled to node N3. Long channel transistor 302 is provided between node N5 and ground voltage GND, and has its gate electrically coupled to ground voltage GND. Transistor 303 is arranged between nodes N5 and N6, and has a gate receiving control signal / PWRDWN. Capacitor 304 is provided between node N6 and ground voltage GND.

  In the normal mode, control signals PWRDWN and / PWRDWN are set to “L” level and “H” level, respectively. Accordingly, the transistor 201 is turned on, and the power supply voltage VDDH is supplied to the current-voltage conversion circuit 300. Since the node N1 and the node N3 are electrically coupled, the transistor 301 receiving the node N3 at the gate causes a constant current i to flow through a current mirror with the transistor 202. A constant current i passing through the transistor 301 flows through the long channel transistor 302. Therefore, the constant current i flowing through the long channel transistor 302 is converted into a current voltage by the long channel transistor. Since the transistor 303 is on, the converted voltage is output as the internal reference voltage VREF0. The internal reference voltage VREF0 is set to the channel resistance Rc × i + | VTHP | of the long channel transistor 302. For example, when the constant current i is 0.3 μA as an example, the channel resistance Rc is 250 kΩ, and VTHP is the threshold voltage of the long channel transistor 302, for example, −0.45 V, the internal reference voltage VREF0 is 1 Set to 2V.

  Further, since node N5 and node N6 are electrically coupled, a charge corresponding to the voltage level of node N5 is accumulated in capacitor 304. The capacitor 304 constitutes a state holding unit CU3 that holds the state of the node N5 or the node N6 in the low power consumption mode.

  Buffer circuit 400 includes transistors 401 to 407 and a capacitor 408. As an example, the transistors 401 to 403 and 407 are P-channel MOS transistors. Transistors 404 to 406 are N-channel MOS transistors.

  Transistor 401 is arranged between power supply voltage VDDH and node N7, and has its gate receiving control signal / PWRDWN. Transistor 402 is arranged between nodes N7 and N8, and has its gate electrically coupled to node N8. Transistor 404 is arranged between nodes N8 and N10, and has its gate electrically coupled to node N6. Transistor 403 is arranged between nodes N7 and N9, and has its gate electrically coupled to node N8. Transistor 405 is arranged between nodes N9 and N10, and has its gate electrically coupled to node N9. Transistor 406 is arranged between node N10 and ground voltage GND, and has its gate receiving input of intermediate voltage BIASL of the constant current generating circuit described above. Transistor 407 is arranged between nodes N9 and N11, and has a gate receiving control signal / PWRDWN. Capacitor 408 is arranged between node N11 and ground voltage GND.

  In the normal mode, control signals PWRDWN and / PWRDWN are set to “L” level and “H” level, respectively. Accordingly, the transistor 401 is turned on, the power supply voltage VDDH is supplied to the buffer circuit 400, and the constant current i flows as a passing current according to the input of the intermediate voltage BIASL. Further, transistor 407 is turned on, and nodes N9 and N11 are electrically coupled. Buffer circuit 400 outputs the same voltage level as reference voltage VREFS based on the input of internal reference voltage VREF0 transmitted to node N6, which is an input node. The buffer circuit 400 impedance-converts a high output resistance, that is, a high impedance internal reference voltage VREF0 into a low output resistance, that is, a low impedance reference voltage VREFS, and outputs the converted voltage.

  In response to the input of the reference voltage VREFS, the internal power supply voltage VDDS is generated in the subsequent active voltage generation circuit as described above. Although the reference voltage VREFS has been described here, the other reference voltages VREFP and VREFB are also generated according to the same method except for the voltage level values. Specifically, the voltage level is adjusted by adjusting the resistance value of the channel resistance Rc of the current-voltage conversion circuit 300.

  Note that in the normal mode, since the transistor 407 is on, the node N9 and the node N11 are electrically coupled, and electric charge corresponding to the voltage level of the node N9 is accumulated in the capacitor 408. The capacitor 408 constitutes a state holding unit CU4 that holds the state of the node N9 or the node N11 in the low power consumption mode. In this example, the capacitors 209, 210, 304, and 408 are assumed to be MOS capacitors.

  On the other hand, in the deep power down mode which is the low power consumption mode, in constant current generation circuit 200, control signals PWRDWN and / PWRDWN are set to the “H” level and the “L” level, respectively. In response to this, the transistor 201 is turned off, and the electrical connection between the power supply voltage VDDH and the node N0 is separated. That is, the power supply to the constant current generating circuit 200 is cut off. The transistor 201 constitutes a switch SW1 that cuts off the power supply of the power supply voltage VDDH and cuts off the operating current. Further, the transistor 207 is turned off, and the node N1 and the node N3 are electrically disconnected. Further, the transistor 208 is turned off, and the node N2 and the node N4 are electrically disconnected. In response to this, one electrode of the capacitor 209 is in the power supply voltage VDDH and the other electrode is in an open state, so that the charge accumulated in the normal mode is held. Similarly, since one electrode of capacitor 210 is at ground voltage GND and the other electrode is in an open state, the charge accumulated in the normal mode is held.

  In current-voltage conversion circuit 300, control signals PWRDWN and / PWRDWN are set to the “H” level and the “L” level, respectively. In response to this, the transistor 201 is turned off, so that the electrical connection between the power supply voltage VDDH and the node N0 is disconnected as described above, so that the power supply to the current-voltage conversion circuit 300 is cut off. Further, the transistor 303 is turned off, and the node N5 and the node N6 are electrically disconnected. In response to this, one electrode of the capacitor 304 is at the ground voltage GND and the other electrode is in an open state, so that the charge accumulated in the normal mode is held.

  In buffer circuit 400, control signals PWRDWN and / PWRDWN are set to the “H” level and the “L” level, respectively. In response to this, the transistor 401 is turned off, so that the electrical connection between the power supply voltage VDDH and the node N7 is disconnected, so that the power supply to the buffer circuit 400 is cut off. Further, the transistor 407 is turned off, and the node N9 and the node N11 are electrically disconnected. In response to this, one electrode of the capacitor 408 is held at the ground voltage GND, and the other electrode is in an open state, so that the charge accumulated in the normal mode is held.

  Therefore, when the control signals PWRDWN and / PWRDWN indicating the deep power down mode which is the low power consumption mode are set to the “H” level and the “L” level, the supply of the power supply voltage VDDH is cut off and the constant current is generated. All operating currents flowing through the circuit 200, the current-voltage conversion circuit 300, and the buffer circuit 400 are cut off.

  On the other hand, the capacitor 209 provided corresponding to the nodes N3 and N4 of the constant current generating circuit 200 is opened by turning off the transistors 207 and 208, and the charge accumulated according to the voltage levels of the nodes N3 and N4 is stored. It will be held. Thereby, transistors 207 and 208 are turned on when control signals PWRDWN and / PWRDWN are switched (shifted) from the “L” level and “H” level, that is, from the low power consumption mode to the normal mode. Thereby, node N1 and node N3 to which capacitor 209 is electrically coupled are electrically coupled. In addition, node N2 and node N4 to which capacitor 210 is electrically coupled are electrically coupled. As a result, charges are charged from capacitors 209 and 210, and the internal state, which is the voltage level of nodes N1 and N2 set when constant current i flows through constant current generation circuit 200 in the normal mode, is set (returned) at high speed. ) Will be.

  Therefore, the constant current generating circuit 200 can generate the constant current i at high speed.

  Also in current-voltage conversion circuit 300, capacitor 304 provided corresponding to node N6 is in an open state when transistor 303 is turned off, and the charge accumulated according to the voltage level of node N6 is held. It becomes. Thereby, transistor 303 is turned on when control signal / PWRDWN is at the “H” level, that is, when the low power consumption mode is shifted to the normal mode. Thereby, node N5 and node N6 to which capacitor 304 is electrically coupled are electrically coupled. As a result, electric charge is charged from the capacitor 304, and the voltage level of the internal reference voltage VREF0 generated from the current-voltage conversion circuit 300 in the normal mode is set (returned) at high speed.

  Therefore, the current-voltage conversion circuit 300 can generate the internal reference voltage VREF0 at high speed.

  Also in the buffer circuit 400, the capacitor 408 provided corresponding to the node N11 is in an open state when the transistor 407 is turned off, and the accumulated charge is held in accordance with the voltage level of the node N11. . Thereby, transistor 407 is turned on when control signals PWRDWN, / PWRDWN are shifted from "L" level and "H" level, that is, from the low power consumption mode to the normal mode. Thereby, node N9 and node N11 to which capacitor 408 is electrically coupled are electrically coupled. As a result, charges are charged from the capacitor 408, and the voltage level of the reference voltage VREFS generated from the buffer circuit 400 in the normal mode is set (returned) at high speed.

  Therefore, the buffer circuit 400 can generate the reference voltage VREFS at high speed.

Next, the active voltage generation circuit unit 20 will be described.
FIG. 5 is a circuit configuration diagram of boosted voltage detection circuit 12 according to the first embodiment of the present invention.

  Referring to FIG. 5, boosted voltage detection circuit 12 according to the first embodiment of the present invention includes transistors 500 to 507 and an inverter 508. Transistors 500, 501, 503, and 504 are P-channel MOS transistors as an example. Transistors 502 and 505 to 507 are N-channel MOS transistors as an example.

  Transistor 500 is arranged between internal power supply voltage VPP, which is a boosted voltage generated from the output node of boost pump circuit 15, and node N20, and has its gate electrically coupled to node N20. Transistor 501 is arranged between nodes N20 and N21, and has its gate electrically coupled to node N21. Transistor 502 is arranged between node N21 and ground voltage GND, and has a gate receiving control signal / PWRDWN. Transistor 503 is arranged between power supply voltage VDDH and node N22, and has its gate electrically coupled to node N22. Transistor 505 is arranged between nodes N22 and N24, and has its gate electrically coupled to node N20. Transistor 507 is arranged between node N24 and ground voltage GND, and has a gate receiving control signal / PWRDWN. Transistor 504 is arranged between power supply voltage VDDH and node N23, and has its gate electrically coupled to node N22. Transistor 506 is arranged between nodes N23 and N24, and has a gate receiving reference voltage VREFP. Inverter 508 inverts the voltage signal transmitted to node N23 and outputs the inverted signal to node N25 as control signal OUTP. Here, the transistors 503 to 507 are formed by a differential amplifier circuit 509 that compares input voltages supplied to the gates of the transistors 505 and 506 and amplifies the difference.

  Boosted voltage detection circuit 12 according to the first embodiment of the present invention is activated when transistors 502 and 507 are turned on and a current path is formed when control signal / PWRDWN is at "H" level, and control signal / PWRDWN is activated. In the case of the “L” level, the transistors 502 and 507 are turned off, the current path is cut off and deactivated. When control signal / PWRDWN is at “L” level, control signal OUTP is set at “L” level.

  Here, the voltage VPP / 2 is input to the gate of the transistor 505, and the reference voltage VREFP is input to the gate of the transistor 506. For example, when voltage VPP / 2 ≧ reference voltage VREFP, an “H” level signal is transmitted to node N23. As a result, the control signal OUTP is inverted and set to the “L” level.

  On the other hand, when voltage VPP / 2 <reference voltage VREFP, an “L” level signal is transmitted to node N23. As a result, the control signal OUTP is inverted and set to the “H” level.

  As will be described later, since the intended voltage level of the internal power supply voltage VPP, which is a boosted voltage, is 2.7V, the intended voltage level VPP / 2 is 1.35V. Therefore, by comparing the voltage level of the voltage VPP / 2 with the reference voltage VREFP, it is possible to detect whether the voltage level of the internal power supply voltage VPP is higher or lower than the intended voltage value. As a result, when the voltage level of internal power supply voltage VPP is lower than the intended voltage value, control signal OUTP is set to “H” level, as will be described later, and the voltage level of internal power supply voltage VPP is set to the desired voltage. When the value is higher than the value, the control signal OUTP is set to the “L” level.

FIG. 6 is a circuit configuration diagram of boost pump circuit 15 according to the first embodiment of the present invention.
Referring to FIG. 6, boost pump circuit 15 according to the first embodiment of the present invention includes an AND circuit 510, inverters 511, 516 and 517, and transistors 512, 513, 514, 515, 518 and 519. Note that in the transistors 512 and 518, the sources and drains are electrically coupled to form a MOS capacitor.

  AND circuit 510 transmits an AND logic operation result to node N26 based on externally input clock signal CLK and control signal OUTP. When control signal OUTP is set to “H” level, boost pump circuit 15 is activated to transmit clock signal CLK to node N26. On the other hand, when control signal OUTP is set to “L” level, boost pump circuit 15 is deactivated and node N26 is maintained at “L” level.

  Inverter 511 and transistor 512 are connected in series between nodes N26 and N27, and the gate of transistor 512 is electrically coupled to node N27. The source and drain of transistor 512 are electrically coupled to the output node of inverter 511. Inverters 516 and 517 and transistor 518 are connected in series between nodes N26 and N28, and the gate of transistor 518 is electrically coupled to node N28. Note that the source and drain of transistor 518 are electrically coupled to the output node of inverter 517.

  Transistor 513 is provided between power supply voltage VDDH and node N27, and has its gate electrically coupled to power supply voltage VDDH. Transistor 514 is arranged between power supply voltage VDDH and node N27, and has its gate electrically coupled to node N27. Transistor 515 is electrically coupled to power supply voltage VDDH and the gate of transistor 519, and the gate of transistor 515 is electrically coupled to node N27. Transistor 519 is connected between nodes N28 and N29, and has its gate electrically coupled to node N28.

Next, the operation of the booster pump circuit 15 shown in FIG. 6 will be described.
Inverter 516 inverts clock signal CLK from AND circuit 510 and outputs the inverted signal to inverter 517, and inverter 517 inverts the output signal of inverter 516 and outputs the inverted signal to the source and drain of transistor 518. Inverter 511 inverts clock signal CLK and outputs the inverted signal to the source and drain of transistor 512.

  When inverter 511 outputs an “L” level signal to the source and drain of transistor 512, holes flow from power supply voltage VDDH to node N 27 via transistor 513. Then, the voltage on the node N27 increases. Then, the channel width of the transistor 514 increases in proportion to an increase in the voltage on the node N27, and holes flowing from the power supply voltage VDDH to the node N27 through the transistor 514 increase. Then, the voltage on the node N27 is further increased.

  Thus, the voltage on node N27 increases in proportion to the “L” level period of the signal output from inverter 511.

  As the voltage on node N27 increases, the channel width of transistor 515 also increases, the number of holes flowing from power supply voltage VDDH to node N28 via transistor 515 increases, and the voltage on node N28 also increases.

  During the period in which the inverter 511 outputs the “L” level signal, the inverter 517 outputs the “H” level signal to the source and drain of the transistor 518, so that holes are injected from the source and drain into the channel region of the transistor 518. Then, the hole on the node N28 receives a Coulomb force in a direction away from the gate terminal of the transistor 518.

  Accordingly, the holes on the node N28 are supplied to the node N29 through the transistor 519, and the voltage on the node N29 becomes high. The node N29 outputs an internal power supply voltage VPP of 2.7 V obtained by boosting the reference voltage VREFP.

  In a period in which the inverter 511 outputs an “L” level signal to the source and drain of the transistor 512, and the inverter 517 outputs an “L” level signal to the source and drain of the transistor 518, electrons pass through the transistors 513 and 514. From the power supply voltage VDDH to the node N27.

  Then, the voltage on the node N27 is slightly lowered, and the channel width of the transistor 514 is also narrowed. Then, holes flowing from the power supply voltage VDDH to the node N27 through the transistor 515 decrease, and holes supplied to the node N28 are attracted to the gate of the transistor 518.

Therefore, during this period, boosted voltage VPP on node N29 is slightly lowered.
When inverter 511 outputs an “L” level signal to the source and drain of transistor 512, and inverter 517 outputs an “H” level signal to the source and drain of transistor 518, the node operates in the same manner as described above. The voltage on N29 is boosted.

  In this manner, boost pump circuit 15 repeats the cycle of setting the potential on node N29 to a large positive potential and the cycle of slightly reducing the potential on node N29, and the internal power supply voltage that is a boosted voltage of 2.7V. Outputs VPP. The operation of repeating the cycle of setting the potential on the node N29 to a large positive potential and the cycle of slightly lowering the potential on the node N29 corresponds to the pumping operation.

  Boosted voltage detection circuit 12 and boosted pump circuit 15 according to the first embodiment of the present invention operate in response to input of control signal OUTP and clock signal CLK when control signal / PWRDWN is at “H” level as described above. When control signal / PWRDWN is at "L" level, the current path of boosted voltage detection circuit 12 is cut off and inactivated, and control signal OUTP input to booster pump circuit 15 is also at "L" level. In order to maintain the state, the booster pump circuit 15 does not operate. Therefore, in the low power consumption mode, that is, when control signal / PWRDWN is at “L” level, power consumption can be reduced in boosted voltage detection circuit 12 and booster pump circuit 15. Note that the boost voltage detection circuit 12 and the boost pump circuit 15 are designed to have low impedance unlike the above-described reference voltage generation circuit, so that even when the operating current amount is high and the mode is shifted from the low power consumption mode to the normal mode. It can return at high speed.

FIG. 7 is a circuit configuration diagram of negative voltage detection circuit 14 according to the first embodiment of the present invention. Referring to FIG. 7, negative voltage detection circuit 14 according to the first embodiment of the present invention includes transistors 600 to 605. including.

  Transistor 600 is connected between power supply voltage VDDH and node N30, and has a gate receiving control signal PWRDWN. Transistor 601 is arranged between nodes N30 and N31, and has its gate electrically coupled to node N31. Transistor 602 is provided between nodes N30 and N34, and has its gate electrically coupled to node N31. Transistor 603 is provided between nodes N31 and N32 and has a gate receiving reference voltage VREFB.

  Transistor 604 is provided between node N32 and internal power supply voltage VBB generated from the output node of negative voltage pump circuit 16, and has its gate electrically coupled to ground voltage GND. Transistor 605 is arranged between node N34 and ground voltage GND, and has its gate electrically coupled to node N33 receiving reference voltage VREFB. Transistor 602 is provided between nodes N30 and N34, and has its gate electrically coupled to node N31.

  In the negative voltage detection circuit 14 according to the first embodiment of the present invention, when the control signal PWRDWN is at “L” level, the transistor 600 is turned on, and the power supply voltage VDDH and the node N30 are electrically coupled to each other. Is formed and activated, and when the control signal PWRDWN is at “H” level, the transistor 600 is turned off, and the current path is cut off and deactivated. When control signal PWRDWN is at “L” level, control signal OUTB is set at “L” level.

  Here, the threshold voltage of the transistors 603 to 605 is set to the gate-source voltage VGS = 1.0V. When internal power supply voltage VBB is set to -1.0 V or less, transistors 603 to 605 are turned on to supply current to nodes N31 and N34, and node N34 is set to "L" level. As a result, the control signal OUTB is set to the “L” level.

  On the other hand, when internal power supply voltage VBB is higher than −1.0 V, transistors 603 and 604 are off, so that node N31 is set to “H” level and node N34 is set to “H” level. . The control signal OUTB is inverted and set to the “L” level. Thereby, the control signal OUTB is set to the “H” level.

  Therefore, the negative voltage detection circuit 14 detects whether the voltage level of the internal power supply voltage VBB is higher or lower than the intended voltage value (−1.0 V), and the voltage level of the internal power supply voltage VBB is the expected voltage level. When it is higher than the voltage value, that is, when it is larger than −1.0 V, the control signal OUTB is set to the “H” level, and when the voltage level of the internal power supply voltage VBB is lower than the intended voltage value, that is, −1. In the case of 0 V or less, the control signal OUTB is set to the “L” level.

FIG. 8 is a circuit configuration diagram of negative voltage pump circuit 16 according to the first embodiment of the present invention.
Referring to FIG. 8, negative voltage pump circuit 16 according to the first embodiment of the present invention includes an AND circuit 606, inverters 607, 608, 611, transistors 609, 610, and transistors 612 to 615. The AND circuit 606 outputs the AND logic operation result to the node N35 based on the input of the clock signal CLK and the control signal OUTB input from the outside.

  Inverter 607 receives clock signal CLK, inverts the received clock signal CLK, and outputs the inverted signal to inverter 608. Inverter 608 inverts the output signal of inverter 607 and outputs the inverted signal to the source and drain of transistor 609.

  Inverter 611 receives clock signal CLK, inverts the received clock signal CLK, and outputs the inverted signal to the source and drain of transistor 610.

  Transistor 614 is connected between the gate of transistor 615 and ground voltage GND. Transistors 610 and 614 receive the voltage on node N37 at their gates.

  Transistor 615 is connected between nodes N36 and N38. Transistors 609 and 615 receive the voltage on node N36 at their gates.

  Since the signal output from the inverter 608 is a signal obtained by inverting the signal output from the inverter 611, the carrier is induced at the gate of the transistor 609, that is, the node N 36, when the carrier is generated at the gate of the transistor 610, that is, the node N 37. It has a phase difference of 180 degrees with the induced timing.

  When inverter 611 outputs an “H” level signal to the source and drain of transistor 610, electrons flow from ground voltage GND to node N37 via transistor 612. Then, the potential on node N37 further decreases, and electrons further flow from ground voltage GND to node N37 via transistor 613. Therefore, the potential on node N37 decreases in proportion to the period during which the signal output from inverter 611 is held at "H" level, that is, the period during which clock signal CLK is held at H level.

  Then, the transistor 614 has a wider channel width in response to a decrease in the potential on the node N37, and the amount of electrons supplied from the ground voltage GND to the node N36 increases. In this case, the inverter 608 outputs an “L” level signal to the source and drain of the transistor 609, so that the electrons of the node N 36 are supplied to the node N 38 via the turned-on transistor 615. Node N38 outputs a negative voltage VBB of -1.0V.

  When inverter 611 outputs an “L” level signal to the source and drain of transistor 610, and inverter 608 outputs an “H” level signal to the source and drain of transistor 609, the electrons on node N 37 cause transistor 612 to be output. To ground voltage GND, and the potential on node N37 rises.

  Then, electrons flowing from ground voltage GND to node N36 through transistor 614 decrease, and the potential on node N36 increases. Then, electrons flowing from the node N36 to the node N38 through the transistor 615 also decrease, and the potential on the node N38 also increases.

  After that, when the inverter 611 outputs an “H” level signal to the source and drain of the transistor 610 and the inverter 608 outputs an “L” level signal to the source and drain of the transistor 609, the node N38 is -1.0V negative voltage VBB is output.

  Thus, negative voltage pump circuit 16 outputs negative voltage VBB of −1.0 V while repeating the cycle of setting the potential on node N38 to a large negative potential and the cycle of slightly increasing the potential on node N38. To do. The operation of repeating the cycle of setting the potential on the node N38 to a large negative potential and the cycle of slightly increasing the potential on the node N38 corresponds to the pumping operation.

  Negative voltage detection circuit 14 and negative voltage pump circuit 16 according to the first embodiment of the present invention operate in response to input of control signal OUTB and clock signal CLK when control signal PWRDWN is at "L" level as described above. When the control signal PWRDWN is at “H” level, the current path of the negative voltage detection circuit 14 is cut off and inactivated, and the control signal OUTB input to the negative voltage pump circuit 16 is also at “L” level. In order to maintain the state, the negative voltage pump circuit 16 does not operate. Therefore, in the low power consumption mode, that is, when the control signal PWRDWN is at “H” level, the negative voltage detection circuit 14 and the negative voltage pump circuit 16 can reduce power consumption. Note that the negative voltage detection circuit 14 and the negative voltage pump circuit 16 are designed to have low impedance unlike the above-described reference voltage generation circuit, so that the amount of operation current is also high, and the shift is made from the low power consumption mode to the normal mode. Can also return quickly.

FIG. 9 is a circuit configuration diagram of VDC circuit 17 according to the first embodiment of the present invention.
Referring to FIG. 9, VDC circuit 17 according to the first embodiment of the present invention includes transistors 700 to 706 and an AND circuit 707.

  Transistor 700 is arranged between power supply voltage VDDH and node N40, and has its gate electrically coupled to node N40. Transistor 702 is arranged between nodes N40 and N41, and has a gate receiving internal power supply voltage VDDS generated from the output node of VDC circuit 17. Transistor 701 is arranged between power supply voltage VDDH and node N42, and has its gate electrically coupled to node N40. Transistor 703 is arranged between nodes N42 and N41, and has a gate receiving reference voltage VREFS. Transistor 704 is arranged between node N41 and ground voltage GND, and its gate receives the output of AND circuit 707. Transistor 705 is arranged between power supply voltage VDDH and output node N43, and has its gate electrically coupled to node N40. Transistor 706 is arranged between power supply voltage VDDH and node N40, and has its gate electrically coupled to control signal / PWRDWN. Note that the transistors 700 to 704 and the AND circuit 707 form a comparator 708.

  In VDC circuit 17 according to the first embodiment of the present invention, AND circuit 707 outputs “H” level based on both control signal ACT and control signal / PWRDWN being at “H” level. In response to this, the transistor 704 is turned on, a current path is formed between the power supply voltage VDDH and the ground voltage GND, and the comparison unit 708 of the VDC circuit 17 is activated. In response to this, the reference voltage VREFS and the internal power supply voltage VDDS generated from the output node of the VDC circuit 17 are compared, and a signal corresponding to the comparison is generated at the output node N40. The transistor 705 is turned on according to the voltage level generated at the node N40, and the internal power supply voltage VDDS obtained by stepping down the power supply voltage VDDH is generated at the node N43. For example, when the internal power supply voltage VDDS and the reference voltage VREFS are compared and the internal power supply voltage VDDS is higher than the reference voltage VREFS, the node N40 is set to the “H” level, and the internal power supply voltage VDDS is set to the reference voltage. When it is lower than VREFS, the node N40 is set to the “L” level.

  When control signal / PWRDWN is set to “L” level, transistor 706 is turned on, and power supply voltage VDDH and node N40 are electrically coupled, so that transistor 705 is forcibly turned off and transistor 705 is turned off. The leakage from the power supply voltage VDDH to the node N43 is cut. On the other hand, when control signal / PWRDWN is set to the “H” level, transistor 706 is turned off.

  Therefore, in the low power consumption mode, that is, when the control signal PWRDWN is at the “L” level, the VDC circuit 17 is deactivated, so that the power consumption can be reduced. Since the VDC circuit 17 is designed to have a low impedance unlike the above-described reference voltage generation circuit, the VDC circuit 17 has a high operating current amount and can return at a high speed even when shifting from the low power consumption mode to the normal mode.

FIG. 10 is a schematic configuration diagram of push-pull circuit 18 according to the first embodiment of the present invention.
Referring to FIG. 10, push-pull circuit 18 according to the first embodiment of the present invention includes transistors 707 to 713. Transistors 707 and 708 are arranged between internal power supply voltage VDDS and node N46, and have their gates electrically coupled to control signal PWRDWN and node N45. Transistor 709 is provided between node N46 and node N46 #, and has its gate electrically coupled to node N46. Transistor 710 is provided between node N46 # and node N44, and has its gate electrically coupled to node N44. Transistor 711 is connected between node N44 and ground voltage GND, and has its gate electrically coupled to node N45. Transistor 712 is connected between internal power supply voltage VDDS and node N45, and has its gate electrically coupled to node N46. Transistor 713 is connected between node N45 and ground voltage GND, and has its gate electrically coupled to node N44.

  Node N44 is set to 0.6V, which is an intermediate voltage of internal power supply voltage VDDS = 1.2V, in accordance with transistors 709 and 710. The voltage level of node N46 is set to 0.6V + Vthn (Vthn: threshold voltage of transistor 709).

  Further, the voltage level of the node N44 is set to 0.6V-Vthp (Vthp: threshold voltage of the transistor 710).

  In response to this, transistors 712 and 713 operate and output from node N45 as a voltage level of 0.6 V, which is 1/2 the voltage level of internal power supply voltage VDDS.

  Here, when the control signal / PWRDWN is at the “L” level, the transistor 707 is turned on to form a current path flowing through the push-pull circuit 18, the push-pull circuit 18 is activated, and the internal power supply voltage VBL is When the control signal / PWRDWN is at “H” level, the transistor 707 is turned off, the current path is cut off, and the push-pull circuit 18 is deactivated.

  Therefore, in the low power consumption mode, that is, when the control signal PWRDWN is at the “H” level, the push-pull circuit 18 is deactivated and the power consumption can be reduced. Since the push-pull circuit 18 is designed to have a low impedance unlike the above-described reference voltage generation circuit, the push-pull circuit 18 can operate at a high speed even when the operating current amount is high and the mode is shifted from the low power consumption mode to the normal mode. .

  FIG. 11 is a diagram illustrating the voltage level of the internal power supply voltage in the normal mode and the low power consumption mode according to the first embodiment of the present invention.

  Referring to FIG. 11, here, at time T0, the normal mode in which the activation command is not input, that is, the standby time. It is assumed that an activation command is input at time T1 and the time is active. For example, in the case of a memory, a read command for instructing data reading or a write command for instructing data writing is input. In response to this, in the case of the memory, a predetermined operation such as data reading or data writing is executed. In the normal mode, control signals PWRDWN, / PWRDWN are set to “L” level and “H” level, so that internal power supply voltage generator VCRT is activated and internal power supply voltages VPP, VDDS, VBB are activated. Are set to 2.7V, 1.2V, and -1V, respectively. The power supply voltage VDDH and the ground voltage GND are 2.5V and 0V. When the input of the activation command is completed at time T2, the standby mode is resumed.

  On the other hand, when the mode is shifted to the low power consumption mode at time T3, control signals PWRDWN and / PWRDWN are set to the “H” level and the “L” level, respectively. In response to this, the internal power supply voltage generation unit VCRT is deactivated, and the internal power supply voltages VPP, VDDS, and VBB gradually transition to 0V due to leakage. In the external direct connection power down mode, internal power supply voltage generator VCRT # is activated, so that the power supply voltage directly supplied from the outside and the internal power supply voltage are electrically coupled. Specifically, the power supply voltage VDDH supplied from the outside is supplied as the internal power supply voltage VPP. Further, the power supply voltage VDDS supplied from the outside is supplied as the internal power supply voltage VDDS. Also, ground voltage GND supplied from the outside is supplied as internal power supply voltage VBB. As a result, the voltage level of the internal power supply voltage supplied to the inside of the circuit is slightly lowered so that power consumption can be reduced, and for example, the logic level (“H” of the internal state of the circuit such as a memory circuit). "Level" or "L" level).

  In the deep power down mode, which is the low power consumption mode in the first embodiment, as described above, by providing the capacitor that holds the state of the internal node of the reference voltage generation circuit, the internal power supply voltage VPP, Even when VDDS and VBB gradually transition to 0 V, the voltage of the intermediate node of the reference voltage generation circuit can be maintained. Note that, at time T4, a case where an activation command is input in the low power consumption mode is shown, but in this case, the circuit is not activated and becomes invalid.

  Next, at time T5, when the low power consumption mode is shifted to the normal mode, control signals PWRDWN and / PWRDWN are set to the “L” level and the “H” level, respectively. In response to this, the internal power supply voltage generating unit VCRT is activated, and the internal power supply voltages VPP, VDDS, and VBB rise from 0V to an intended voltage level.

  Since the reference voltage generating circuit according to the first embodiment of the present invention has a configuration in which the capacitor for holding the state of the internal node is provided as described above, the internal state is restored at a high speed, and the intended voltage level is rapidly reached. Will be restored. Here, a case is shown in which recovery is possible in a period of 100 ns (0.1 μs).

  On the other hand, the conventional reference voltage generation circuit is not configured to hold the state of the internal node, and thus transitions to 0 V with the passage of time. Therefore, when shifting to the normal mode, it takes a long time to restore the internal state of the high-impedance reference voltage generation circuit. Here, as an example, a case is shown in which recovery is possible in a period of 100 μs.

  In the case of shifting from the external direct connection power down mode to the normal mode, in the external direct connection power down mode, the voltage level of each internal power supply voltage is not 0 V but is set to a slightly lower voltage level than in the normal mode. Therefore, since the time required for the voltage level of each internal power supply voltage to transition to the intended voltage level in the normal mode is shortened, the case where the voltage level is restored in 20 μs is shown here.

  When the mode is shifted to the normal mode, and again at time T6, when an activation command is input, the active mode is set and a predetermined operation is performed. In the case of the external direct connection power down mode, the control signals PWRDWN and / PWRDWN continue to maintain the “H” level and the “L” level.

  Therefore, with the configuration according to the first embodiment of the present invention, in the low power consumption mode (deep power down mode), the power supply is cut off and the operating current is cut to reduce the power consumption. Even when shifting to the normal mode, a high-speed return is possible.

  In the configuration according to the first embodiment, the description has been given of the configuration in which the capacitor that holds the charge is provided in the internal node to hold the internal state. However, the capacitor also leaks. For example, a MOS capacitor having a source and a drain connected can be used as a capacitor, but the potential gradually decreases due to an off-leakage current or a gate leakage current of an adjacent transistor.

  For example, when the internal state is held using a MOS capacitor having a capacitance value of about 2 pF, the held potential drops by about 0.1 V after a few seconds. If left as it is, the held potential is lost due to leakage.

  FIG. 12 is a diagram illustrating the voltage level and internal power supply voltage of the internal node of the reference voltage generation circuit of the internal power supply voltage generation unit in the configuration according to the first embodiment of the present invention.

  FIG. 12A shows a decrease in the voltage level of the internal node when the holding time of the capacitor is 1 s and the holding time is 10 s. Here, when the charge of the capacitor is almost lost as shown, for example, at time T11, when shifting from the low power consumption mode to the normal mode, the recovery time of about 100 μs is the same as the conventional configuration. Will take.

  FIG. 12B shows a method of periodically refreshing so that the potential of the capacitor does not decrease too much. Specifically, the standby mode (normal mode) is set to about 100 ns every about 100 ms from time T10 when the normal mode is shifted to the low power consumption mode. That is, in order to set the normal mode for about 100 ns, the control signals PWRDWN, / PWRDWN are set to the “L” level and the “H” level, respectively. In response to this, the internal power supply voltage generator VCRT is activated, the power supply voltage VDDH is supplied to set the internal power supply voltages VPP, VDDS, VBB at a high speed, and the internal power supply voltages VPP, VDDS, VBB are set. Charges that set the internal state of the internal node are precharged again with respect to the capacitor provided at the internal node in the reference voltage generation circuit that generates the reference voltages VREFP, VREFB, and VREFS for generation. In this example, by repeating this operation every about 100 ms, the charge of the capacitor is refreshed and the potential of the capacitor is always held. It becomes possible to restore the internal power supply voltage at high speed.

  It should be noted that here, even in the low power consumption mode, the control signals PWRDWN, / PWRDWN are canceled and the refresh to switch to the normal mode for a moment is executed, so that a passing current flows in the circuit and power is consumed, but the power is very short, 100 ns. This is a period and is considered to be a level that can be almost ignored from the viewpoint of an increase in power consumption.

  Note that since the capacitor retention time depends on the capacitance value, providing a capacitor with a large capacitance value prolongs the period of the refresh execution (refresh cycle) and reduces the number of refreshes to consume more. Although it is possible to reduce electric power, since the area of a capacitor also increases, it can be set to an appropriate capacitance value from the viewpoint of area penalty.

  FIG. 12C shows another method of periodically refreshing so that the potential of the capacitor does not decrease too much. In FIG. 12B, the method of activating both the reference voltage generation circuit and the active voltage generation circuit and executing the refresh has been described. However, the active voltage generation circuit is not provided with a capacitor for holding the internal state. There is no need to refresh. Therefore, by refreshing only the reference voltage generation circuit and not supplying power to the active voltage generation circuit, power consumption can be further reduced. In the above configuration, the configuration in which the control signals PWRDWN and / PWRDWN are input to the reference voltage generation circuit unit 10 and the active voltage generation circuit unit 20 as the same control signal has been described. It is also possible to adopt a configuration for inputting. For example, instead of the control signals PWRDWN and / PWRDWN input to the reference voltage generation circuit unit 10, the control signals PWRDWN1 and / PWRDWN1 are input, and the control signals PWRDWN and / PWRDWN input to the active voltage generation circuit unit 20 are substituted. It is possible to input control signals PWRDWN2 and / PWRDWN2. In the low power consumption mode, the control signals PWRDWN1 and / PWRDWN input to the reference voltage generation circuit unit 10 can be activated to refresh only the reference voltage generation circuit unit 10. It is.

  Note that the timing generation of the control signal PWRDWN that shifts from the low power consumption mode to the normal mode at intervals of about 100 ms in the low power consumption mode described above, that is, the refresh cycle is defined, for example, from the communication base station to the portable device It is possible to receive a signal transmitted at a constant cycle (for example, 32 kHz) toward the outside and input it from the outside of the chip as the above-mentioned pulse signal with an interval of about 100 ms (pulse width of about 100 ns) using the signal. is there. Alternatively, it is possible to generate a similar signal using an oscillator (for a clock) mounted on a portable device and input it from the outside of the chip. The control signal / PWRDWN described above is a signal obtained by inverting the control signal PWRDWN, and is generated using an inverter or the like inside the chip.

  In this example, the internal power supply voltage generator VCRT1 provided corresponding to the memory circuit MEM1 of the semiconductor integrated circuit device 1 is reduced in power consumption in the low power consumption mode and shifted from the low power consumption mode to the normal mode. In the above description, the configuration capable of high-speed recovery has been described. However, the present invention is not limited to the internal power supply voltage generator VCRT1 provided corresponding to the memory circuit MEM1, and corresponds to other memory circuits, analog circuits, or logic circuits. The same can be applied to the provided internal power supply voltage generators VCRT2 to VCRT6.

(Embodiment 2)
In the second embodiment of the present invention, a configuration for driving the active voltage generation circuit section at high speed will be described.

  FIG. 13 is a circuit configuration diagram illustrating VDC circuit 17 # according to the second embodiment of the present invention.

  Referring to FIG. 13, VDC circuit 17 # according to the second embodiment of the present invention is different from VDC circuit 17 described in FIG. 9 in that a precharge circuit 720 is further provided.

  Precharge circuit 720 includes transistors 721 and 723, a capacitor 722, and an inverter 724.

  Transistor 721 is arranged between nodes N40 and N47, and has a gate receiving control signal / PWRDWN. Capacitor 722 is provided between node N47 and ground voltage GND. Transistor 723 is provided between ground voltage GND and node N 47, and has a gate receiving control signal / PWRDWN input through inverter 724.

  In VDC circuit 17 #, in the normal mode, control signal / PWRDWN is set at "H" level, so that transistor 706 is off. On the other hand, transistor 721 is turned on, and node N47 and node N40 electrically coupled to one electrode of capacitor 722 are electrically coupled.

  In the low power consumption mode, as control signal / PWRDWN is set to “L” level, transistor 723 is turned on, node N47 is electrically coupled to ground voltage GND, and capacitor 722 is grounded. Charged to voltage GND level.

  Again, in the normal mode, since control signal / PWRDWN is set to the “H” level, transistor 706 is turned off and transistor 721 is turned on as described above. Thereby, the control signal COMP is forcibly set to the “L” level for a predetermined period by the electric charge accumulated in the capacitor 722. As a result, the transistor 705 is turned on, and the voltage level of the internal power supply voltage VDDS increases due to the supply from the power supply voltage VDDH. In other words, in the configuration according to the second embodiment, when shifting from the low power consumption mode to the normal mode, the control signal COMP is set to the “L” level regardless of the comparison result of the comparison unit 708, whereby the VDC circuit 17 # can be driven at high speed.

FIG. 14 is a circuit configuration diagram of negative voltage detection circuit 14 # according to the second embodiment of the present invention.
Referring to FIG. 14, negative voltage detection circuit 14 # according to the second embodiment of the present invention is different from negative voltage detection circuit 14 described in FIG. 7 in that a precharge circuit 730 is further provided.

  Precharge circuit 730 includes transistors 732 and 733, a capacitor 731 and an inverter 734.

  Capacitor 731 is provided between power supply voltage VDDH and node N48. Transistor 733 is provided in parallel with capacitor 731 between external power supply voltage VDDH and node N48. The gate receives control signal / PWRDWN. Transistor 732 is provided between nodes N48 and N34, and has a gate receiving an inverted signal of control signal / PWRDWN via inverter 734.

  In the VDC circuit 14 #, in the normal mode, since the control signal / PWRDWN is set to the “H” level, the transistor 733 is off. On the other hand, transistor 732 is turned on, and node N48 and node N34 that are electrically coupled to one electrode of capacitor 731 are electrically coupled.

  In the low power consumption mode, as control signal / PWRDWN is set to “L” level, transistor 733 is turned on, node N47 is electrically coupled to power supply voltage VDDH, and capacitor 731 is connected to power supply. Charged to voltage VDDH level.

  Again, in the normal mode, since control signal / PWRDWN is set to the “H” level, transistor 733 is turned off and transistor 732 is turned on as described above. Thereby, the control signal OUTB is forcibly set to the “L” level for a predetermined period by the electric charge accumulated in the capacitor 731. As a result, the negative voltage pump circuit 16 in the subsequent stage is activated. That is, in the configuration according to the second embodiment, when shifting from the low power consumption mode to the normal mode, the control signal OUTB is set to the “L” level regardless of the detection result of the negative voltage detection circuit 14 #. Therefore, VDC circuit 17 # can be driven at high speed.

  By adopting such a circuit, the control signal is generated immediately without waiting for the comparison result of the detection circuit or the comparison unit of the VDC circuit when the normal mode is recovered from the low power consumption mode, and the internal power supply voltage generation circuit is activated. Therefore, the recovery time can be further increased.

(Embodiment 3)
In Embodiment 3 of the present invention, a configuration of a reference voltage generation circuit different from that in Embodiment 1 will be described.

FIG. 15 is a circuit configuration diagram of a reference voltage generating circuit according to the third embodiment of the present invention.
Here, a reference voltage generation circuit that generates the reference voltage VREFS is shown as an example.

  Referring to FIG. 15, the reference voltage generation circuit according to the third embodiment of the present invention has constant current generation circuit 200, constant current generation circuit 200 #, and current compared to the reference voltage generation circuit described in FIG. The difference is that voltage conversion circuit 300 is replaced with current-voltage conversion circuit 300 # and buffer circuit 400 is replaced with buffer circuit 400 #.

  The constant current generation circuit 200 # is different from the constant current generation circuit 200 in that the transistors 207 and 208 are deleted and a transistor 211 is newly provided. Since other points are similar, detailed description thereof will not be repeated. Transistor 211 is provided between ground voltage GND and transistors 205 and 206, and has a gate receiving control signal / PWRDWN.

  Current-voltage conversion circuit 300 # differs from current-voltage conversion circuit 300 in that transistor 303 is deleted and transistor 305 is newly provided. Since the other points are the same, detailed description thereof will not be repeated. Transistor 305 is provided between ground voltage GND and transistor 202, and has a gate receiving control signal PWRDWN.

  Buffer circuit 400 # differs from buffer circuit 400 in that transistor 407 is deleted and transistor 409 is newly provided. Since other points are similar, detailed description thereof will not be repeated. Transistor 409 is provided between node N10 and transistor 406, and has a gate receiving control signal / PWRDWN.

  In the reference voltage generating circuit described with reference to FIG. 4, a transistor is provided between the internal node and the capacitor so that the charge of the capacitor provided corresponding to the internal node is held in the low power consumption mode. Although it is configured so as to be disconnected, it is possible to retain electric charge in the capacitor if a discharge path is not formed from the capacitor to the ground voltage GND without providing a transistor between the internal node and the capacitor. is there.

  Therefore, in the reference voltage generating circuit according to the third embodiment of the present invention, electrical connection with ground voltage GND is reduced at a location where a current path is formed with respect to ground voltage GND, that is, a discharge path is formed. The structure similar to that shown in FIG. 4 can be realized by providing a transistor that is disconnected in the power mode.

  Specifically, in the constant current generation circuit 200 # of FIG. 15, the current path that flows to the ground voltage GND, that is, the discharge path can be cut off by turning off the transistor 211. The transistor 211 constitutes a switch SW7 that disconnects the electrical connection with the ground voltage GND and cuts off the operating current.

  In current-voltage conversion circuit 300 #, the current path that flows to ground voltage GND, that is, the discharge path, can be cut off by turning off transistor 305. The transistor 305 constitutes a switch SW8 that cuts off the operating current by disconnecting the electrical connection with the ground voltage GND.

  In buffer circuit 400 #, by turning off transistor 409, the current path that flows to ground voltage GND, that is, the discharge path, can be cut off. The transistor 409 constitutes a switch SW9 that cuts off the operating current by disconnecting the electrical connection with the ground voltage GND.

  In the configuration according to the third embodiment, since the electrical connection with ground voltage GND is controlled by switches SW7 to SW9, supply of power supply voltage VDDH and ground voltage GND is cut off from the reference voltage generation circuit. It is possible to realize a reference voltage generation circuit in which charges are held in the state holding units CU1 to CU4 and power consumption can be reduced and high-speed recovery can be performed as in the first embodiment.

  Further, since the transistor is not connected to the node where the intermediate voltages ICONST and BIASL are generated, the provision of the transistor can suppress the characteristics of the constant current generating circuit 200 from fluctuating.

(Embodiment 4)
In the above embodiment, the reference voltage generation circuit unit has been described with a configuration in which a plurality of reference voltage generation circuits having different reference voltages are provided. However, in the fourth embodiment of the present invention, the reference voltage generation circuit unit is provided. A configuration capable of reducing the number of constituent elements and reducing the layout area will be described.

FIG. 16 is a circuit configuration diagram of a reference voltage generating circuit according to the fourth embodiment of the present invention.
Referring to FIG. 16, the reference voltage generation circuit according to the fourth embodiment of the present invention is configured to share constant current generation circuit 200, current-voltage conversion circuit 300, and buffer circuit 400. The constant current generation circuit 200, the current-voltage conversion circuit 300, and the buffer circuit 400 are the same as described with reference to FIG. Note that buffer circuit 400 according to the fourth embodiment of the present invention is connected to resistor 410, which will be described later, and the size ratio of transistor 404 and transistor 405 is the same as that in FIG. 4 in order to supply current i to resistor 410. Have been adjusted differently. Specifically, when the size ratio of the transistor 404 and the transistor 405 is set to 5: 4 and a current of 10i flows from the power supply voltage VDDH to the ground voltage GND, the passing current flowing through the transistor 404 is 5i, and the transistor 405 Is set to 4i, and the remaining passing current i is adjusted to flow through the resistor 410.

  Compared to the reference voltage generation circuit according to FIG. 4, the reference voltage generation circuit according to the fourth embodiment of the present invention further includes a resistor 410 and buffer circuits 400a to 400c. Buffer circuits 400a-400c include buffer units 420-422, transistors 423, 425, 427, and capacitors 424-428.

  Resistor 410 is provided between node N11 and ground voltage GND. Each of the buffer circuits 400a to 400c is connected to the resistor 410, and the voltage level input to each of the buffer circuits 400a to 400c can be adjusted according to the position connected to the resistor 410, and constitutes a voltage generation unit. Specifically, a voltage level corresponding to the resistance division is input to each of the buffer circuits 400a to 400c according to the position where the resistor 410 is connected. In this example, an appropriate reference voltage is set to be input to each of the buffer circuits 400a to 400c by appropriately adjusting the position where each of the buffer circuits 400a to 400c is connected to the resistor 410.

  The buffer circuits 400a to 400c have the same configuration, and the buffer circuit 400a will be described here. The buffer circuit 400a includes a buffer unit 420, and the buffer unit 420 includes transistors having the same connection relationship as the transistors 401 to 406 of the buffer circuit 400. Transistor 423 is provided between output node N49 and node N50 of buffer unit 420, and control signal / PWRDWN is input to the gate of transistor 423. Capacitor 424 is provided between node N50 and ground voltage GND. The transistor 423 and the capacitor 424 have functions similar to those of the transistor 407 and the capacitor 408 of the buffer circuit 400 as described in Embodiment 1, and the capacitor 424 has the node N49 or the node N50 in the low power consumption mode. The state holding unit CU10 that holds this state is configured.

  Other buffer circuits 400b and 400c have the same configuration, and detailed description thereof will not be repeated.

Reference voltage generation in the reference voltage generation circuit according to the fourth embodiment of the present invention will be described.
The current-voltage conversion circuit 300 adjusts the resistance value of the long channel transistor 302 to set the reference voltage VREF0. Here, the reference voltage VREF0 of the current-voltage conversion circuit 300 is set to 1.5V. The reference voltage VREF0 is input to the buffer circuit 400, impedance-converted, and output as the reference voltage VREF (1.5V). Then, setting is made so that a desired reference voltage is output by resistance division using the resistor 410 at the subsequent stage of the buffer circuit 400. For example, the voltage level obtained by dividing the resistor 410 by resistance division is input to the buffer circuit 400a, and the buffer circuit 400a outputs the reference voltage VREFP (1.35V). Further, the resistor 410 is divided by resistance and the divided voltage level is input to the buffer circuit 400b, and the buffer circuit 400b sets the reference voltage VREFS (1.2V). Further, the resistor 410 is divided and the voltage level obtained by dividing the resistance is input to the buffer circuit 400c, and the buffer circuit 400c sets the reference voltage VREFB (1.0 V).

  The configuration according to the fourth embodiment of the present invention is different from the configuration according to the first embodiment in that a current-voltage conversion circuit and a buffer circuit are provided in common in each reference voltage generation circuit. With this configuration, the number of parts of the reference voltage generation circuit unit 10 can be reduced, and the layout area of the reference voltage generation circuit unit 10 can be reduced.

  The embodiment disclosed this time should be considered as illustrative in all points and not restrictive. The scope of the present invention is defined by the terms of the claims, rather than the description above, and is intended to include any modifications within the scope and meaning equivalent to the terms of the claims.

1 is a schematic diagram of a semiconductor integrated circuit device 1 according to a first embodiment of the present invention. It is a schematic block diagram illustrating an internal power supply voltage generation unit VCRT according to the first embodiment of the present invention. FIG. 6 is a diagram illustrating a relationship between a mode type and an internal power supply voltage or the like of the semiconductor integrated circuit device according to the first embodiment of the present invention. FIG. 3 is a circuit configuration diagram of a reference voltage generation circuit according to the first embodiment of the present invention. FIG. 3 is a circuit configuration diagram of a boosted voltage detection circuit 12 according to the first embodiment of the present invention. FIG. 3 is a circuit configuration diagram of a booster pump circuit 15 according to the first embodiment of the present invention. It is a circuit block diagram of the negative voltage detection circuit 14 according to Embodiment 1 of the present invention. It is a circuit block diagram of the negative voltage pump circuit 16 according to the first embodiment of the present invention. FIG. 3 is a circuit configuration diagram of a VDC circuit 17 according to the first embodiment of the present invention. It is a schematic block diagram of the push pull circuit 18 according to Embodiment 1 of this invention. It is a figure explaining the voltage level of the internal power supply voltage in the normal mode and the low power consumption mode according to the first embodiment of the present invention. FIG. 7 is a diagram illustrating a voltage level and an internal power supply voltage of an internal node of a reference voltage generation circuit of an internal power supply voltage generation unit in the configuration according to the first embodiment of the present invention. FIG. 11 is a circuit configuration diagram illustrating a VDC circuit 17 # according to a second embodiment of the present invention. FIG. 11 is a circuit configuration diagram of negative voltage detection circuit 14 # according to the second embodiment of the present invention. FIG. 9 is a circuit configuration diagram of a reference voltage generation circuit according to a third embodiment of the present invention. FIG. 7 is a circuit configuration diagram of a reference voltage generation circuit according to a fourth embodiment of the present invention.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 1 Semiconductor integrated circuit device, 4 Current voltage converter circuit group, 6 Buffer circuit group, 10 Reference voltage generation circuit part, 12 Boost voltage detection circuit, 14, 14 # Negative voltage detection circuit, 15 Boost voltage pump circuit, 16 Negative voltage pump circuit , 17, 17 # VDC circuit, 18 push-pull circuit, 20 active voltage generation circuit unit, 200, 200 # constant current generation circuit, 300, 300 # current voltage conversion circuit, 400, 400 #, 400a to 400c buffer circuit.

Claims (8)

A semiconductor integrated circuit device having a normal mode and a low power consumption mode,
An internal circuit for performing a predetermined operation upon receiving a supply of voltage;
An internal power supply voltage generating circuit for receiving the first external power supply voltage and the second external power supply voltage lower than the first external power supply voltage and supplying the internal power supply voltage to the internal circuit. ,
The internal power supply voltage generation circuit includes:
A reference voltage generating circuit connected to the first and second external power supply voltages to generate a reference voltage serving as a reference for generating the internal power supply voltage;
A voltage generation circuit for generating an internal power supply voltage based on the reference voltage,
The reference voltage generation circuit includes:
A first current cut-off switch for cutting off an operating current of the reference voltage generating circuit in the low power consumption mode;
A state for holding the voltage level of at least one internal node set based on the operating current in the reference voltage generation circuit when the reference voltage is generated in the normal mode during the low power consumption mode Holding part,
The voltage generation circuit includes:
The time in the low power consumption mode, a second current blocking switch for cutting off the operating current of the voltage generating circuit, the semiconductor integrated circuit device.   2. The semiconductor integrated circuit device according to claim 1, wherein the first and second current cut-off switches supply or cut off the operating current according to an input of an external instruction signal instructing the normal mode and the low power consumption mode. .   The semiconductor integrated circuit device according to claim 1, wherein the state holding unit is electrically coupled to a current path through which the operating current flows steadily in the normal mode. The state holding unit includes a capacitive element for holding the voltage level of the internal node,
4. The semiconductor integrated circuit device according to claim 3, wherein the reference voltage generation circuit further includes a switch for electrically disconnecting the current path and the capacitive element in the low power consumption mode. The voltage generation circuit includes:
A comparison unit that compares the reference voltage output from the reference voltage generation circuit with the internal power supply voltage output from the output node of the internal power supply voltage generation unit and outputs an activation signal based on a comparison result;
In response to the activation signal from the comparison unit, a voltage adjustment unit that is activated and adjusts the voltage level to follow the voltage level of the internal power supply voltage to a target level ;
Wherein and a precharge circuit for the activation signal and outputs a predetermined period when the normal mode from the low power consumption mode is instructed, the semiconductor integrated circuit device according to claim 1, wherein. The state holding unit includes a capacitive element for holding the voltage level of the internal node,
The first current cut-off switch is
A first power switch for disconnecting electrical connection with the first external power supply voltage;
The semiconductor integrated circuit device according to claim 1, further comprising: a second power switch that disconnects electrical connection with the second external power supply voltage. A semiconductor integrated circuit device having a normal mode and a low power consumption mode,
A plurality of internal circuits for receiving a voltage supply and executing predetermined operations respectively;
Internally connected to the first external power supply voltage and the second external power supply voltage lower than the first external power supply voltage, and for supplying a plurality of different internal power supply voltages to the plurality of internal circuits. Power supply voltage generation circuit,
The internal power supply voltage generation circuit includes:
A reference voltage generating circuit that receives the first and second external power supply voltages and generates a plurality of reference voltages that serve as a reference for generating the plurality of internal power supply voltages;
A plurality of voltage generation circuits for generating the plurality of internal power supply voltages based on the generation of the plurality of reference voltages;
The reference voltage generation circuit includes:
A constant current generating circuit that receives the first and second external power supply voltages and generates a common constant current;
A voltage generation unit that generates each of the plurality of reference voltages based on the constant current;
A first current cut-off switch for cutting off an operating current of the reference voltage generating circuit in the low power consumption mode;
A state for holding the voltage level of at least one internal node set based on the operating current in the reference voltage generation circuit when the reference voltage is generated in the normal mode during the low power consumption mode Holding part,
The voltage generation circuit includes:
The time in the low power consumption mode, a second current blocking switch for cutting off the operating current of each of said voltage generating circuit, the semiconductor integrated circuit device. The voltage generation unit includes a resistance element,
8. The semiconductor integrated circuit according to claim 7, wherein each of the plurality of reference voltages is generated based on a resistance value of the resistance element and the constant current, each of which is divided by a plurality of resistance divisions with respect to the resistance element. Circuit device.

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