KR100544690B1 - non-volatile MRAM cell and operating methode thereof, and ultra-high large scale integrated multi-radix MRAM using non-volatile MRAM cell - Google Patents

Abstract

The present invention relates to an operation principle and a structure of a nonvolatile magnetic memory cell using a difference in magnetoresistance according to a relative magnetization direction of a multilayer magnetic thin film. The nonvolatile magnetic memory cell of the present invention is characterized by having a magnetic pinned layer having a first magnetic pinned layer (ferromagnetic) / antiferromagnetic layer / second magnetic pinned layer (ferromagnetic) structure in which exchange biases which are antiparallel to each other are formed. By using the difference in the magnetoresistance according to the relative magnetization direction of the first and second magnetic pinned layer and the first and second magnetic free layers (ferromagnetic layers) in which the magnetization directions are fixed in parallel to each other by the exchange bias formed in parallel, A nonvolatile magnetic memory unit cell having a base or quadratic information storage capability is implemented. The unit cell may be applied to both magnetic memory devices using a large magnetoresistance (GMR) or a tunneling magnetoresistance (TMR) as an information reading method, and a method of implementing a pulverization method by stacking the above unit cells; It provides the structure, thereby implementing a nonvolatile ultra-high density magnetic memory.

Quaternary, Minced, Magnetic Memory Device, Nonvolatile, Magnetic Thin Film, Exchange Bias, Giant Magnetoresistance

Description

Non-volatile magnetic memory cell, an operation method and a non-volatile MRAM using the same, and an ultra-high large scale integrated multi-radix MRAM using non-volatile MRAM cell}

1A is a schematic diagram of a specimen for implementing a magnetically fixed layer having an anti-parallel exchange bias proposed by the present invention

FIG. 1B is a transmission electron microscope (TEM) image of the cross section of the specimen of FIG. 1A

Figure 1c is the hysteresis curve of the specimen of Figure 1a measured at room temperature using the Kerr rotation angle

FIG. 2A shows the magnetization direction of each magnetic pinned layer according to a specific external magnetic field on the magnetic hysteresis curve and the magnetic hysteresis curve measured using the rotation angle of the specimen of FIG. 1A at a blocking temperature at which no exchange bias is formed.

2B, 2C, and 2D show the specimens in which the magnetization directions of the magnetic layers are arranged in an external magnetic field in the magnetic history curves of FIG. 2A and then cooled to room temperature, respectively. Magnetic hysteresis curve measured by the angle of rotation and the magnetic direction of each magnetic layer in the absence of external magnetic field

3A shows the layer structure of the nonvolatile quaternary magnetic memory unit cell proposed by the present invention and the magnetization direction of each magnetic layer.

3B is a schematic diagram of a magnetic history curve formed by the unit cell of FIG. 3A and a magnetization direction of each magnetic layer according to a change in an external magnetic field.

3c shows a relative magnetization direction between a magnetic free layer and a magnetic pinned layer which a unit cell of the present invention should have in order to store quaternary information.

4A and 4B show an arrangement of digit lines and bit lines for reading information using a large magnetoresistance and a tunneling magnetoresistance for a nonvolatile quadrupole magnetic memory cell implemented using a unit cell of the present invention, respectively.

4C is a cell arrangement constructed using the cell structure of FIG. 4A.

FIG. 4D is a cell arrangement constructed using the cell structure of FIG. 4B.

FIG. 5A is a schematic diagram of a magnetic history curve of a unit cell for a case where an exchange bias caused by a magnetic pinning layer is applied to an adjacent magnetic free layer, and a magnetization direction of each magnetic layer according to a specific external magnetic field on the magnetic history curve.

FIG. 5B shows a magnetic history curve of a unit cell predicted by computer simulation when an exchange bias caused by a magnetic pinning layer acts on an adjacent magnetic free layer.

5C and 5D illustrate a cell including one digit line and one or two bit lines when each unit cell is implemented as a nonvolatile ternary magnetic memory that reads information using a giant magnetoresistance or a tunneling magnetoresistance. Schematic

FIG. 5E shows a cell arrangement using the cell structure of FIG. 5C

FIG. 5F illustrates a cell arrangement using the cell structure of FIG. 5D

6A, 6B, 6C, and 6D illustrate the substructure of the memory cell, the magnetoresistance of the cell substructure along the magnetization direction of the first magnetic free layer 301, the superstructure of the memory cell, and the second, respectively. Magnetoresistance size of the cell superstructure according to the magnetization direction of the magnetic free layer 307

6E is a change in magnetoresistance according to the relative magnetization directions of the magnetic free layers and the magnetic pinned layers constituting the unit cell of the present invention.

FIG. 6F illustrates a change in magnetoresistance of a unit cell according to an external magnetic field predicted through computer simulation when an exchange bias caused by a magnetic pinning layer acts on an adjacent magnetic free layer.

7A is a schematic representation of a magnetic pinned layer with parallel exchange bias

FIG. 7B illustrates the magnetization direction of each magnetic layer according to the magnetic hysteresis curve and the external magnetic field of FIG. 7A.

FIG. 7C illustrates a change in magnetoresistance according to the magnetic hysteresis curve and external magnetic field of a unit cell predicted by computer simulation when using a magnetic pinned layer having an exchange bias parallel to the unit cell of the present invention.

8A and 8B are schematic diagrams of a nonvolatile quantum magnetic memory implemented by stacking an array of unit cells, digit lines, and bit lines for reading information using a giant magnetoresistance or a tunneling magnetoresistance, respectively.

9A is a schematic diagram for applying a BMR (Ballistic Magneto Resistance) effect to a unit cell of the present invention

9B is a schematic diagram for adjusting the free layer magnetization direction of a unit cell with stress induced magnetic anisotropy according to voltage;

The present invention relates to the operation principle and structure of a nonvolatile quaternary magnetic memory cell using a magnetic pinned layer having an antiparallel exchange bias, and more particularly, to a nonparallel quaternary magnetic memory cell of the present invention. And a magnetically fixed layer having a first magnetically fixed layer (ferromagnetic layer) / antiferromagnetic layer / second magnetically fixed layer (ferromagnetic layer) structure having a bias formed thereon, and being fixed in parallel to each other by an anti-parallel exchange bias. Quadratic non-volatile information per unit cell is stored and read using the change of magnetoresistance according to the magnetization direction of the first and second magnetic pinned layers and the relative magnetization direction of the first and second magnetic free layers (ferromagnetic layers). A magnetic memory implementation that can be done.

The main object of the present invention is to implement an ultra-high density nonvolatile multi-factor device through stacking of unit cells, which is a method of increasing the density without reducing the area of the unit cell and the distance between the unit cells in order to increase the information storage density. To provide. Therefore, the area of the cell is reduced and the spacing between the cells is reduced to increase the density of the MRAM, thereby solving the problem of localization of the switching magnetic field for recording information and information loss due to the interaction between cells.

In addition, the unit cell of the present invention uses the BMR effect of the ferromagnetic nano contact formed in the insulating layer between the magnetic pinned layer and the magnetic free layer in order to increase the signal-to-noise ratio, according to the relative magnetization direction of each magnetic layer. In order to solve the problem of localization of the magnetic field for controlling the magnetization direction of each magnetic free layer, the magnetization direction of the magnetic free layer may be controlled by stress induced magnetic anisotropy according to voltage.

A typical random access memory cell (DRAM) is composed of a field effect transistor (FET) and a linear capacitor. Since the dielectric in the linear capacitor is polarized by an external voltage, the dielectric is used to store data by storing charge in the dielectric. However, the charge stored in the linear capacitor is discharged by itself, so the periodic rewriting process is essential. Thus, in the event of a power failure, all stored information is lost.

Recently, a key technical issue in the field of advanced information storage devices is to implement an ideal nonvolatile device. Recently, the most popular technology is the ferroelectric random access memory (FRAM) using the spontaneous polarization of the ferroelectric and the magnetism using the difference of magnetoresistance (giant magnetoresistance or tunneling magnetoresistance effect) according to the relative magnetization direction of the magnetic thin film. Random Access Memory (MRAM).

FRAM has the advantage that the existing DRAM technology can be applied as it is. When the dielectric film interposed between the linear capacitors of the DRAM is replaced with a ferroelectric film, the ferroelectric film stores information in the form of spontaneous polarization, and the charges accumulated by the spontaneous polarization are non-discharged. However, the ferroelectric thin film loses its capability as a nonvolatile memory device because the ferroelectric thin film causes fatigue phenomenon in which spontaneous polarization effect is reduced when the direction of polarization is changed several times. Therefore, in the case of FRAM, developing a ferroelectric thin film resistant to fatigue is a key task of implementing the technology.

MRAM is classified into two types, using a large magnetoresistance effect or a tunneling magnetoresistance effect as an information reading method. In the case of MRAM using the giant magnetoresistive effect (the existing MRAM technology using the giant magnetoresistive effect described below is described in US Pat. No. 5,343,422), the unit cell is a substrate / spacer layer / first ferromagnetic layer (magnetic free layer). ) / Bit line (conductive layer-read, write line) / second ferromagnetic layer (magnetic fixed layer) / anti-ferromagnetic layer / digit line (conductive layer-write line). The first ferromagnetic layer (magnetic free layer) can easily adjust the magnetization direction by using a magnetic field change by a digit line using a soft magnetic material, and the second ferromagnetic layer (magnetic fixed layer) Since the exchange bias is formed, the magnetization direction does not change even when the magnetic field is changed by the digit line. Accordingly, the magnetoresistance of the bit line varies according to the relative magnetization directions of the first ferromagnetic layer (magnetic free layer) and the second ferromagnetic layer (magnetic pinned layer), and the binary information is stored using the bit line.

Large magnetoresistance effect In order for MRAM to have non-volatile characteristics, the magnetization direction of the first ferromagnetic layer (magnetic free layer) should not be changed by the magnetic field caused by the "read" current of the bit line. For this purpose, the easy magnetization axis is formed parallel to the "write" magnetic field by the digit line and perpendicular to the "read" or "write" magnetic field direction by the bit line by varying the length of the unit cell in the width direction and the longitudinal direction. The magnetic field caused by the "read" current prevents the magnetization direction of the first ferromagnetic layer from changing. In particular, when the short length of the unit cell is smaller than the domain wall thickness of the ferromagnetic layer forming the magnetic free layer, the fixing effect of the easy magnetization axis is large. In addition, the magnetization direction of the first ferromagnetic layer (magnetic free layer) of a neighboring cell is changed by a "write" magnetic field to adjust the magnetization direction of the first ferromagnetic layer (magnetic free layer) of a certain cell, thereby preventing the stored information from being lost. In order to form a spacer layer on the substrate to increase the distance between the adjacent cells.

In the large magnetoresistive effect MRAM, both digit lines and bit lines are used for " write " to selectively store information in each unit cell. In general, magnetization in a state in which the magnetic field parallel to the easy magnetization axis (the magnetic field caused by the "write" current flowing through the digit line) is not large enough to reverse the magnetization direction of the first ferromagnetic layer (magnetic free layer). It can be seen that the magnetization direction of the first ferromagnetic layer is reversed when a magnetic field in the direction perpendicular to the easy axis (a magnetic field caused by a "write" current flowing in the bit line) is formed. Using this, only the first ferromagnetic layer (magnetic free layer) of a specific unit cell in the n × n unit cell array can adjust the magnetization direction.

However, in the case of using the giant magnetoresistive effect, since a plurality of unit cells are configured in series on one bit line, the size of the signal is reduced at the time of reading. Therefore, there is a weak point when the degree of integration is increased and a large number of unit cells must be formed on one bit line.

In case of MRAM using tunneling magnetoresistance effect, MTJ (Magnetic Tunnel Junction) is used as a basic structure. The structure of MTJ (US Pat. No. 5,650,958) is based on substrate / lower electrode (conductive layer) / antiferromagnetic layer / second ferromagnetic layer (magnetic fixed layer) / tunneling layer (insulating layer) / first ferromagnetic layer (magnetic free layer) / protective layer It has a structure of (nonmagnetic layer) / upper electrode (conductive layer). Tunneling magnetoresistance MRAM using MTJ structure also has the difference of magnetoresistance according to the relative magnetization direction of the first ferromagnetic layer (magnetic free layer) and the second ferromagnetic layer (magnetic fixed layer) as in the case of MRAM using a large magnetoresistive effect Save the information with However, in the case of tunneling magnetoresistive MRAM, the "read" current flows in a direction perpendicular to the MTJ structure.

In the case of tunneling magnetoresistive MRAM, like the giant magnetoresistive effect MRAM, the first ferromagnetic layer (magnetic free layer) uses a soft magnetic material to easily adjust the magnetization direction by the "write" magnetic field of the digit line and the bit line. , The second ferromagnetic layer (magnetically fixed layer) forms an exchange bias with the antiferromagnetic layer (US Pat. No. 5,650,985), or uses a hard magnetic material (US Pat. No. 5,764,567) so that the magnetization direction is not changed by the "write" magnetic field. do.

The unit cell of the tunneling magnetoresistance effect MRAM is also different from the unit cell of the large magnetoresistance effect MRAM by varying the length in the width direction and the length direction of the unit cell so that the axis of easy magnetization is parallel to the magnetic field by the digit line and perpendicular to the magnetic field by the bit line. Form. The magnetization direction of the first free layer (magnetic free layer) of a specific cell in the n × n cell array can be adjusted using bit lines and digit lines formed perpendicular to each other (US Pat. No. 5,838,608). The effect is the same as MRAM. However, when reading stored information, a "read" current must flow perpendicular to the MTJ structure, so a current line must be measured from the line through the MTJ structure to the digit line, or a new line dedicated to "reading" below the MTJ. do.

In the case of using the tunneling magnetoresistance effect, the resistance of each unit cell changes greatly depending on the thickness of the insulating film. Therefore, information is currently stored by using a resistance difference from an adjacent comparison cell. However, when the thickness of the tunneling insulating layer between the storage cell and the comparison cell is 0.2 mm or more, it is difficult to grasp the information stored in the device. Therefore, there is a technical problem of forming an insulating film of uniform thickness on a wafer of several inches radius during the production process.

The structure of the MRAM described above has been developed through continuous efforts to increase the magnetoresistance ratio or the thermal stability. Here, a brief description will be made of an improved MRAM structure using a spacer layer and an anti-parallel coupling layer.

In the case of MRAM using exchange bias, the distance between the magnetic free layer and the magnetic pinned layer is closer when the cell size becomes smaller, and thus the ferromagnetic material of the magnetic free layer is affected by the magnetic field of the ferromagnetic material forming the magnetic pinned layer. The magnetic field generated by the magnetic pinned layer, that is, the stray field, may have a bad effect on lowering the magnetoresistance rate or increasing the coercive force of the magnetic free layer.

In particular, the MTJ structure uses the tunneling magnetoresistance effect so that the thickness of the tunneling layer is thinner than the bit line thickness of the giant magnetoresistive effect MRAM. Therefore, the distance between the magnetic pinned layer and the magnetic free layer is closer, and the magnetization of the magnetic free layer is much affected by the magnetic pinned layer. To prevent this, a nonmagnetic conductive spacer layer is formed between the insulating layer and the magnetic free layer to increase the distance between the magnetic free layer and the magnetic pinned layer. (US Pat. No. 5,764,567).

In another method, the ferromagnetic layer constituting the magnetic pinning layer is replaced with a ferromagnetic layer / semi-parallel coupling layer / ferromagnetic layer. Inserting a parallel antiparallel layer between two ferromagnetic layers arranges the magnetization direction of each ferromagnetic layer in parallel with the thickness of the antiparallel coupling layer and creates a "closed flow" of the stray field by each ferromagnetic layer. Therefore, the stray field by the magnetic pinned layer does not affect the magnetic free layer. The antiparallel bonding layer mainly uses nonmagnetic materials such as ruthenium (Ru) and shows strong antiparallel bonding at thicknesses of 2 to 8 mm 3. This is a technique already applied to spin valve sensors (domestic patent 1999-0036731, US patent application 08 / 697,396).

In the case of the conventional MRAM, the magnetization direction of the magnetic layer is adjusted by using a magnetic field. Therefore, when the distance between unit cells is narrowed to increase the degree of integration of the device, the magnetic field is adjusted by the magnetic field to adjust the magnetization direction of the magnetic free layer of one unit cell. Information stored in the cell is more likely to be lost. Therefore, in order to increase the reliability of information, a method of controlling biaxial magnetization using voltage has been developed. In particular, the technique of combining the ferromagnetic layer and the piezoelectric body with the stress-induced magnetic anisotropy according to the voltage to easily adjust the axis of magnetization of the free layer from the horizontal to the vertical plane (Korean Patent Application No. 20022-46734) does not require a magnetic field for information storage. The reliability of the information is increased and the stray field is not fundamentally generated because the information is stored using the magnetoresistance according to the magnetization directions in the vertical and horizontal directions. In addition, since information is stored using a voltage, an ultra low-power memory device can be realized.

In the case of BMR (Ballistic Magneto Resistance), which has recently attracted attention, the existing large magnetoresistance effect has only a few tens of percent of the magneto-resistance effect according to the magnetization direction of the ferromagnetic layer. (N. Garcia, M. Munoz, and Y.-W. Zhao, Phys. Rev. Lett., Vol. 82 Num. 14, p2923), and recently achieved a magneto-resistance effect of 100,000% ( Suan Z. Hau and Harsh Deep Chopra, Phys. Rev. B 67, 060401) are increasingly used in magnetic devices. In particular, in the case of the multiplex magnetic memory according to the present invention, in order to maintain the existing signal-to-noise ratio, the magnetoresistance according to the relative magnetization direction of the magnetic layer should be larger than that of the binary magnetic memory device, and thus the utilization thereof is greater.

Recently, various efforts have been made to implement the chopped properties in the existing devices. Since the multi-element element has several times the information storage capability compared to the binary element of the same area, it is very important. However, in the magnetic memory device, such as MRAM, there is an example having the binary characteristics as described in the prior art, but there is no example for the implementation of the multiplicity characteristics disclosed herein. Representative techniques of the implementation method of the multiplication method include Shibata's 4-terminal transistors and neural network transistors (US Pat. No. 6,356,136) and MFS FETs by partial switching of Ishiwara. (Japanese Laid-Open Patent Publication No. 1996-204,232, Japanese Laid-Open Patent Publication 1998-242,856, and Japanese Laid-Open Patent Publication 2000-138,351). In addition, there is a matrix type chopped ferroelectric random access memory using a leakage current of Samsung Electronics (Japanese Patent Laid-Open No. 1996-303,378, Japanese Patent Laid-Open No. 1996-056,141, Korean Laid-Open Patent 1998-031,960, and Korean Laid-Open Patent 1997-076,816).

Hereinafter, each of the conventional quantum memory cell technologies will be briefly described.

In the case of a four-terminal transistor, a transistor having two gates has been proposed in comparison with a conventional field effect transistor (FET) having one gate terminal. When there is a constant voltage difference between the source and the drain, the characteristic of the current flowing between the source and the drain is determined by the voltage of the gate. Therefore, in the case of a three-terminal transistor having one gate, a single gate voltage Vs. In the case of a four-terminal transistor having a source-drain current characteristic curve while having two gates, a plurality of gate voltages Vs. Source-drain current characteristics. By using the current characteristics of such a four-terminal transistor to implement a multi-chip memory device.

Gate voltage Vs. of 4-terminal transistors. Neural network transistors have been developed as multi-terminal devices using source-drain current characteristic curves. The neural network transistor has n multiple gates, so the multiple gate voltages Vs. It has a source-drain current characteristic curve and uses it to implement a quantum method.

However, Shibata's four-terminal transistors and neural network transistors have the disadvantages of volatility because they adopt existing DRAM technology.

In the case of the partially switched MFS FRAM (Metal-Ferroelectric-substrate FRAM) of Ishiwara, the existing gate insulating thin film is replaced with a ferroelectric insulating thin film. The voltage is applied to the gate to adjust the spontaneous polarization direction of the ferroelectric gate insulating thin film, and the configuration of the energization channel is determined by the spontaneous polarization direction. Since the polarization of the ferroelectric is nonvolatile, it is possible to implement a nonvolatile memory device. In addition, the degree of polarization can be freely adjusted by adjusting the voltage applied to the gate or the time of applying the voltage, and through this, the gate voltage Vs. It is possible to adjust the source-drain current characteristics. Thus, the partial switching of the ferroelectric gate insulating film can be used to implement a nonvolatile mining method. The use of the ferroelectric gate insulating layer does not require the area of the capacitor because the information is stored by using the resistance difference of the conduction channel itself, rather than storing the information by the electric charge stored in the capacitor. As a result, it is possible to achieve high density compared to conventional memory devices using capacitors. However, the ferroelectric used as the gate insulating film is limited to a material that can be directly deposited on the silicon, and it causes fatigue phenomenon because the device uses polarization of the ferroelectric.

In the case of Samsung's leakage current-using multi-chip device, the gate is composed of a multilayer structure of dielectric film / bottom electrode / ferroelectric film / top electrode. Due to the characteristics of the dielectric thin film and the ferroelectric thin film, a leakage current is formed at a predetermined voltage or more. In general, the dielectric generates a leakage current at a lower voltage than the ferroelectric. In this case, when the information is "written", a voltage is applied to the gate to form a conduction channel like a general metal oxide-silicon (MOS) FET, and when the information is "cleared", the dielectric thin film is formed by applying a voltage higher than the "write" to the gate. The leakage current passes through to charge the lower electrode. Through this " clear " time adjustment, it is possible to control the amount of charge stored in the lower electrode, and according to the amount of charge stored in the lower electrode, the gate voltage Vs. The source-drain current characteristics will change. By using this, a chopped memory device is implemented. Since this technique does not use the polarization of the ferroelectric, fatigue phenomenon can be prevented, and various ferroelectrics can be used since the ferroelectric thin film is formed on the lower electrode (metal). However, since information is stored as leakage charges stored in the lower electrode, it is necessary to form a special structure in order to implement it as a nonvolatile device, which appears as a process difficulty.

In order to solve the above problems, the present invention is characterized by a non-magnetic layer comprising a first magnetic pinned layer (ferromagnetic layer) / antiferromagnetic layer / second magnetic pinned layer (ferromagnetic layer) having anti-parallel exchange bias. Implement volatile quaternary magnetic memory.

More specifically, the magnetization direction of the first and second magnetic pinning layers is antiparallelly fixed to each other by anti-parallel exchange bias, and includes two conductive or insulating layers and first and second magnetic free layers. A unit cell is formed, and four magnetoresistance values according to four different relative magnetization direction states of two magnetic free layers and two magnetic pinning layers provided in the unit cell are doubled compared to conventional MRAM unit cells. Implement a nonvolatile quadrupole magnetic memory cell with information storage capability.

Existing memory cells increase the degree of integration by reducing the cell area or the cell-to-cell spacing, and thus require new technologies continuously. In particular, in order to reduce the wire width to less than 0.1 [mu] m in order to increase the density, not only has to solve the extremely difficult technical problem, but also the production cost increases exponentially. In addition, when the density of the existing MRAM is increased by the above method, information is lost due to interaction between each unit cell or localized magnetic field for information storage due to the decrease of the area of the unit cell or the gap between cells. Occurs. Since the unit cell of the present invention does not use a method such as reducing the area or spacing of the unit cell, and implements a quaternary magnetic memory to increase the degree of integration, it is possible not only to use the existing technology but also to interact with an external magnetic field or spin. This can solve the problem that the MRAM has in increasing the density of information loss. Another technical advantage of the present invention is to stack the nonvolatile quaternary magnetic memory unit cells in the height direction, thereby implementing the multiplied nonvolatile memory, thereby enabling ultra-high density nonvolatile memory cells.

In order to achieve the above object, the quaternary magnetic memory unit cell of the present invention is characterized by including a magnetic pinned layer of a ferromagnetic layer, an antiferromagnetic layer, and a ferromagnetic layer having antiparallel magnetization directions.

The magnetic pinned layer is composed of a ferromagnetic layer, an antiferromagnetic layer, and a ferromagnetic layer, and after raising the temperature above a blocking temperature at which no exchange bias is formed, the two ferromagnetic layers forming the magnetic pinned layer are antiparallel to each other. After applying an external magnetic field having a direction or cooling to room temperature in a state where the magnetic field is removed thereafter, a magnetic pinned layer having an anti-parallel magnetization direction can be formed.

The unit cell of the present invention may be configured by providing a conductive layer or an insulating layer and two magnetic free layers in the magnetic fixing layer. Therefore, the unit cell of the present invention includes a first magnetic free layer / conductive layer or an insulating layer / first magnetic pinned layer / antiferromagnetic layer / second magnetic pinned layer / conductive layer or insulating layer / second magnetic free layer. In addition, the structure of the ferromagnetic layer / anti-parallel coupling layer / ferromagnetic layer having a magnetization direction antiparallel to the first and second magnetic pinning layer to remove the stray field of the first and second magnetic pinning layer Alternatively, the spacer layer may be used to increase the distance between the magnetic free layer and the magnetic pinned layer.

In the case of reading information using a large magnetoresistance, a conductive layer is used so that the current flows in parallel with the unit cell plane, and in the case of reading information using tunneling magnetoresistance, the current flows perpendicularly to the unit cell. An insulating tunneling layer (eg Al ₂ O ₃ ) is used.

When the thickness of the conductive layer or the insulating layer is adjusted or a nonmagnetic spacer layer is formed between the magnetic free layer and the magnetic pinned layer to adjust the distance between the magnetic free layer and the magnetic pinned layer, the first and second magnetic free layers The exchange bias by the magnetic pinning layer acts on the layer, so that the hysteresis curves of the first magnetic free layer and the second magnetic free layer are separated in the positive and negative external magnetic directions. By using this, the magnetization direction of the first magnetic free layer and the second magnetic free layer is adjusted by the external magnetic field generated by one conductor.

Without using the magnetic pinned layer having the anti-parallel exchange bias and using the magnetic pinned layer having the parallel exchange bias, the magnetoresistance according to the magnetization direction of the first magnetic free layer and the first magnetic pinned layer and the second magnetic free layer and the In the present invention using the difference in the magnetoresistance according to the magnetization direction of the magnetic pinned layer, it is possible to implement a nonvolatile quaternary memory device. However, in the case of using a magnetically fixed layer with parallel exchange bias, the range of external magnetic fields available to control the magnetization direction of the magnetic free layer is reduced compared to the case of using a magnetically fixed layer with an antiparallel exchange bias. It is not easy to control the magnetization direction of layers.

In addition, since the direction of the exchange bias acting on the first magnetic free layer and the second magnetic free layer formed by controlling the distance between the magnetic free layer and the magnetic pinned layer is the same, the magnetic history curves of the first and second magnetic free layers are It is not separated. Therefore, it is not possible to independently control the magnetization directions of the first and second magnetic free layers with an external magnetic field by one conductor.

Another feature of the present invention is that the stacking of nonvolatile quadrupole magnetic memory unit cells does not reduce the area and spacing of the unit cells, and enables ultra-high density memory devices through the implementation of the multiplicity memory.

Since the unit cell of the present invention stores the chopped method information by using the magnetoresistance, in order to maintain the signal-to-noise ratio of the conventional MRAM, the magnetoresistance according to the magnetization direction must be larger than that of the conventional device. Therefore, high signal-to-noise ratios can be obtained by forming ferromagnetic nano-contacts in the insulating layer between the magnetic pinned layer and the magnetic free layer by using the BMR (Ballistic Magneto Resistance) effect according to the relative magnetization direction of each magnetic layer.

In order for the unit cell of the present invention to store the information of the quadratic method, it is necessary to independently adjust the first and second magnetic free layers. To this end, two digit lines are formed per unit cell. However, since the information stored in the adjacent magnetic free layer may be lost by the magnetic field for adjusting the magnetization direction of each magnetic free layer, the magnetization direction of each magnetic free layer may be adjusted by the stress induced magnetic anisotropy according to the voltage.

Hereinafter, a quaternary nonvolatile magnetic memory unit cell according to the present invention and a nonvolatile, ultra-high density multipolar magnetic memory device using the same will be described with reference to the accompanying drawings. In all figures, the solid arrows on the surface of the magnetic thin film indicate the magnetization direction of the ferromagnetic layer, and the dashed arrows indicate the magnetization direction of the antiferromagnetic layer interface adjacent to the ferromagnetic layer.

Since the present invention is characterized by a magnetic pinned layer having an anti-parallel exchange bias, a specimen having a structure of a ferromagnetic layer, an antiferromagnetic layer, and a ferromagnetic layer is constructed through an embodiment to realize this. This will be described with reference to FIG. 1.

1A is a schematic diagram of a specimen for implementing a magnetic pinned layer having an anti-parallel exchange bias proposed by the present invention. The detailed layer structure stacks SiO ₂ (150 nm) and Ta (5 nm), Ni ₈₁ Fe ₁₉ (8 nm), Fe ₅₀ Mn ₅₀ (20 nm), Co (3.5 nm) on the Si substrate from the bottom in order. . SiO ₂ is formed by natural oxidation, and the layers of Ta (5 nm), Ni ₈₁ Fe ₁₉ (8 nm), and Fe ₅₀ Mn ₅₀ (20 nm) have a basic pressure of 5 × 10 ^-6 Torr using DC magnetron sputtering. The Ar pressure was maintained at a high vacuum of 1 to 2 mTorr, and the stack was applied while applying an external magnetic field of 100 Oe parallel to the thin film surface. The specimen was transferred to a high vacuum MOKE chamber of 2 × 10 ^-8 Torr for measuring the rotation angle magnetic hysteresis curve, the oxide film formed on the Fe ₅₀ Mn ₅₀ thin film was removed, and the electron beam evaporation method was performed at 0.76Å / min. At the deposition rate of 3.5nm Co thin film was deposited. The specimen forms a three-layer thin film structure of ferromagnetic (Ni ₈₁ Fe ₁₉ ) / anti-ferromagnetic (Fe ₅₀ Mn ₅₀ ) / ferromagnetic (Co).

FIG. 1B is a photograph of the cross-sectional structure of the specimen of FIG. 1A observed through a transmission electron microscope (TEM). At this time, in order to prevent the oxidation of the Co thin film was observed after depositing a 1.5 nm Pd protective layer in a high vacuum chamber. Looking at the drawings it can be seen that each layer of the specimen for this embodiment forms a layer structure with a uniform thickness, and the interface between each layer is also well formed.

FIG. 1C is a magnetic history curve of the specimen of FIG. 1A measured at room temperature using a Kerr rotation angle. It can be seen that two exchange biases are formed in the ferromagnetic / antiferromagnetic / ferromagnetic triple thin film structure. The exchange bias magnetic field of the Ni ₈₁ Fe ₁₉ thin film is -170 Oe and the coercive force is 24 Oe. In addition, the size of the exchange bias magnetic field of the Co thin film is -22 Oe and the coercive force is 60 Oe.

Looking through Figure 1 it can be seen that the exchange bias is formed in parallel with the ferromagnetic layers (Co, Ni ₈₁ Fe ₁₉ ) forming the specimen of this embodiment. Therefore, in order to implement a magnetically fixed layer having an anti-parallel exchange bias to be used by the present invention, several steps must be taken. This will be described with reference to FIG. 2.

FIG. 2A illustrates the magnetization direction of the magnetic pinning layer according to a specific external magnetic field on the magnetic hysteresis curve and the magnetic hysteresis curve measured by the rotation angle of the specimen of FIG. 1A at a temperature (190 ° C.) at which an exchange bias is not formed. The exchange bias of the ferromagnetic layer / antiferromagnetic layer / ferromagnetic layer thin film of this example disappeared completely at 190 ° C. Looking at the magnetic history curve, it can be seen that the magnetization directions of the ferromagnetic layers constituting the magnetic pinning layer in the external magnetic state of FIGS. 2A and 2 are formed in parallel with each other.

In the present invention, the magnetization direction of the magnetic pinned layer is a constant in which the magnetization directions of the ferromagnetic layers are arranged in parallel in parallel after first heating the magnetic pinned layer to a temperature at which no exchange bias occurs (190 ° C in this embodiment). An external magnetic field (external magnetic field in the state (2) or (3) of FIG. 2A) is applied or thereafter cooled to room temperature in a state where the magnetic field is removed. Then, since the magnetization direction of the antiferromagnetic layer interface is arranged in the magnetization direction of the ferromagnetic layer in contact, an exchange bias is formed which is antiparallel to the interface of the antiferromagnetic layer. The magnetization direction is fixed. Therefore, the magnetic pinned layer having the anti-parallel exchange bias used in the present invention can be implemented.

2B, 2C, and 2D show the magnetization directions of the magnetic layers in the magnetic fields of (1), (2), and (3) on the magnetic hysteresis curve of FIG. 2A, respectively, and then cooled to room temperature. It is the magnetic hysteresis curve and magnetization direction measured at room temperature by the rotation angle of the cell. In each case, the magnitude of the exchange bias (H _eb ) and the coercive force (H _c ) are shown in the figure.

Since the magnetic hysteresis curve measured by the present embodiment is measured using Kerr rotation angle, which is a magneto-optical measuring method, it is not possible to compare the absolute magnetization strength of each magnetic layer by the magnetic hysteresis curve alone.

The unit cell of the present invention having a self-fixing layer having an anti-parallel exchange bias implemented in the above embodiment may be configured according to the relative magnetization directions of the first magnetic fixing layer and the first magnetic free layer, and the second magnetic fixing layer and the second magnetic free layer. Non-volatile quadratic information is stored using the difference in magnetoresistance. Hereinafter, a nonvolatile quaternary magnetic memory unit cell of the present invention will be described with reference to FIG. 3.

FIG. 3A illustrates the layer structure of the quaternary nonvolatile magnetic memory unit cell 30 proposed by the present invention and the magnetization direction of each layer. The unit cell 30 has a magnetic pinned layer 31 having an anti-parallel exchange bias as implemented through the embodiment of FIG. 2. The detailed structure of the unit cell 30 is described below from the first magnetic free layer 301, the conductive layer or the insulating layer 302, the first magnetic pinned layer 303, the antiferromagnetic layer 304, and the second magnetic pinned layer 305. ), A conductive layer or insulating layer 306, and a second magnetic free layer 307.

The anti-parallel layer 31 composed of the first magnetic pinned layer 303, the anti-ferromagnetic layer 304, and the second magnetic pinned layer 305 of the unit cell 30 is semi-parallel exchanged through the process as implemented in the embodiment. Because of the bias, the magnetization directions of the ferromagnetic layers 303 and 305 constituting each of the magnetic pinning layers are fixed in parallel to each other. Therefore, the magnetization direction does not change in the range of the external magnetic field of a certain size. The ferromagnetic layer constituting the first and second magnetic free layers 301 and 307 may use a soft magnetic material to adjust the magnetization direction to an external magnetic field in which the magnetization directions of the magnetic pinned layers 303 and 305 do not change. This will be described in detail with reference to FIG. 3B.

FIG. 3B is a schematic diagram of a magnetic history curve formed by the unit cell of FIG. 3A and a magnetization direction of each magnetic free layer according to a change in an external magnetic field. The magnetic hysteresis curve is such that the distance between the magnetic pinned layer and the magnetic free layer is sufficient so that the materials forming the first and second magnetic free layers 301 and 307 have the same magnetic characteristics. It is a schematic diagram constructed under the assumption. Looking at the magnetic hysteresis curve, the magnetic hysteresis curves of the first and second magnetic pinned layers 303 and 305 are separated in the positive and negative external magnetic directions by anti-parallel exchange biases, respectively, and the magnetization directions of the first and second magnetic pinned layers are different. The range? H is not affected by the external magnetic field.

In the magnetic hysteresis curve, the magnetic hysteresis curves of the first and second magnetic free layers 301 and 307 are magnetically identical to each other, and the magnetization layers are magnetized by the magnetic pinned layers 303 and 305. Since it is not affected by, it shows the same magnetic hysteresis curve. In addition, since the magnetic free layers 301 and 307 use a soft magnetic material to easily adjust the magnetization direction by using an external magnetic field, the magnetic hysteresis curves of the magnetic free layers 301 and 307 are positive and negative due to an exchange bias. It exists between the magnetic history curves ΔH of the first and second magnetic pinned layers 303 and 305 separated in the external magnetic direction. Accordingly, the magnetization directions of the magnetic free layers 301 and 307 may be changed by an external magnetic field within a predetermined range ΔH where the magnetization directions of the magnetic pinned layers 303 and 305 do not change. However, when looking at the magnetization direction of each magnetic free layer in a specific external magnetic field, the magnetic free layers 301 and 307 of the unit cell 30 are changed in the same direction due to the change in the external magnetic field, The magnetization direction of the first and second magnetic free layers 301 and 307 cannot be adjusted independently with one external magnetic field.

Since the unit cell 30 of the present invention stores information by using a magnetoresistance according to a relative magnetization direction of the first and second magnetic free layers 301 and 307 and the first and second magnetic pinned layers 303 and 305. In order to have the characteristics as a quaternary nonvolatile memory device, as shown in FIG. 3C, the relative magnetization directions of the first and second magnetic free layers 301 and 307 and the first and second magnetic pinned layers 303 and 305 are different from each other. You must have four states. Therefore, the magnetization directions of the first and second magnetic free layers should be independently adjustable. A method of adjusting the magnetic free layers 301 and 307 of the present invention for this purpose will be described with reference to FIG.

4A and 4B show the configuration of the digit lines and the bit lines for reading the information stored in the nonvolatile ternary magnetic memory of the present invention with a large magnetoresistance and a tunneling magnetoresistance, respectively. Since two digit lines are provided per unit cell 30, an independent external magnetic field may be applied to the first magnetic free layer 301 and the second magnetic free layer 307. Accordingly, the magnetization directions of the first magnetic free layer 301 and the second magnetic free layer 307 can be independently adjusted, and the non-volatile information of the quaternary method can be stored using the magnetization directions. When reading information by using a large magnetoresistance, a "read" current must be flowed to the conductive layers 302 and 306 to determine the relative magnetization direction state of each magnetic layer, so as shown in FIG. In the case of configuring the lines 403 and 404 and reading the information by the tunneling magnetoresistance, the "read" current must pass vertically through the unit cell 30 and pass through the tunneling (insulation layer), so that the upper and lower portions of the unit cell 30 Bit lines 407 and 408 should be constructed. In the case of using the tunneling magnetoresistance, since the digit lines 405 and 406 and the bit lines 407 and 408 are adjacent to each other, the insulating layers 308 and 309 are formed between the digit lines and the bit lines to prevent current leakage. do.

The unit cell 30 of the present invention applies the technique of the MRAM so that the length W in the width direction is shorter than the length L in the longitudinal direction, so that the axis of easy magnetization is parallel to the magnetic field by the digit line and is formed by the bit line. Form perpendicular to the magnetic field. Also, the digit lines 401, 402 or 405, 406 and the bit lines 403, 404 or 407, 408 are both used for " write " to adjust the magnetization direction of the free layer. This method has been described through the above-described "prior art," which will be omitted here.

When the unit cell 30, the digits, and the bit lines are combined, an n × n cell array may be formed. The cell arrangement in the case of using the giant magnetoresistive effect is shown in FIG. 4C, and the case of using the tunneling magnetoresistive effect is shown in FIG. 4D. Since the cell array uses both the digit line and the bit line to "write" like the conventional MRAM cell array, it is possible to selectively store information in a specific cell. The unit cell 30 of the present invention has two magnetic free layers 301 and 307, and two digit lines 401, 402 or 405, 406 and two bit lines 403, for adjusting the magnetization direction thereof. Since it has 404 or 407, 408, it is characterized by having four lines per unit cell 30. Therefore, only the magnetization directions of the first or second magnetic free layers 301 and 307 of the specific unit cells of the n × n cell array can be independently adjusted.

Compared with the conventional MRAM, the unit cell of the present invention requires twice the number of lines for storing the binary information. Since this can be a significant disadvantage in the process, the present invention provides a method for independently adjusting the magnetization directions of the first and second magnetic free layers with two lines, such as three per unit cell or an existing MRAM line arrangement. Explain through 5.

FIG. 5A shows a schematic diagram and magnetization direction of the hysteresis curve of the unit cell 30 in the case where the exchange bias by the magnetic pinned layers 303 and 305 acts on the adjacent free layers 301 and 307. In the magnetic hysteresis curve of the unit cell 30 described with reference to FIG. 3B, the magnetic hysteresis curves of the magnetic free layers 301 and 307 have a distance between the magnetic free layers 301 and 307 and the magnetic pinned layers 302 and 305. Since the first and second magnetic free layers 301 and 307 have sufficient magnetic properties without sufficient magnetic influence on each other, they appear as one magnetic history curve. However, the thickness of the conductive or insulating layers 302 and 306 of the unit cell 30 is adjusted, or a nonmagnetic spacer layer is inserted between the magnetic free layers 301 and 307 and the magnetic pinned layers 303 and 305. When the distance between the magnetic free layer and the magnetic pinned layer is properly adjusted, the exchange bias by the magnetic pinned layers 303 and 305 acts on the magnetic free layers 301 and 307. Since the magnetic pinned layers 303 and 305 have antiparallel magnetization directions, the exchange biases acting on the magnetic free layers 301 and 307 are also antiparallel to each other. Therefore, the magnetic history curves of the magnetic free layers 301 and 307 are separated in the positive and negative external magnetic directions.

Looking at the magnetization direction of each magnetic layer in the specific external magnetic state shown in the drawing, when the magnetic hysteresis curve separation of the magnetic free layers 301 and 307 is used, the first and second magnetic freedoms are the external magnetic field by one conductor. The direction of the layers can be adjusted. However, in the case of (2) and (4) in the drawing, the same magnetization direction state is used, and as the external magnetic field by one conductor, four different types of magnetic free layers 301 and 307 and magnetic pinned layers 303 and 305 are provided. Relative magnetization directions cannot be implemented. Therefore, when the magnetization direction of the magnetic free layers 301 and 307 constituting the unit cell 30 is adjusted to one conductive line, only the information of the ternary method can be stored.

5B is a magnetic history curve predicted by computer simulation when the exchange bias caused by the magnetic pinned layer affects the magnetic free layer. The figure shows simulation results assuming that NiFe and CoFe are used as ferromagnetic layers and 20ÅCu is used as the conductive layer. The size of the exchange bias by the magnetic pinning layer is determined by the thickness of the conductive or insulating layer between the magnetic pinning layer and the magnetic free layer. In general, as the thickness of the conductive layer or the insulating layer decreases, the magnitude of the exchange bias acting on the magnetic free layer by the magnetic pinning layer increases in the form of an exponential function. Therefore, if the distance between the magnetic pinned layer and the magnetic free layer is properly adjusted, three relative magnetization directions can be stored in the unit cell of the present invention with a small magnetic field, thereby storing the information of the ternary method.

5C and 5D show one digit line 501 or 504 and one digit when the unit cell 30 is implemented as a nonvolatile ternary magnetic memory that reads information using a giant magnetoresistance or a tunneling magnetoresistance, respectively. A schematic diagram of a cell comprising two bit lines 502, 503, or 505. In both cases, since one digit line 501 or 504 is provided per unit cell 30, a magnetic field by one conductor is applied to the first magnetic free layer and the second magnetic free layer. However, when the magnetic hysteresis curves of the first and second magnetic free layers are separated as described with reference to FIG. 5A, the relative magnetization directions of the respective magnetic layers representing the information of the ternary method can be expressed by the magnetic field of one conductive wire.

5E and 5F show an n × n cell arrangement combining cell structures using one digit line shown in FIGS. 5C and 5D, respectively. In the case of reading information using a giant magnetoresistance (FIG. 5E), each unit cell 30 has a “read” current flowing through two bit lines 502 and 503, so that one digit per unit cell 30 is obtained. Line 501 and two bit lines 502 and 503, and in the case of using a tunneling magnetoresistance (FIG. 5F), a " read " current passes through the two tunneling layers 302 and 306 in the bit line. One digit line 504 and one bit line 505 are provided per unit cell 30 because it must flow in the. Therefore, the nonvolatile ternary magnetic memory unit cell 30 of the present invention using the tunneling magnetoresistance effect can be applied to the wiring technology of MRAM, which used the conventional MTJ structure.

In the above description, the structure of the unit cell 30 of the present invention and the magnetization directions of the first and second magnetic free layers 301 and 307 constituting the unit cell 30 are independently adjusted so that the unit cell 30 may be in a quadratic manner or the like. We have seen how to store ternary information. Hereinafter, the hexadecimal information stored in the unit cell is read using the difference in the magnetoresistance according to the relative magnetization directions of the first and second magnetic free layers 301 and 307 and the first and second magnetic pinned layers 303 and 305. The method will be described with reference to FIG. 6.

6A, 6B, 6C, and 6D illustrate the substructure of the memory cell, the magnetoresistance of the cell substructure along the magnetization direction of the first magnetic free layer 301, the superstructure of the memory cell, and the second, respectively. The magnetoresistance of the cell superstructure along the magnetization direction of the magnetic free layer 307 is shown.

6B, R ₁ (when magnetization directions are parallel to each other) and R, which are magnitudes of magnetoresistance according to relative directions of the first magnetic free layer 301 and the first magnetic pinned layer 303 of the unit cell lower part 61 through FIG. 6B. ₂ (when the magnetization directions are antiparallel to each other), the magnetic resistance according to the relative direction of the second magnetic free layer 307 and the second magnetic pinned layer 305 of the unit cell upper part 62 is shown through FIG. 6D. The magnitudes R ₃ (when the magnetization directions are parallel to each other) and R ₄ (when the magnetization directions are half parallel to each other) are shown.

When the magnitudes of R _1, R _2, R _{3, and} R ₄ , which are the magnitudes of the magnetoresistance according to the relative magnetization directions of the respective magnetic layers shown in FIGS. 6B and 6D, are different from each other, the magnetoresistance due to the unit cell lower portion 61 and the unit The magnetoresistance by the cell top 62 can be of four combinations of different sizes. This is shown in connection with the magnetization direction of each magnetic layer is shown in Figure 6e. Referring to FIG. 6E, four magnetoresistive states appear according to the relative magnetization directions of the respective magnetic layers. When measured using the current flowing in the bit line, it is possible to read the relative magnetization direction of the magnetic layers of the four states stored in the unit cell, that is, the nonvolatile information of the quadratic method.

6F is a change in magnetoresistance according to an external magnetic field predicted by computer simulation when the exchange bias caused by the magnetic pinned layer acts on the magnetic free layer. The figure shows simulation results assuming that NiFe and CoFe are used as ferromagnetic layers and 2ÅCu is used as the conductive layer. As a result of this simulation, one external magnetic field simultaneously adjusts the magnetization directions of the first magnetic free layer and the second magnetic free layer, and thus cannot have four relative magnetization directions as shown in FIG. 6E. Therefore, ternary information can be stored per unit cell. Since the size of the exchange bias can be adjusted by adjusting the distance between the magnetic pinned layer and the magnetic free layer, it can be seen that all three magnetoresistance states can be represented in the range of a small magnetic field.

When using a method of reading stored information by four combinations of different magnitudes of the magnetoresistance by the unit cell lower portion 61 and the magnetoresistance by the unit cell upper portion 62, ferromagnetics having parallel exchange biases with each other. Even when a magnetic pinned layer composed of a layer, an antiferromagnetic layer, and a ferromagnetic layer is used, it is possible to store information in a quadratic manner per unit cell and read the stored information using a bit line. This will be described with reference to FIG. 7 in comparison with the magnetic pinned layer 31 having the anti-parallel exchange bias of the present invention.

FIG. 7A is a schematic diagram of a magnetic pinned layer 70 having parallel exchange biases, and FIG. 7B is a magnetic history curve for FIG. 7A. In addition, the magnetization directions of two ferromagnetic layers 701 and 703 forming a magnetic pinned layer in a specific external magnetic field are illustrated in FIG. 7B.

Hereinafter, FIG. 7B, which is a magnetic history curve of the pinned layer 70 having parallel exchange bias, is compared with FIG. 3B or FIG. 5A, which is a magnetic history curve of the unit cell 30 of the present invention having the anti-parallel magnetic fixed layer 31. Will be explained. First, a point to be noted in the magnetic history curve of FIG. 7B compared to FIG. 3B is a range ΔH of the external magnetic field in which the magnetization directions of the ferromagnetic layers 701 and 703 constituting the magnetic pinned layer 70 do not change. The larger the range of ΔH, the easier it is to form an external magnetic field for adjusting the magnetization direction of the magnetic free layers 301 and 307. In particular, when the degree of integration increases, it becomes difficult to uniformly generate a magnetic field for adjusting the magnetization directions of the magnetic free layers 301 and 307, and the neighboring unit cells may be affected by the magnetic field for storing information of a specific unit cell. Therefore, the range of ΔH becomes important.

Referring to the magnetic hysteresis curve of FIG. 7B, the magnetization direction of the ferromagnetic bodies 701 and 703 constituting the magnetic pinned layer does not change by the positive external magnetic field, so that the range of ΔH is larger than that of FIG. 3B. However, in order to store information through the magnetization direction of the magnetic free layer, an external magnetic field in both positive and negative directions must be applied, so the practically important range of ΔH is ΔH 'which is a range in the negative direction. In general, ΔH 'is large in the case of the magnetic pinned layer 31 having the anti-parallel exchange bias. Comparing FIG. 2B and FIG. 2D of the embodiment, it can be seen that ΔH ′ is larger than 35 Oe of the magnetic fixing layer forming the parallel exchange bias at 46 Oe in the case of the magnetic fixing layer forming the anti-parallel exchange bias.

5A, when the magnetic pinned layer 70 having the parallel exchange bias is used, the exchange bias is adjusted by adjusting the distance between the magnetic free layers 301 and 307 and the magnetic pinned layers 303 and 305. Since the second magnetic free layer acts in the same direction, the magnetic history curves of the two magnetic free layers 301 and 307 are not separated. Therefore, it is not possible to form a nonvolatile ternary magnetic memory unit cell using one digit line.

FIG. 7C shows the change in magnetoresistance according to the magnetic hysteresis curve and the external magnetic field predicted using computer simulation when using a magnetic pinned layer having an exchange bias parallel to the unit cell of the present invention. In each case, the simulation results assume that NiFe and CoFe are used as ferromagnetic layers and 20ÅCu is used as the conductive layer. As a result, since the direction of the exchange bias acting on the first and second magnetic free layers by the magnetic pinned layer is the same, the magnetic hysteresis curves of the magnetic free layers are all moved in the negative direction, and the separation of the magnetic hysteresis curves is also shown in FIG. It can be seen that small compared to. Therefore, it can be seen that adjusting each magnetic free layer independently with one digit line is more difficult than using a magnetically fixed layer having an antiparallel exchange bias.

The quaternary nonvolatile magnetic memory unit cell 30 according to the present invention described above may be stacked in a height direction to implement a nonvolatile minced magnetic memory cell, which will be described with reference to FIG. 8.

8A and 8B are schematic diagrams of a nonvolatile quantum magnetic memory implemented by stacking an array of unit cells 30, a digit line, and a bit line, each of which reads information using a giant magnetoresistance or a tunneling magnetoresistance. Since one unit cell 30 stores information of the ternary system in four different magnetization states, n unit cells can be stacked to store 4n base information. In this case, 2n digit lines 401, 402 or 405, 406 are required to adjust the magnetization directions of the magnetic free layers 301 and 307 of the unit cell 30, respectively. Since the "read" current flows into the two bit lines 403 and 404 of each unit cell 30, 2n bit lines are needed for measuring the magnetoresistance. When reading information with a tunneling magnetoresistance, only two bit lines are needed at both ends of the unit cell stack structure because the "read" current flows perpendicularly to the unit cell stack and must pass through the tunneling layer.

9A is a schematic diagram for applying a BMR (Ballistic Magneto Resistance) effect to increase the signal-to-noise ratio of a unit cell. Since the unit cell of the present invention stores the chopped method information by using the magnetoresistance, in order to maintain the signal-to-noise ratio of the conventional MRAM, the magnetoresistance according to the magnetization direction must be larger than that of the conventional device. Therefore, high signal-to-noise ratios can be obtained by forming ferromagnetic nano-contacts in the insulating layer between the magnetic pinned layer and the magnetic free layer by using the BMR (Ballistic Magneto Resistance) effect according to the relative magnetization direction of each magnetic layer.

9B is a schematic diagram for independently adjusting the first and second magnetic free layers using stress induced magnetic anisotropy. In order for the unit cell of the present invention to store information of the quadratic method, it is necessary to independently adjust the first and second magnetic free layers. To this end, two digit lines are formed per unit cell. However, since the information stored in the adjacent free layer may be lost by the magnetic field for adjusting the magnetization direction of each magnetic free layer, the magnetization direction of each magnetic free layer may be adjusted by the stress induced magnetic anisotropy according to the voltage. Through this, the reliability of the stored information can be increased, and the magnetization direction can be adjusted through the voltage, thereby implementing the ultra-low power magnetic memory device.

The present invention has a magnetoresistive layer of ferromagnetic layer / antiferromagnetic layer / ferromagnetic layer with anti-parallel exchange bias, and according to the relative magnetization directions of the first and second magnetic pinning layers and the first and second magnetic free layers, As a difference, a memory device capable of storing nonvolatile information in a quadratic system per unit cell is proposed.                     

Therefore, compared to the conventional MRAM, it is possible to achieve twice the density without reducing the area of the unit cell or the spacing between cells. As a result, the present invention can solve technical problems such as magnetic interference between each cell that must be solved as the integration of the existing MRAM increases, and localization of the magnetic field for adjusting the magnetization direction of the magnetic layer.

Existing memory devices want to increase the degree of integration by reducing the two-dimensional area of cells, wires, etc., so that ultra high integration requires new technologies such as pattern and wiring processes, and the production cost also increases exponentially. The stacking of the unit cells according to the present invention enables the implementation of a pulverization element, and if a technology capable of distinguishing the difference in magnetoresistance is provided, it is possible to store the information of the n-base system in one unit cell. Even if it is used, a dramatic improvement in the density can be expected.

Claims (27)

A first magnetic free layer; A first nonmagnetic layer; A first magnetic pinned layer; Antiferromagnetic layer; A second magnetic pinned layer; A second nonmagnetic layer; And The nonvolatile magnetic memory cell of claim 2, wherein the second magnetic free layer is sequentially stacked. The method according to claim 1, The nonvolatile magnetic memory cell further includes a digit line for writing information outside each of the first and second magnetic free layers, wherein the first and second nonmagnetic layers are bits for reading or writing information. A nonvolatile magnetic memory cell comprising lines. The method according to claim 1, In the nonvolatile magnetic memory cell, the first and second nonmagnetic layers are tunneling insulating layers, and further include bit lines for reading or writing information on the outside of each of the first and second magnetic free layers. And a digit line for writing information on the outside thereof, and an insulating layer interposed between the bit line and the digit line. The method according to claim 1, The nonvolatile magnetic memory device further includes one digit line for writing information on either outside of the first or second magnetic free layer, and a bit for reading or writing information on the first and second nonmagnetic layers. A nonvolatile magnetic memory cell comprising lines. The method according to claim 1, In the nonvolatile magnetic memory cell, the first and second nonmagnetic layers are tunneling insulating layers, and further include one digit line for writing information on either outside of the first or second magnetic free layer, and the other side is free. A nonvolatile magnetic memory cell further comprising a bit line outside the layer for reading or writing information. The method according to any one of claims 1 to 5, And the first magnetic pinned layer and the second magnetic pinned layer are magnetized in anti-parallel to each other and fixed. The method according to any one of claims 1 to 5, And the first magnetic pinned layer and the second magnetic pinned layer are magnetized and fixed in parallel with each other. The method according to any one of claims 1 to 5, And the magnetization direction of the first magnetic free layer and the second magnetic free layer is changed by an external magnetic field. The method of claim 8, And the external magnetic field is supplied by a digit line and a bit line. The method of claim 8, The intensity of the external magnetic field varying the magnetization direction of the free layer is within a range (ΔH) not affecting the magnetization direction of the fixed layer. The method according to any one of claims 1 to 5, The first magnetic free layer, the first magnetic pinned layer, the antiferromagnetic layer, the second magnetic pinned layer, and the second magnetic free layer are Ni ₈₁ Fe ₁₉ , Ni ₈₁ Fe ₁₉ , Fe ₅₀ Mn ₅₀ (or Ir ₂₁ Mn ₇₉ ), respectively. , Co ₉₀ Fe ₁₀ (or Co) and Ni ₈₁ Fe ₁₉ , or Ni ₈₁ Fe ₁₉ , Co ₉₀ Fe ₁₀ (or Co), Fe ₅₀ Mn ₅₀ (or Ir ₂₁ Mn ₇₉ ), Ni ₈₁ Fe ₁₉ and Ni ₈₁ Non-volatile magnetic memory cell, characterized in that the Fe ₁₉ material. The method according to any one of claims 1 to 5, The nonvolatile memory cell of claim 1, wherein a length direction of the stacked structure is longer than a width direction. The method according to any one of claims 1 to 5, And the non-volatile memory cell forms a magnetic axis for magnetization parallel to the magnetic field by the digit line and perpendicular to the magnetic field by the bit line. The method according to any one of claims 1 to 5, And wherein the nonvolatile memory cell identifies information by using a difference in magnetoresistance according to a relative magnetization direction of the free layer and the pinned layer. The method of claim 14, The magnitude of the magnetoresistance is R1 when the magnetic fields of the first magnetic free layer and the first magnetic pinning layer are parallel to each other, and R2 and the second magnetic field when the magnetic fields of the first magnetic free layer and the first magnetic fixing layer are parallel to each other. R3 is the case where the magnetic fields of the free layer and the second magnetic pinned layer are parallel to each other, and R1 is the case where the magnetic fields of the second magnetic free layer and the second magnetic pinned layer are parallel to each other. A nonvolatile magnetic memory cell characterized by being set to a different size. The method according to any one of claims 1 to 5, And a ferromagnetic nano contact on the first nonmagnetic layer and the second nonmagnetic layer to increase the signal-to-noise ratio of the unit cell. The method according to any one of claims 1 to 5, A conductive layer is further included between the first nonmagnetic layer and the first magnetic free layer, and between the second nonmagnetic layer and the second magnetic free layer, and a piezoelectric body is disposed outside the first magnetic free layer and outside the second magnetic free layer. And a layer, whereby the magnetization directions of the first magnetic free layer and the second magnetic free layer are independently controlled using stress-induced magnetic anisotropy. The method according to any one of claims 1 to 5, By further including a piezoelectric layer and a conductive layer between the first nonmagnetic layer and the first magnetic free layer, and between the second nonmagnetic layer and the second magnetic free layer, the first magnetic free layer and the second magnetic free layer The magnetization direction of the nonvolatile magnetic memory cell, characterized in that it is independently controlled using the stress-induced magnetic anisotropy. The first digit line, the first magnetic free layer, the first bit line, the first magnetic pinned layer, the antiferromagnetic layer, the second magnetic pinned layer, the second bit line, the second magnetic free layer, and the second digit line are sequentially stacked. Nonvolatile magnetic memory cells, The storage of the information may be performed by changing the magnetization direction of the first magnetic free layer using the first digit line and the first bit line, and by using the second digit line and the second bit line. By changing the magnetization direction, Discrimination of information is performed by detecting a difference in magnetoresistance according to a relative magnetization direction between each of the free and fixed layers by using a bit line. First digit line, insulating layer, first bit line, first magnetic free layer, first tunneling insulating layer, first magnetic fixing layer, antiferromagnetic layer, second magnetic fixing layer, second tunneling insulating layer, second magnetic free layer A nonvolatile magnetic memory cell in which a second bit line, an insulating layer, and a second digit line are sequentially stacked, The storing of the information may be performed by changing the magnetization direction of the first magnetic free layer by using the first digit line and the first bit line, and by using the second digit line and the second bit line. By changing the magnetization direction, Discrimination of information is performed by detecting a difference in magnetoresistance according to a relative magnetization direction between each of the free and fixed layers by using a bit line. Nonvolatile magnetic memory in which one digit line, a first magnetic free layer, a first bit line, a first magnetic pinned layer, an antiferromagnetic layer, a second magnetic pinned layer, a second bit line, and a second magnetic free layer are sequentially stacked In the cell, The information is stored by changing the magnetization directions of the first and second magnetic free layers using the one digit line, Determination of information is performed by detecting the difference in the magnetoresistance according to the relative magnetization direction between each of the free layer and the pinned layer by using a bit line. One digit line, the first magnetic free layer, the first tunneling insulating layer, the first magnetic fixing layer, the antiferromagnetic layer, the second magnetic fixing layer, the second tunneling insulating layer, the second magnetic free layer, and one bit line are sequentially In a non-volatile magnetic memory cell stacked in the The information is stored by changing the magnetization directions of the first and second magnetic free layers using the one digit line, Determination of the information is performed by detecting the difference in the magnetoresistance according to the relative magnetization direction between each of the free layer and the pinned layer by using one bit line. A first magnetic free layer; A first nonmagnetic layer; A first magnetic pinned layer; Antiferromagnetic layer; A second magnetic pinned layer; A second nonmagnetic layer; In a nonvolatile magnetic memory cell in which second magnetic free layers are sequentially stacked, the magnetization direction of the pinned layer is (A) heating above a blocking temperature at which no exchange bias is formed between the first and second magnetic pinned layers and the antiferromagnetic layer; (B) applying an external magnetic field or removing the applied external magnetic field such that the magnetization directions of the two magnetic pinning layers are formed parallel or antiparallel to each other at the above temperature; (C) A method of forming an exchange bias of a nonvolatile magnetic memory cell, characterized in that the magnetization direction of the magnetic pinned layer is fixed by cooling to room temperature in a state in which the magnetization direction is formed in parallel or anti-parallel. A nonvolatile magnetic memory cell comprising a first magnetic free layer, a first magnetic pinned layer, an antiferromagnetic layer, a second magnetic pinned layer, and a second magnetic free layer, SiO ₂ , the first magnetic free layer, is formed by natural oxidation of the Si substrate, and Ta, Ni ₈₁ Fe _19, and Fe ₅₀ Mn ₅₀ (or Ir ₂₁ Mn ₇₉ ), which are the buffering layer, the first magnetic pinned layer, and the antiferromagnetic layer, By using DC magnetron sputtering, Ar pressure is maintained at a predetermined size in high vacuum, and an external magnetic field of a predetermined size is applied in parallel with the thin film surface. The second magnetic fixing layer, Co ₉₀ Fe ₁₀ (or Co), is laminated. And depositing at a predetermined deposition rate using an electron beam deposition method. The method of claim 24, The high vacuum pressure is 5 × 10 ^-6 Torr, the Ar pressure is 1 ~ 2 mTorr, the size of the external magnetic field is 100 Oe, the deposition rate of the electron beam deposition method is 0.76 Å / min, characterized in that the magnetic memory cell. A chopped nonvolatile magnetic memory cell constructed by stacking the memory cells of any one of claims 1 to 5 vertically. The nonvolatile magnetic memory device of claim 1, wherein the memory cells of any one of claims 1 to 5 are arranged in a lattice shape of an n Ⅹ n array along a digit line and a bit line.

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