KR100543264B1 - Bit line sense amplifier - Google Patents

Abstract

A bit line sense amplifier is disclosed. The bit line sense amplifier includes: a differential amplifier having a first input terminal for receiving a voltage of a bit line, a second input terminal for receiving a voltage of a complementary bit line, and a first output terminal and a second output terminal; A first PMOS transistor having a power supply voltage and a gate connected to the first output terminal and connected to the second output terminal; And a second PMOS transistor having a gate connected to the power supply voltage and the second output terminal and connected to the first output terminal.

Bit line sense amplifier

Description

Bit line sense amplifier

The detailed description of each drawing is provided in order to provide a thorough understanding of the drawings cited in the detailed description of the invention.

1 is a circuit diagram of a semiconductor device having a general bit line sense amplifier.

FIG. 2 illustrates an operation timing diagram of the semiconductor device shown in FIG. 1.

3 is a circuit diagram of a semiconductor device having a bit line sense amplifier according to the present invention.

4 illustrates an operation timing diagram of the semiconductor device illustrated in FIG. 3.

The present invention relates to a semiconductor device, and more particularly to a bit line sense amplifier.

MRAM (magnetro-resistive RAM) is a non-volatile memory that is currently being researched and developed. It has fast response speed, high integration, and low power consumption.

As devices used in MRAM, various devices such as PSV (Pseudo Spin Valve), Giant Magneto-Resistance (GMR), and Spin Valve (SV) have been developed, but now magnetic tunnel junction (MTJ) Much research has been done using.

Unlike DRAM, MRAM has a different magnetro-resistance depending on the magnetization direction of MTJ. Thus, MRAM can store and read data. In the case of DRAM, the voltage difference in which the bit line sense amplifier can operate normally, that is, the voltage difference between the bit line pairs is known to be about 100-200 mV. In the case of MRAM, the voltage difference in which the bit line sense amplifier can operate normally is about 50. It is about -100mV.

Therefore, the voltage difference coming into the input terminals of the bit line sense amplifier when the MRAM is used as the memory cell is smaller than the voltage difference entering the input terminals of the sense amplifier when the DRAM is used as the memory cell. Therefore, the bitline sense amplifiers must have the ability to amplify small voltage differences quickly.

The MRAM structure known so far uses two memory cells to store different information, and a double-cell structure using a single memory cell as a reference and a reference generator (Reference) 1T-1MTJ structure that separates generator). While the twin cell structure occupies a large area, since two MTJs always store opposite values, there is an advantage in that the voltage difference between the pairs of bit lines is greater than that of other structures.

Accordingly, a technical problem of the present invention is to provide a bit line sense amplifier capable of sensing and amplifying data stored in MRAMs in a dual cell structure.

A bit line sense amplifier for achieving the technical problem is a differential amplifier having a first input terminal for receiving the voltage of the bit line, a second input terminal for receiving the voltage of the complementary bit line, the first output terminal and the second output terminal; A first switching circuit connected to a power supply voltage and the first output terminal and switched according to the voltage of the second output terminal; And a second switching circuit connected to the power supply voltage and the second output terminal and switched according to the voltage of the first output terminal.

A bit line sense amplifier for achieving the technical problem comprises a differential amplifier having a first input terminal for receiving the voltage of the bit line, a second input terminal for receiving the voltage of the complementary bit line, the first output terminal and the second output terminal; A first PMOS transistor having a power supply voltage and a gate connected to the first output terminal and connected to the second output terminal; And a second PMOS transistor having a gate connected to the power supply voltage and the second output terminal and connected to the first output terminal.

In accordance with an aspect of the present invention, a bit line sense amplifier includes: a first NMOS transistor connected between a first output terminal of the bit line sense amplifier and a common node and having a gate configured to receive a first voltage; A second NMOS transistor having a gate connected between a second output terminal of the bit line sense amplifier and the common node and receiving a second voltage; A third NMOS transistor having a gate connected between the common node and a ground voltage and having an enable signal; A first PMOS transistor having a power supply voltage and a gate connected to the first output terminal and connected to the second output terminal; And a second PMOS transistor having a gate connected to the power supply voltage and the second output terminal and connected to the first output terminal.

The bit line sense amplifier further includes a third PMOS transistor connected between the first output terminal and the second output terminal and having a gate for receiving the enable signal.

In order to fully understand the present invention, the operational advantages of the present invention, and the objects achieved by the practice of the present invention, reference should be made to the accompanying drawings which illustrate preferred embodiments of the present invention and the contents described in the accompanying drawings.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. Like reference numerals in the drawings denote like elements.

1 is a circuit diagram of a semiconductor device having a general bit line sense amplifier.

Referring to FIG. 1, the semiconductor device 100 includes a memory block 110 and a bit line sense amplifier 130. The memory block 110 includes a plurality of memory cells 111-1. 111-2, 111-3, and 111-4 and connection transistors bs1 and bs2. Each of the plurality of memory cells 111-1. 111-2, 111-3, and 111-4 includes one transistor and one MTJ element. However, the plurality of memory cells 111-1, 111-2, 111-3, and 111-4 may be implemented with DRAM.

The two memory cells 111-1 and 111-2, 111-3, and 111-4 are double cells 2T-2MTJ. Therefore, when the data on the bit line BL is logic high (or low), the data on the complementary bit line BLB may represent a logic low (or logic high).

The bit line sense amplifier 130 is composed of a differential amplifier composed of transistors M6 to M8 and a latch composed of a plurality of transistors M1, M2, M4, and M5.

When the block select signal SL_SEL is activated, data on the bit line BL and the complementary bit line BLB are input to the differential amplifier through the transistors bs1 and bs2, and the differential amplifier is connected to the bit line BL. The voltage difference of the complementary bit line BLB is amplified, and the amplified voltage difference is held and output by the latch.

Each transistor M3 and M8 controls the operation of the bit line sense amplifier 130. When the enable signal SA_EN becomes logic HIGH, transistor M8 is turned on and transistor M3 is turned off. Therefore, the bit line sense amplifier 130 operates normally.

However, when the enable signal SA_EN is logic low, the transistor M3 is turned on, so that the voltages at the output terminals Out and Outb are equal to each other.

FIG. 2 illustrates an operation timing diagram of the semiconductor device shown in FIG. 1. 2 illustrates a result of simulating the operation of the semiconductor device 100 using Hspice. When a predetermined voltage difference is generated between the bit line BL and the complementary bit line BLB, the enable signal SA_EN becomes logic high, so the bit line sense amplifier 130 amplifies the voltage difference. And latch the amplified result.

3 is a circuit diagram of a semiconductor device having a bit line sense amplifier according to the present invention. Referring to FIG. 3, the semiconductor device 300 includes a memory block 110 and a bit line sense amplifier 310.

The structure and function of the memory block 110 are the same as the structure and function of the memory block 110 shown in FIG. 1.

The bit line sense amplifier 310 includes a differential amplifier 311, a first switching circuit M11, and a second switching circuit M12.

The differential amplifier 311 includes an NMOS transistor M14 connected between the first output terminal OUT and the common node CM, an NMOS transistor M15 connected between the second output terminal OUTb and the node CM, and a common node. An NMOS transistor M16 is connected between the node CM and the ground voltage VSS.

The voltage of the bit line BL is input to the gate of the NMOS transistor M14 and the voltage of the complementary bit line BLB is input to the gate of the NMOS transistor M15. The voltage of the bit line BL is determined by the MTJ of the memory cells 111-1 or 111-3, and the voltage of the complementary bit line BLB is the MTJ of the memory cells 111-2 or 111-4. Is determined by.

The differential amplifier 311 senses and amplifies a voltage difference between the voltage of the bit line BL and the complementary bit line BLB, and outputs the amplification result to the first output terminal OUT and the second output terminal OUTb.

The first switching circuit M11 is connected between the power supply voltage VDD and the first output terminal OUT, and transmits the power supply voltage VDD to the first output terminal OUT in response to the voltage of the second output terminal OUTb. Supply. The first switching circuit M11 is preferably implemented with a PMOS transistor. The gate of the PMOS transistor M11 is connected to the second output terminal OUTb.

The second switching circuit M12 is connected between the power supply voltage VDD and the second output terminal OUTb, and transmits the power supply voltage VDD to the second output terminal OUTb in response to the voltage of the first output terminal OUT. Supply. The second switching circuit M12 is preferably implemented with a PMOS transistor. The gate of the PMOS transistor M12 is connected to the first output terminal OUT.

That is, each of the transistors M11 and M12 amplifies the voltage difference between the voltage of the first output terminal OUT and the second output terminal OUTb.

The bit line sense amplifier 310 further includes an equalization transistor M13 connected between the first output terminal OUT and the second output terminal OUTb. The equalizing transistor M13 equalizes the voltages of the respective output terminals OUT and OUTb in response to the enable signal SA_EN having a logic low in order to increase the operation speed of the bit line sense amplifier 310.

4 illustrates an operation timing diagram of the semiconductor device illustrated in FIG. 3. The operation of the semiconductor device will be described with reference to FIGS. 3 and 4 as follows.

When the enable signal SA_EN is logic low, the voltage at each output terminal OUT and OUTb is maintained at about 3.0V.

When the block select signal BL_SEL goes logic high and the enable signal SA_EN goes logic high, the voltage of the bit line BL is input to the gate of the transistor M14 through the transistor bs1 and the complementary bit line. The voltage VBLB of the BLB is input to the gate of the transistor M15 through the transistor bs2. Thus, each transistor M14 and M15 is turned on.

Since the voltage VBL of the bit line BL is higher than the voltage VBLB of the complementary bit line BLB, the voltage VOUT of the first output terminal OUT is greater than the voltage VOUTb of the second output terminal OUTb. Decreases faster. Therefore, when the voltage VOUT of the first output terminal OUT reaches the threshold voltage of the PMOS transistor M12, the PMOS transistor M12 is turned on, so that the voltage VOUTb of the second output terminal OUTb is the power supply voltage. Pull-up to the (VDD) level. At this time, the PMOS transistor M11 maintains the off state in response to the voltage of the second output terminal OUTb.

2 and 4, it can be seen that the operating performance of each of the sense amplifiers 130 and 310 is almost the same. However, the layout area for implementing the sense amplifier 310 according to the present invention is about 15% smaller than the layout area for implementing the conventional sense amplifier 130.

In general, since the bit line sense amplifiers must be installed for each bit line pair, the total area occupied by the bit line sense amplifiers in the semiconductor memory device is quite large.

However, when the bit line sense amplifier according to the present invention is used, the area occupied by all the bit sense amplifiers can be reduced while exhibiting almost the same operation speed as the conventional bit line sense amplifier.

Although the present invention has been described with reference to one embodiment shown in the drawings, this is merely exemplary, and those skilled in the art will understand that various modifications and equivalent other embodiments are possible therefrom. Therefore, the true technical protection scope of the present invention will be defined by the technical spirit of the appended claims.

As described above, the layout area of the bit line sense amplifier according to the present invention is reduced.

Claims (4)

(correction) In a bit line sense amplifier, A first input terminal bs1 for receiving the voltage of the bit line BL, a second input terminal bs2 for receiving the voltage of the complementary bit line BLB , a first output terminal OUT, and a second output terminal OUTb. Differential amplifiers M6 to M8 ; A first switching circuit (M1) connected to a power supply voltage (VDD) and the first output terminal (OUT) and switched according to the voltage of the second output terminal (OUTb ) ; And And a second switching circuit (M2) connected to said power supply voltage (VDD) and said second output terminal (OUTb) and switched in accordance with the voltage of said first output terminal (OUTb) . (correction) In a bit line sense amplifier, It has a first input terminal bs1 for receiving the voltage of the bit line BL, a second input terminal bs2 for receiving the voltage of the complementary bit line BLB , a first output terminal OUT, and a second output terminal OUTb. Differential amplifier 311 ; A first PMOS transistor (M11) having a power supply voltage (VDD) and a gate connected to the first output terminal (OUT) and connected to the second output terminal (OUTb ) ; And And a second PMOS transistor (M12) having a gate connected to said power supply voltage (VDD) and said second output terminal (OUTb) and connected to said first output terminal (OUT) . (correction) In a bit line sense amplifier, A first NMOS transistor (M14) having a gate connected between a first output terminal (OUT) of the bit line sense amplifier and a common node (CM) and receiving a first voltage; A second NMOS transistor (M15) having a gate connected between a second output terminal (OUTb) of the bit line sense amplifier and the common node (CM) and receiving a second voltage; A third NMOS transistor M16 connected between the common node CM and a ground voltage VSS and having a gate configured to receive an enable signal SA_EN ; A first PMOS transistor (M11) having a power supply voltage (VDD) and a gate connected to the first output terminal (OUT) and connected to the second output terminal (OUTb ) ; And And a second PMOS transistor (M12) having a gate connected to said power supply voltage (VDD) and said second output terminal (OUTb) and connected to said first output terminal (OUT) . (correction) The method of claim 3, The first output terminal (OUT) and the second output terminal (OUTb) is connected between the 3PMOS transistors of bit line sense according to claim 1, further comprising a (M3, M13) having a gate receiving the enable signal (SA_EN) amplifier.

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