KR100542397B1 - Sensing circuit for semiconductor memory device - Google Patents

Abstract

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a sensing circuit of a semiconductor memory device, comprising: a bias voltage generating circuit for generating a bias voltage having a predetermined potential according to a sensing enable signal; A reference cell for sensing a state of a reference cell by supplying a reference voltage generator circuit for generating a reference voltage of the same, and supplying the same voltage to a drain terminal of the reference cell according to the sensing enable signal, the bias voltage, and the plurality of reference voltages; Main cell sensing means for sensing a state of a main cell by supplying a same voltage to a drain terminal of a main cell according to the sensing means, the sensing enable signal, the bias voltage, and the plurality of reference voltages; Comprising a sense amplifier for comparing the state of the main cell to determine the output And made, is stable to improve the sensing margin in a read operation can be performed it is provided a sensing circuit of a semiconductor memory device which can improve the reliability of the device to.

Sensing Circuit, Sensing Margin, Reference Cell Programmation Prevention, Supply Voltage Detection, Multiple Reference Voltages

Description

Sensing circuit for semiconductor memory device             

1 is a conventional main cell sensing circuit diagram.

2 is a conventional reference cell sensing circuit diagram.

3 is a reference voltage voltage generation circuit diagram.

4 is a timing diagram according to a conventional sensing operation.

5 is a main cell sensing circuit diagram according to the present invention;

6 is a reference cell sensing circuit diagram in accordance with the present invention.

7 is a bias generation circuit diagram according to the present invention.

8 is a reference voltage generation circuit diagram according to the present invention.

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a sensing circuit of a semiconductor memory device. In particular, a transistor connected in parallel operates according to a plurality of reference voltages applied differently depending on the power supply voltage even when the power supply voltage is increased. The present invention relates to a sensing circuit of a semiconductor memory device capable of improving a sensing margin capable of performing a read operation, thereby improving device reliability.

In order to sense the state of the main cell of the semiconductor memory device, the state of the reference cell sensed by the reference cell sensing circuit and the state of the main cell sensed by the main cell sensing circuit are compared and the result is output. To this end, a main cell sensing circuit shown in FIG. 1, a reference cell sensing circuit shown in FIG. 2, and a reference voltage generating circuit shown in FIG. 3 for supplying a reference voltage to the main cell and the reference cell are required.

1 is a conventional main cell sensing circuit diagram, the configuration of which is as follows.

The first PMOS transistor P101 and the first NMOS transistor N101 which invert the sensing enable signal SAEN between the power supply terminal Vcc and the ground terminal Vss to output the sensing enable bar signal SAENb. Inverters connected in series are connected. A second PMOS transistor P102 driven according to the sensing enable bar signal SAENb is connected between the power supply terminal Vcc and the first node Q101. Second, third and fourth NMOS transistors N102, N103 and N104 driven according to the reference voltage VREF are connected in parallel between the first node Q101 and the second node Q102. The fifth and sixth NMOS transistors N105 and N106 driven in accordance with the sensing regulation signal SAREG are connected in series between the second node Q102 and the third node Q103. The potential of the seventh NMOS transistor N107 driven according to the sensing enable bar signal SAENb between the third node Q103 and the ground terminal Vss and the fourth node Q104 connected to the bit line of the main cell. The eighth NMOS transistor N108 which is driven in accordance with is connected in parallel. A ninth NMOS transistor N109 driven according to the potential of the third node Q103 is connected between the power supply terminal Vcc and the fourth node Q104. A tenth NMOS transistor N110 connected in a diode form is connected between the fourth node Q104 and the ground terminal Vss. A ground voltage Vss is applied to the gate terminal between the power supply terminal Vcc and the fifth node Q105 and driven according to the sensing regulation signal SAREG and the third PMOS transistor P103 which is always turned on. 11 NMOS transistors N111 are connected in series. A twelfth NMOS transistor N112 driven according to the potential of the second node Q102 is connected between the fifth node Q105 and the bit line of the main cell. The potential of the fifth node Q105 is input to one input terminal of the sense amplifier 11 as a potential according to the state of the main cell. The sense amplifier 11 inputs the fifth node Q105, which is the potential of the main cell, to one input terminal, inputs the sensing voltage SAINR of the reference cell to the other input terminal, compares the two voltages, and senses the sensing output signal ( SAOUT).

2 is a conventional reference cell sensing circuit diagram and is configured as follows.

The first PMOS transistor P201 and the first NMOS transistor N201 which invert the sensing enable signal SAEN between the power supply terminal Vcc and the ground terminal Vss to output the sensing enable bar signal SAENb. Inverters connected in series are connected. A second PMOS transistor P202 driven according to the sensing enable bar signal SAENb is connected between the power supply terminal Vcc and the first node Q201. Second, third and fourth NMOS transistors N202, N203 and N204 driven according to the reference voltage VREF are connected in parallel between the first node Q201 and the second node Q202. The fifth and sixth NMOS transistors N205 and N206 driven in accordance with the sensing regulation signal SAREG are connected in series between the second node Q202 and the third node Q203. The potential of the seventh NMOS transistor N207 driven according to the sensing enable bar signal SAENb between the third node Q203 and the ground terminal Vss and the fourth node Q204 connected to the bit line of the reference cell. The eighth NMOS transistor N208 which is driven in accordance with is connected in parallel. A ninth NMOS transistor N209 driven according to the potential of the third node Q203 is connected between the power supply terminal Vcc and the fourth node Q204. The ground voltage Vss is applied to the gate terminal between the power supply terminal Vcc and the output terminal SAINR of the reference cell sensing circuit to the third PMOS transistor P203 and the sensing regulation signal SAREG that are always turned on. The tenth NMOS transistor N210 driven along is connected in series. An eleventh NMOS transistor N211 driven according to the potential of the second node Q202 is connected between the output terminal SAINR of the reference cell sensing circuit and the bit line of the reference cell.

3 is a conventional reference voltage generation circuit diagram, the configuration of which is as follows.

A first PMOS transistor P301 is driven between the power supply terminal Vcc and the third node Q303 according to the read enable signal READEN and to which the power supply voltage Vcc is applied to the well. A second voltage is applied to the gate terminal between the power supply terminal Vcc and the first node Q301 and driven according to the sensing regulation signal SAREG and the second PMOS transistor P302 which is always turned on. One NMOS transistor N301 is connected in series. The potential of the first node Q301 becomes the reference voltage VREF. The third and fourth PMOS transistors P303 and P304 having the sensing regulation signal SAREG as the well voltage are connected in series between the first node Q301 and the second node Q302 to form a diode chain. A second NMOS transistor N302 driven according to the potential of the second node Q302 is connected between the second node Q302 and the third node Q303. The sensing regulation voltage SAREG is applied to the well between the first node Q301 and the third node Q303 and driven according to the potential of the fifth PMOS transistor P305 and the second node Q302 connected in the form of a diode. The third NMOS transistor N303 is connected in series. The fourth NMOS transistor N304 driven according to the sensing regulation signal SEREG between the third node Q303 and the ground terminal Vss and the fifth NMOS transistor N305 driven according to the read enable signal READEN. Is connected in series.

When the sensing enable signal SAEN is applied in a high state in order to sense the state of the main cell in the sensing circuit of the semiconductor memory device having the basic configuration as described above, the first PMOS transistor of the main cell sensing circuit shown in FIG. P101 is turned off, and the first NMOS transistor N101 is turned on so that the sensing enable bar signal SAENb is turned low. The second PMOS transistor P102 is turned on by the sensing enable bar signal SAENb in the low state. At this time, the second to fourth NMOS transistors N102 to N104 connected in parallel driven according to the reference voltage VREF are turned on to supply the power voltage Vcc to the second node Q102. The second node Q102 turns on the twelfth NMOS transistor N112 since the power supply voltage Vcc is supplied to maintain the high state. On the other hand, the sensing regulation voltage SAREG is applied to turn on the fifth and sixth NMOS transistors N105 and N106 to turn the third node Q103 high, thereby turning on the ninth NMOS transistor N109. . In addition, the power supply voltage Vcc is transferred to the fifth node Q105 through the third PMOS transistor P103 maintaining the turned on state and the eleventh NMOS transistor N111 maintaining the turned on state according to the sensing regulation voltage SAREG. Supplied. The voltage supplied to the fifth node Q105 is supplied to the bit line of the main cell through the twelfth NMOS transistor N12, and the potential of the fifth node Q105 is determined according to the state of the main cell. That is, if the main cell is programmed, the current path is not formed in the main cell, so that the fifth node Q105 maintains a high state. If the main cell is in the erased state, the fifth path is formed in the fifth cell. Q105) remains low. The potential of the fifth node Q105 and the sensing voltage SAINR of the reference cell are sensed by the sense amplifier 11 to read the state of the main cell.

Since the reference cell sensing method in the reference cell sensing circuit is the same as the method for sensing the state of the main cell in the main cell sensing circuit, it will be omitted.

However, when the power supply voltage Vcc is applied at a high voltage, charge coupling occurs due to a sudden increase in current in the A portions of FIGS. 1 and 2. As a result, the increased voltage increases the potential of the second node Q202 of the reference cell sensing circuit further before the reference voltage generating circuit transitions to the stable bias level as shown in part B of FIG. 4. This turns on the eleventh NMOS transistor N211 which supplies a bias to the drain of the reference cell of FIG. 2 to supply a power supply voltage to the reference cell, thereby weakly programming the reference cell. If this operation is repeated several times, the reference cell is in a program state, and thus, even if the main cell is correctly programmed or erased, a read margin may occur because the sensing margin is insufficient to sense the state of the main cell.

This phenomenon occurs when the second to fourth NMOS transistors N202 to N204 connected in parallel to maintain the bias level of the second node Q202 of the reference cell sensing circuit when the read operation is performed at a low voltage. This occurs by raising the voltage by the coupling.

An object of the present invention is a sensing circuit of a semiconductor memory device capable of preventing a read error by preventing a reference cell from being programmed by preventing a rise in a reference voltage due to a charge coupling phenomenon caused by excessive current flow due to an increase in power supply voltage. To provide.

Another object of the present invention is to provide a semiconductor memory device capable of preventing charge coupling by driving NMOS transistors connected in parallel to different reference voltages to maintain bias levels of sensing nodes of a main cell sensing circuit and a reference cell sensing circuit. To provide a sensing circuit.

Another object of the present invention is to divide them according to the power supply voltage to generate different reference voltages, and to connect in parallel to maintain the bias levels of the sensing nodes of the main cell sensing circuit and the reference cell sensing circuit using these reference voltages. The present invention provides a sensing circuit of a semiconductor memory device capable of preventing a charge coupling phenomenon by driving NMOS transistors differently according to a power supply voltage.

The present invention for achieving the above object is a bias voltage generation circuit for generating a bias voltage of a predetermined potential in accordance with the sensing enable signal, and a plurality of reference voltages that detect and vary according to the power supply voltage in accordance with the sensing enable signal And a reference voltage generating circuit for generating a voltage and a plurality of reference voltages applied differently according to the level of the power supply voltage in response to the sensing enable signal, the bias voltage, and the plurality of reference voltages. Reference cell sensing means for supplying a constant voltage to sense a state of a reference cell to output a sensing voltage of the reference cell; and a level of the power supply voltage in response to the sensing enable signal, the bias voltage, and the plurality of reference voltages; Of the reference cell by a plurality of reference voltages applied differently according to Main cell sensing means for sensing a state of the main cell by supplying a constant voltage to the in terminal at all times, and outputting a sensing voltage of the main cell, and comparing the sensing voltage of the reference cell with the sensing voltage of the main cell to determine an output Characterized in that it comprises a sense amplifier for.

delete

The present invention will be described in detail with reference to the accompanying drawings.

5 is a main cell sensing circuit diagram according to the present invention.

The first PMOS transistor P501 and the first NMOS transistor N501 which invert the sensing enable signal SAEN between the power supply terminal Vcc and the ground terminal Vss to output the sensing enable bar signal SAENb. Inverters connected in series are connected. A second NMOS transistor N502 driven according to the bias voltage Vbias is connected between the power supply terminal Vcc and the first node Q501. The third, fourth and fifth NMOS transistors N503, N504, and N505 are connected in parallel between the first node Q501 and the second node Q502. The third NMOS transistor N503 is driven according to the first reference voltage VREF1, the fourth NMOS transistor N504 is driven according to the second reference voltage VREF2, and the fifth NMOS transistor N505 is driven by the third reference voltage. It is driven according to the reference voltage VREF3. The sixth and seventh NMOS transistors N506 and N507 driven in accordance with the sensing regulation signal SAREG are connected in series between the second node Q502 and the third node Q503. The potential of the eighth NMOS transistor N508 driven according to the sensing enable bar signal SAENb between the third node Q503 and the ground terminal Vss and the fourth node Q504 connected to the bit line of the main cell. Are connected in parallel to the ninth NMOS transistor N509. A tenth NMOS transistor N510 driven according to the potential of the third node Q503 is connected between the power supply terminal Vcc and the fourth node Q504. An eleventh NMOS transistor N511 connected in a diode form is connected between the fourth node Q504 and the ground terminal Vss. A second voltage is applied to the gate terminal between the power supply terminal Vcc and the fifth node Q505 to be driven according to the sensing regulation signal SAREG and the second PMOS transistor P502 which is always turned on. 12 NMOS transistors N512 are connected in series. A thirteenth NMOS transistor N513 that is driven along the potential of the second node Q502 is connected between the fifth node Q505 and the bit line of the main cell. The potential of the fifth node Q505 is input to one input terminal of the sense amplifier 51 as a potential according to the state of the main cell. The sense amplifier 51 inputs the fifth node Q505, which is the potential of the main cell, to one input terminal, inputs the sensing voltage SAINR of the reference cell to the other input terminal, compares the two voltages, and outputs the sensing output signal ( SAOUT).

The driving method of the main cell sensing circuit according to the present invention configured as described above is as follows.

When the sensing enable signal SAEN is applied in a high state, the first PMOS transistor P501 is turned off, and the first NMOS transistor N501 is turned on so that the sensing enable bar signal SAENb is turned low. The eighth NMOS transistor N508 is turned off by the sensing enable bar signal SAENb in the low state. At this time, the second NMOS transistor N502 is turned on by the bias voltage Vbias applied to the predetermined voltage, and the third to fifth NMOS by the first to third reference voltages VREF1 to VREF3 applied to the high state. The transistors N503 to N505 are turned on to apply a power supply voltage Vcc to the second node Q502. However, when the low power supply voltage Vcc is applied, the first to third reference voltages VREF1 to VREF3 turn on the third to fifth NMOS transistors N503 to N505, but the power supply voltage Vcc rises and is applied. When the first reference voltage VREF1 is applied in a low state, the third NMOS transistor N503 is turned off. When the power supply voltage Vcc is applied above the second predetermined voltage, the second reference voltage is applied. VREF2 is applied in a low state to turn off the fourth NMOS transistor N504. As described above, since the first to third reference voltages VREF1 to VREF3 are applied according to the potential of the power supply voltage, the charge coupling phenomenon does not occur at the first node Q501. Since the second node Q502 is supplied with the power supply voltage Vcc to maintain the high state, the second node Q502 turns on the thirteenth NMOS transistor N513. Meanwhile, the sensing regulation voltage SAREG is applied to turn on the sixth and seventh NMOS transistors N506 and N507 to turn the third node Q503 high, thereby turning on the tenth NMOS transistor N510. . In addition, the power supply voltage Vcc is transferred to the fifth node Q505 through the second PMOS transistor P502 maintaining the turn on state and the twelfth NMOS transistor N512 maintaining the turn on state according to the sensing regulation voltage SAREG. Supplied. The voltage supplied to the fifth node Q505 is supplied to the bit line of the main cell through the thirteenth NMOS transistor N503, and the potential of the fifth node Q505 is determined according to the state of the main cell. That is, when the main cell is programmed, the current path is not formed in the main cell, so the fifth node Q505 maintains a high state. When the main cell is in the erased state, the fifth path Q5 is formed in the main cell. Node Q505 remains low. The potential of the fifth node Q505 and the sensing voltage SAINR of the reference cell are sensed by the sense amplifier 51 to read the state of the main cell.

6 is a reference cell sensing circuit diagram according to the present invention and is configured as follows.

The first PMOS transistor P601 and the first NMOS transistor N601 which invert the sensing enable signal SAEN between the power supply terminal Vcc and the ground terminal Vss to output the sensing enable bar signal SAENb. Inverters connected in series are connected. A second NMOS transistor P202 driven according to a bias voltage Vbias is connected between the power supply terminal Vcc and the first node Q601. The third, fourth and fifth NMOS transistors N603, N604 and N605 are connected in parallel between the first node Q601 and the second node Q602. The third NMOS transistor N603 is driven according to the first reference voltage VREF1, the fourth NMOS transistor N604 is driven according to the second reference voltage VREF2, and the fifth NMOS transistor N605 is driven by the third reference voltage VREF1. It is driven according to the reference voltage VREF3. The sixth and seventh NMOS transistors N606 and N607 driven in accordance with the sensing regulation signal SAREG are connected in series between the second node Q602 and the third node Q603. The potential of the eighth NMOS transistor N608 driven according to the sensing enable bar signal SAENb between the third node Q603 and the ground terminal Vss and the fourth node Q604 connected to the bit line of the reference cell. Are driven in parallel with the ninth NMOS transistors N609. A tenth NMOS transistor N610 driven according to the potential of the third node Q603 is connected between the power supply terminal Vcc and the fourth node Q604. The ground voltage Vss is applied to the gate terminal between the power supply terminal Vcc and the output terminal SAINR of the reference cell sensing circuit to the second PMOS transistor P602 and the sensing regulation signal SAREG that are always turned on. The eleventh NMOS transistor N611 driven along is connected in series. A twelfth NMOS transistor N612 driven according to the potential of the second node Q602 is connected between the output terminal SAINR of the reference cell sensing circuit and the bit line of the reference cell.

Referring to the driving method of the reference cell sensing circuit according to the present invention configured as described above are as follows.

When the sensing enable signal SAEN is applied in a high state, the first PMOS transistor P601 is turned off, and the first NMOS transistor N601 is turned on so that the sensing enable bar signal SAENb is turned low. The eighth NMOS transistor N508 is turned off by the sensing enable bar signal SAENb in the low state. At this time, the second NMOS transistor N602 is turned on by the bias voltage Vbias applied to the predetermined voltage, and the third to fifth NMOS by the first to third reference voltages VREF1 to VREF3 applied to the high state. The transistors N603 to N605 are turned on to apply a power supply voltage Vcc to the second node Q602. However, when the low power supply voltage Vcc is applied to the first to third reference voltages VREF1 to VREF3, the third to fifth NMOS transistors N603 to N605 are turned on, but the power supply voltage Vcc is increased to be applied. When the first reference voltage VREF1 is applied in a low state, the third NMOS transistor 6503 is turned off. When the power supply voltage Vcc is applied above the second predetermined voltage, the second reference voltage is applied. VREF2 is applied in a low state to turn off the fourth NMOS transistor N604. As described above, since the first to third reference voltages VREF1 to VREF3 are applied according to the potential of the power supply voltage, the charge coupling phenomenon does not occur at the first node Q601. The second node Q602 turns on the twelfth NMOS transistor N612 because the power supply voltage Vcc is supplied to maintain the high state. Meanwhile, the sensing regulation voltage SAREG is applied to turn on the sixth and seventh NMOS transistors N606 and N607 so that the third node Q603 becomes high, thereby turning on the tenth NMOS transistor N610. do. In addition, the power supply voltage Vcc is transferred to the fifth node Q605 through the second PMOS transistor P602 maintaining the turn on state and the eleventh NMOS transistor N611 maintaining the turn on state according to the sensing regulation voltage SAREG. Supplied. The voltage supplied to the fifth node Q605 is supplied to the bit line of the reference cell through the twelfth NMOS transistor N612, and detects the amount of current according to the state of the reference cell to detect the sensing voltage SAINR of the reference cell. Is applied to the main cell sensing circuit.

As described above, the second NMOS transistor N602 driven according to the bias voltage Vbias and the first to third reference voltages VREF1 that are differently applied according to the power supply voltage Vcc even when the power supply voltage Vcc is applied while rising. Since the power supply voltage is uniformly supplied by the third to fifth NMOS transistors N603 to N605 driven by the second through fifth reference voltages, the reference voltage is not excessively turned on to supply the twelfth NMOS transistor N602 for supplying a voltage to the reference cell. The cell can be prevented from being programmed.

7 is a bias voltage generation circuit diagram according to the present invention and is configured as follows.

The first NMOS transistor N71 and the first driven between the power supply terminal Vcc and the first node Q71 through the sensing enable signal SAEN input through the first and second inverters I71 and I72. The second PMOS transistor P72 which is driven according to the potential of the node Q71 is connected. The potential of the first node Q71 is output as a bias voltage Vbias. A second NMOS transistor N72 driven according to the potential of the second node Q72 is connected between the first node Q71 and the ground terminal Vss. A first PMOS transistor P71 driven between the power supply terminal Vcc and the second node Q72 is driven in accordance with the sensing enable signal SAEN input through the first and second inverters I71 and I72. . A third PMOS transistor P73 driven between the power supply terminal Vcc and the second node Q72 is driven according to the potential of the second node Q72. A fourth NMOS transistor N73 driven according to the potential of the first node Q71 and a power supply voltage Vcc are applied between the second node Q72 and the ground terminal Vss to always turn on. A fifth NMOS transistor N75 driven in accordance with the sensing enable signal SAEN input through the NMOS transistor N74 and the first and second inverters I71 and I72 is connected in series.

Referring to the driving method of the bias voltage generating circuit according to the present invention configured as described above are as follows.

When the sensing enable signal SAEN is applied in a high state, the first and second NMOS transistors N71 and N75 are turned on by being buffered through the first and second inverters I71 and I72 to turn on the first PMOS transistor P71. Turn off). The power supply voltage Vcc is supplied to the first node Q71 through the second PMOS transistor P72 which is turned on according to the turned-on first NMOS transistor N71 and the potential of the first node Q71. However, when the potential of the first node Q71 rises above the predetermined potential, the second PMOS transistor P72 is turned off, so that the first node Q71 maintains a constant potential. The third NMOS transistor N73 is turned on by the potential of the first node Q71 and the fourth NMOS transistor N74 and the fifth NMOS transistor N75 that are always turned on by applying the power supply voltage Vcc. ), The second node Q72 remains low. Since the second node Q72 maintains the low state, the third PMOS transistor P73 is turned on to supply the power supply voltage Vcc to the second node Q72. However, when the potential of the second node Q72 also rises above the predetermined potential, the third PMOS transistor P73 is turned off, so that the second node Q72 maintains a constant potential. Meanwhile, the second NMOS transistor N72 is turned on by the potential of the second node Q72, and the potential of the first node Q71 is supplied to the main cell sensing circuit and the reference cell sensing circuit by the bias voltage Vbias. .

8 is a circuit diagram of a reference voltage generator according to the present invention, which detects a power supply voltage and outputs three different reference voltages.

The first PMOS between the power supply terminal Vcc and the first node Q81 is driven according to the enable bar signal ENb inverted through the first to third inverters I81 to I83. Transistor P81 is connected. The potential of the first node Q81 is output to the first output terminal OUT1 through the diode chain fourth to sixth PMOS transistors P84 to P86. A second PMOS transistor P82 driven according to the potential of the second node Q82 is connected between the first node Q81 and the third node Q83. A third PMOS transistor P83 driven according to the potential of the second node Q82 is connected between the first node Q81 and the second node Q82. A first NMOS transistor N81 driven according to the enable bar signal ENb is connected between the second node Q82 and the ground terminal Vss. Second to fourth NMOS transistors N82 to N84 respectively driven in accordance with the potential of the third node Q83 are connected in series between the third node Q83 and the ground terminal Vss. A fifth NMOS transistor N85 and a fifth resistor R85 are connected between the second node Q82 and the ground terminal Vss according to the potential of the third node Q83. A sixth NMOS transistor N86 driven according to the potential of the third node Q83 is connected between the power supply terminal Vcc and the fourth node Q84, and is connected between the fourth node Q84 and the ground terminal Vss. The seventh NMOS transistor N87 driven in accordance with the potential of the fourth node Q84 and the eighth NMOS transistor N88 driven in accordance with the enable signal EN are connected to each other. The potential of the fourth node Q84 becomes the second output signal OUT2. Meanwhile, a ninth NMOS transistor N89 driven in accordance with the first to fourth resistors R81 to R84 and the enable signal EN is connected in series between the power supply terminal Vcc and the ground terminal Vss. The first to third sense amplifiers 81 to 83 compare the voltages distributed through the second output signal OUT2 and the first to fourth resistors R81 to R84 according to the enable signal EN, respectively. The first to third reference voltages VREF1 to VREF3 are output. That is, the first sense amplifier 81 may apply the voltage divided by the first to fourth resistors R81 to R84 and the first resistor R81 and the second output signal OUT2 according to the enable signal EN. In comparison, the first reference voltage VREF1 is output, and the second sense amplifier 82 generates the first to fourth resistors R81 to R84 and the first and second resistors R81 and R according to the enable signal EN. The second reference voltage VREF2 is output by comparing the voltage divided by R82 with the second output signal OUT2, and the first sense amplifier 83 is first to fourth according to the enable signal EN. The third reference voltage VREF3 is output by comparing the voltage divided by the resistors R81 to R84 and the first to third resistors R81 to R83 with the second output signal OUT2.

Referring to the driving method of the reference voltage generating circuit according to the present invention configured as described above are as follows.

The sensing enable signal SAEN of the high state is buffered and input through the first and second inverters I81 and I82 so that the first and second output signals OUT1 and OUT2 are output from the internal circuit, and the ninth NMOS. Transistor N89 is turned on. The second output signal OUT2 of the internal circuit is input to the reference terminals of the first to third sense amplifiers 81 to 83 according to the enable signal EN. The first sense amplifier 81 compares the voltage divided by the first to fourth resistors R81 to R84 and the first resistor R81 and the second output signal OUT2 according to the enable signal EN. The first reference voltage VREF1 is output, and the second sense amplifier 82 is provided with the first to fourth resistors R81 to R84 and the first and second resistors R81 and R82 according to the enable signal EN. The second reference voltage VREF2 is output by comparing the voltage divided by the second output signal OUT2 with the first sense amplifier 83 according to the enable signal EN. The third reference voltage VREF3 is output by comparing the voltage divided by the R81 to R84 and the first to third resistors R81 to R83 with the second output signal OUT2. However, when the power supply voltage Vcc rises and is applied, the voltage divided by the first to fourth resistors R81 to R84 and the first resistor R81 is lower than the potential of the second output signal OUT2 and thus the first voltage. The first reference voltage VREF1 from the sense amplifier 81 is applied in a low state. When the power supply voltage Vcc is further increased and applied, the voltages divided by the first to fourth resistors R81 to R84 and the first and second resistors R81 and R82 are also applied to the second output signal OUT2. Lower than the potential, the second reference voltage VREF2 from the first sense amplifier 82 is applied in a low state.

As described above, according to the present invention, even when the power supply voltage is applied while the power supply voltage is increased, the transistors connected in parallel operate according to the reference voltage applied differently according to the power supply voltage. Sensing margins can be improved to improve device reliability.

Claims (10)

A bias voltage generation circuit for generating a bias voltage having a predetermined potential according to the sensing enable signal; A reference voltage generation circuit for detecting a power supply voltage according to the sensing enable signal and generating a plurality of reference voltages that vary accordingly; A constant voltage is always supplied to the drain terminal of the reference cell by a plurality of reference voltages applied differently according to the level of the power supply voltage in response to the sensing enable signal, the bias voltage, and the plurality of reference voltages. Reference cell sensing means for sensing a state and outputting a sensing voltage of the reference cell; In response to the sensing enable signal, the bias voltage and the plurality of reference voltages, a constant voltage is always supplied to the drain terminal of the reference cell by a plurality of reference voltages applied differently according to the level of the power supply voltage. Main cell sensing means for sensing a state and outputting a sensing voltage of the main cell; and And a sense amplifier for determining an output by comparing the sensing voltage of the reference cell with the sensing voltage of the main cell. The circuit of claim 1, wherein the reference voltage generator circuit comprises: a plurality of resistors R81, R82, R83, R84 connected between a power supply terminal and a ground terminal; A plurality of sense amplifiers (81, 82, 83) for inputting a voltage divided sequentially by the total resistance and the resistance of each stage and output a plurality of reference voltages compared to a predetermined voltage, characterized in that Sensing circuit of semiconductor memory device. The apparatus of claim 1, wherein the reference cell sensing means comprises: a reference cell; First switching means (P602) for supplying a power supply voltage according to the bias voltage, A plurality of switching means (N603, N604, N605) connected in parallel for supplying a power supply voltage supplied through a first switching means according to the plurality of reference voltages; And a second switching means (N612) for supplying a voltage to the reference cell driven by the power supply voltage supplied through the first switching means and the plurality of switching means. Circuit. 4. The sensing circuit of claim 3, wherein the first switching means is an NMOS transistor. 4. The sensing circuit of claim 3, wherein the plurality of switching means comprise a plurality of NMOS transistors connected in parallel and driven according to a plurality of reference voltages holding different potentials. 4. The sensing circuit of claim 3, wherein the second switching means is an NMOS transistor. 2. The apparatus of claim 1, wherein the main cell sensing means comprises: a main cell; First switching means (N502) for supplying a power supply voltage according to the bias voltage; A plurality of switching means (N503, N504, N505) connected in parallel for supplying a power supply voltage supplied through a first switching means according to the plurality of reference voltages; And a second switching means (N513) for supplying a voltage to the main cell driven by the power supply voltage supplied through the first switching means and the plurality of switching means. Circuit. 8. The sensing circuit of claim 7, wherein the first switching means is an NMOS transistor. 8. The sensing circuit according to claim 7, wherein the plurality of switching means comprise a plurality of NMOS transistors connected in parallel and driven according to a plurality of reference voltages maintaining the different potentials. 8. The sensing circuit of claim 7, wherein the second switching means is an NMOS transistor.

Images