KR100532948B1 - method for manufacturing ball grid array type package - Google Patents
method for manufacturing ball grid array type package Download PDFInfo
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- KR100532948B1 KR100532948B1 KR10-2002-0085941A KR20020085941A KR100532948B1 KR 100532948 B1 KR100532948 B1 KR 100532948B1 KR 20020085941 A KR20020085941 A KR 20020085941A KR 100532948 B1 KR100532948 B1 KR 100532948B1
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- South Korea
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- package
- semiconductor chip
- manufacturing
- metal pattern
- molding
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- 238000004519 manufacturing process Methods 0.000 title claims abstract description 26
- 238000000034 method Methods 0.000 title claims abstract description 20
- 229910052751 metal Inorganic materials 0.000 claims abstract description 39
- 239000002184 metal Substances 0.000 claims abstract description 39
- 239000004065 semiconductor Substances 0.000 claims abstract description 29
- 238000000465 moulding Methods 0.000 claims abstract description 18
- 230000004907 flux Effects 0.000 claims abstract description 10
- 239000000758 substrate Substances 0.000 claims description 6
- 229910000679 solder Inorganic materials 0.000 claims description 5
- 239000003822 epoxy resin Substances 0.000 claims description 3
- 229920000647 polyepoxide Polymers 0.000 claims description 3
- 229920002050 silicone resin Polymers 0.000 claims description 3
- 239000010408 film Substances 0.000 description 8
- 239000010936 titanium Substances 0.000 description 4
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 2
- 238000004544 sputter deposition Methods 0.000 description 2
- 229910052719 titanium Inorganic materials 0.000 description 2
- LEONUFNNVUYDNQ-UHFFFAOYSA-N vanadium atom Chemical compound [V] LEONUFNNVUYDNQ-UHFFFAOYSA-N 0.000 description 2
- 238000007796 conventional method Methods 0.000 description 1
- 230000017525 heat dissipation Effects 0.000 description 1
- 238000003475 lamination Methods 0.000 description 1
- 238000002161 passivation Methods 0.000 description 1
- 239000010409 thin film Substances 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
- H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
- H01L23/3128—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation the substrate having spherical bumps for external connection
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
- H01L21/565—Moulds
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
- H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
- H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
- H05K3/341—Surface mounted components
- H05K3/3431—Leadless components
- H05K3/3436—Leadless components having an array of bottom contacts, e.g. pad grid array or ball grid array components
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/023—Redistribution layers [RDL] for bonding areas
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Manufacturing & Machinery (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Power Engineering (AREA)
- Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
Abstract
본 발명은 몰딩체의 두께를 줄일 수 있는 비지에이 타입 패키지(Ball Grid Array type package) 제조 방법에 관해 개시한다.The present invention discloses a method for manufacturing a ball grid array type package capable of reducing the thickness of a molding.
개시된 본 발명의 비지에이 타입 패키지의 제조 방법은 반도체 칩 영역의 센터 부분에 다수개 형성된 칩패드와, 칩패드와 연결되며 스크라이브라인 영역 밖으로 일부 돌출된 형상을 가진 금속 패턴을 가진 웨이퍼를 제공하는 단계와, 웨이퍼를 덮도록 몰딩체를 형성하는 단계와, 결과물을 쏘잉하여 각각의 반도체 칩으로 분리하는 단계와, 분리된 반도체 칩의 금속 패턴에 플럭스를 도팅하는 단계와, 도팅된 플럭스에 도전성 볼을 부착하는 단계를 포함한다.The disclosed method for manufacturing a BG package of the present invention includes providing a wafer having a plurality of chip pads formed in a center portion of a semiconductor chip region, and a metal pattern connected to the chip pads and having a shape partially protruding out of the scribe line region. Forming a molding to cover the wafer, sawing the resultant into separate semiconductor chips, doping flux into the metal pattern of the separated semiconductor chip, and conducting conductive balls to the doped flux. Attaching.
Description
본 발명은 패키지(package) 제조방법에 관한 것으로, 보다 상세하게는 몰딩체의 두께를 줄일 수 있는 비지에이 타입 패키지(Ball Grid Array type package) 제조 방법에 관한 것이다.The present invention relates to a method of manufacturing a package, and more particularly, to a method of manufacturing a ball grid array type package capable of reducing the thickness of a molding.
일반적으로, 볼 그리드 어레이 패키지는 기판의 이면에 구형의 솔더 볼(solder ball) 등의 도전성 볼을 소정의 상태로 배열하여 아우터 리드(outer lead) 대신으로 사용하게 되며, 패키지 몸체 면적을 QFP(Quad Flat Package) 타입보다 작게 할 수 있고, QFP와는 달리 리드의 변형이 없는 장점이 있다.In general, a ball grid array package arranges conductive balls such as spherical solder balls on a rear surface of a substrate in a predetermined state to use an outer lead, and uses a package body area of QFP (Quad). It can be smaller than the Flat Package type, and unlike QFP, there is no lead deformation.
도 1은 종래의 비지에이(Ball Grid Array )타입의 패키지의 일실시예를 나타내는 단면도이다.1 is a cross-sectional view showing an embodiment of a conventional BG package.
종래 기술에 따른 비지에이 타입의 패키지는, 도 1에 도시된 바와 같이, 상면 가장자리에 다수의 칩패드(102)가 형성된 반도체 칩(100)과, 반도체 칩(100) 상에 형성되며 칩패드(102)를 노출시키는 절연막(106)과, 칩패드(102)와 연결되는 제 1금속배선(108)과, 절연막(106) 상에 형성되며, 제 1금속배선(108)의 일부위와 연결되는 제 2금속배선(112)과, 외부환경으로부터 상기 결과물을 보호하기 위한 몰딩체(110)와, 제 2금속배선(112)에 안착되는 도전성 볼(120)로 구성되어 있다.As shown in FIG. 1, the BIJ type package according to the related art includes a semiconductor chip 100 having a plurality of chip pads 102 formed at an edge of an upper surface thereof, and a chip pad formed on the semiconductor chip 100. An insulating film 106 exposing 102, a first metal wire 108 connected to the chip pad 102, and an insulating film 106 formed on the insulating film 106 and connected to a portion of the first metal wire 108. It consists of a two-metal wiring 112, a molding body 110 for protecting the resultant from the external environment, and a conductive ball 120 seated on the second metal wiring 112.
상기 구성을 가진 종래의 비이에이 타입 패키지의 제조방법은, 도 1에 도시된 바와 같이, 먼저 웨이퍼 상태의 반도체 칩(100) 상에 절연막(106)을 화학기상증착한 다음, 상기 절연막을 식각하여 칩패드(102)를 노출시킨다.In the conventional method for manufacturing a BEI package having the above structure, as shown in FIG. The chip pad 102 is exposed.
상기 반도체 칩(100)의 칩패드(102)들 사이에는 보호막(104)으로 덮여져 있다.The passivation layer 104 is covered between the chip pads 102 of the semiconductor chip 100.
이 후, 절연막(106) 상에 스퍼터링법에 의해 티타늄(Ti) 또는 바나듐(V) 등의 제 1금속막을 증착한 다음, 상기 제 1금속막을 식각하여 칩패드(102)를 노출시키는 제 1금속배선(108)을 형성한다. Thereafter, a first metal film such as titanium (Ti) or vanadium (V) is deposited on the insulating film 106 by sputtering, and then the first metal is etched to expose the chip pad 102. The wiring 108 is formed.
그 다음, 상기 결과물을 덮되, 제 1금속배선(108)의 일부분을 노출시키는 몰딩체(110)를 형성한다.Next, the molding member 110 is formed to cover the resultant and expose a portion of the first metal wiring 108.
이어서, 제 1절연막(106) 스퍼터링 공정에 의해 티타늄(Ti) 또는 바나듐(V) 등의 제 2금속막을 증착한 다음, 상기 제 2금속막을 식각하여 상기 제 1금속배선(108)의 일부분을 노출시키는 제 2금속 배선(112)을 형성한다. Subsequently, a second metal film such as titanium (Ti) or vanadium (V) is deposited by a first sputtering process of the first insulating film 106, and then the second metal film is etched to expose a portion of the first metal wiring 108. The second metal wiring 112 is formed.
이때, 상기 제 2금속배선(112)은 상기 제 1금속 배선(108)을 통해 칩패드(102)와 전기적으로 연결되며, 이 후의 공정을 통해 도전성 볼이 안착되는 볼랜드가 된다. In this case, the second metal wire 112 is electrically connected to the chip pad 102 through the first metal wire 108, and becomes a ball land in which conductive balls are seated through a subsequent process.
이어서, 제 2금속배선(112)에 도전성 볼(120)을 안착시킨 다음, 상기 도전성 볼(120)을 피씨비(Printed Circuit Board)기판(140)에 실장하여 비지에이 패키지 제조를 완료한다.Subsequently, the conductive ball 120 is seated on the second metal wire 112, and then the conductive ball 120 is mounted on the PCB circuit board 140 to complete the manufacture of the BIG package.
그러나, 종래기술에서는 패키지 몸체 하부에 도전성 볼을 실장함으로써, 전체 패키지 두께가 두꺼워지는 문제점이 있었다.However, in the prior art, there is a problem in that the overall package thickness becomes thick by mounting conductive balls under the package body.
이에 본 발명은 상기 종래의 문제점을 해결하기 위해 안출된 것으로, 패키지의 두께를 줄일 수 있는 비지에이 타입 패키지 제조방법을 제공함에 그 목적이 있다.Accordingly, an object of the present invention is to provide a method for manufacturing a BG package that can reduce the thickness of the package.
상기 목적을 달성하기 위한 본 발명에 따른 비지에이 타입 패키지 제조 방법은 반도체 칩영역 및 스크라이브 라인영역이 정의되며, 반도체 칩영역의 센터부분에 다수 개의 칩패드가 구비된 웨이퍼를 제공하는 단계와, 일단은 반도체 칩영역의 칩패드와 연결되고 타단은 스크라이브라인 영역 밖으로 돌출된 형상을 가진 금속 패턴을 형성하는 단계와, 금속 패턴을 포함한 웨이퍼 전면에 몰딩체를 형성하는 단계와, 결과물을 쏘잉하여 각각의 반도체 칩으로 분리하는 단계와, 반도체 칩 측면으로부터 돌출된 금속 패턴 및 그 주변에 플럭스를 도팅하는 단계와, 도팅된 플럭스에 도전성 볼을 부착시켜 패키지를 제조하는 단계를 포함한 것을 특징으로 한다.According to the present invention, there is provided a method of manufacturing a BG package in which a semiconductor chip region and a scribe line region are defined, and providing a wafer having a plurality of chip pads in a center portion of the semiconductor chip region. Forming a metal pattern having a shape that is connected to the chip pad of the semiconductor chip region and the other end protruding out of the scribe region, forming a molding on the front surface of the wafer including the metal pattern, and sawing the resultant Separating the semiconductor chip, doping the flux around the metal pattern protruding from the semiconductor chip side, and manufacturing a package by attaching conductive balls to the doped flux.
상기 금속 패턴은 1∼100㎛ 두께로 형성한다.The metal pattern is formed to a thickness of 1 to 100㎛.
상기 몰딩체는 에폭시계 수지 및 실리콘계 수지 중 어느 하나를 이용하며, 25∼400㎛두께로 형성한다.The molding is any one of an epoxy resin and a silicone resin, and is formed to have a thickness of 25 to 400 μm.
상기 도전성 볼은 상기 웨이퍼 및 몰딩체를 합한 크기보다 크지 않게 형성한다.The conductive balls are formed no larger than the combined size of the wafer and the molding.
상기 패키지를 제조한 다음, 상기 도전성 볼의 상단 및 하단을 그라인딩하는 단계를 추가한다.After manufacturing the package, the step of grinding the top and bottom of the conductive ball is added.
상기 금속 패턴은 상기 반도체 칩의 일측면 및 네측면 중 어느 하나에 돌출되도록 형성한다.The metal pattern is formed to protrude on any one side and four sides of the semiconductor chip.
상기 도전성 볼은 솔더 볼 및 금속 바 중 어느 하나를 이용한다.The conductive ball uses any one of a solder ball and a metal bar.
상기 패키지를 제조한 다음, PCB기판 위에 상기 패키지를 적어도 2개 이상 수직 적층시킨다.After the package is manufactured, at least two or more packages are vertically stacked on a PCB substrate.
이하, 본 발명의 바람직한 실시예를 첨부된 도면을 참조하여 상세히 설명하면 다음과 같다. Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.
도 2는 본 발명의 제 1실시예에 따른 웨이퍼의 평면도이다.2 is a plan view of a wafer according to a first embodiment of the present invention.
또한, 도 3a 내지 도 3d는 본 발명의 제 1실시예에 따른 비지에이 타입 패키지 제조 방법을 도시한 공정 단면도이다.3A to 3D are cross-sectional views illustrating a method of manufacturing a BG package according to a first embodiment of the present invention.
도 4는 본 발명의 제 1실시예에 따른 웨이퍼 레벨 패키지의 저면도이다.4 is a bottom view of a wafer level package according to a first embodiment of the present invention.
본 발명의 제 1실시예에 따른 비지에이 타입 패키지의 제조 방법은, 도 2에 도시된 바와 같이, 먼저 반도체 칩영역(200) 및 그 주변에 스크라이브라인 (scribe line)영역(210)이 정의되며, 상기 반도체 칩 영역(200)의 센터 부분에 칩패드(202)가 다수개 배열된 웨이퍼(W)를 제공한다. 이어, 상기 웨이퍼(W)에 일단은 반도체 칩영역의 칩패드와 연결되고 타단은 스크라이브라인 영역 밖으로 돌출된 형상을 가진 금속 패턴을 형성한다. 이때, 상기 금속 패턴(204)은 1∼100㎛ 두께로 형성된다.In the manufacturing method of the BG package according to the first embodiment of the present invention, as shown in FIG. 2, first, a scribe line region 210 is defined in the semiconductor chip region 200 and its periphery. The wafer W is provided with a plurality of chip pads 202 arranged at a center portion of the semiconductor chip region 200. Subsequently, one end of the wafer W is connected to the chip pad of the semiconductor chip region, and the other end forms a metal pattern protruding out of the scribe line region. At this time, the metal pattern 204 is formed to a thickness of 1 ~ 100㎛.
그런 다음, 상기 구조의 웨이퍼(W) 전면에, 도 3a에 도시된 바와 같이, 금속 패턴(204)을 덮도록 몰딩체(220)를 형성한다. 이때, 상기 몰딩체(220)는 에폭시(epoxy)계 수지 또는 실리콘(silicon)계 수지를 이용하며, 25∼400㎛두께로 형성한다. 또한, 상기 몰딩체(220)는 웨이퍼(W) 상의 금속 패턴(204)를 덮고 나머지 부분을 노출시키도록 형성할 수도 있다.Then, the molding body 220 is formed on the entire surface of the wafer W having the above structure to cover the metal pattern 204, as shown in FIG. 3A. In this case, the molding member 220 is formed of an epoxy resin or a silicone resin, and has a thickness of 25 to 400 μm. In addition, the molding member 220 may be formed to cover the metal pattern 204 on the wafer W and expose the remaining portion.
이 후, 도 3b에 도시된 바와 같이, 상기 결과물을 칩단위로 쏘잉(sawing)하여 개개의 반도체 칩(201)으로 분리시킨다. 이때, 반도체 칩(210)은 일측면 또는 네측면으로 부터 금속 패턴(204)이 돌출된 형상을 가진다.Thereafter, as shown in FIG. 3B, the resultant is sawed in chip units to be separated into individual semiconductor chips 201. At this time, the semiconductor chip 210 has a shape in which the metal pattern 204 protrudes from one side or four sides.
이어, 상기 반도체 칩(201)으로부터 돌출된 금속 패턴(204) 및 그 주변에 전기적 특성이 우수한 금속이 함유된 플럭스(plux)(205)를 도팅(dotting)한다. Next, the metal pattern 204 protruding from the semiconductor chip 201 and a flux 205 containing a metal having excellent electrical characteristics are doped.
그런 다음, 도 3c에 도시된 바와 같이, 상기 플럭스(205) 부분에 도전성 볼(230)을 본딩시켜 패키지(P) 제조를 완료한다. 이때, 상기 도전성 볼(230)은 열압착 방식 또는 리플로우(reflow) 방식에 의해 상기 플럭스(205) 부분에 물리적 결합한다. 또한, 상기 도전성 볼(230) 대신 금속바(metal bar)를 이용할 수도 있다. Then, as shown in Figure 3c, the conductive ball 230 is bonded to the flux 205 portion to complete the package (P) manufacturing. At this time, the conductive ball 230 is physically coupled to the flux 205 portion by a thermocompression method or a reflow method. In addition, a metal bar may be used instead of the conductive ball 230.
본 발명에서는 반도체 칩(201)의 측면 부분에 상기 도전성 볼(230)을 본딩함으로써, 결과적으로 도전성 볼의 크기에 따라 패키지의 두께가 결정된다. 따라서, 상기 도전성 볼(230)은 반도체 칩(201) 및 몰딩체(220)를 합한 크기보다 크지 않게 형성하며, 패키지의 두께를 좀 더 얇게 제조하기 위해서는 도전성 볼(230)의 상단 및 하단을 그라인딩(grinding)하여 접촉면을 플랫(flat)하게 할 수도 있다.In the present invention, by bonding the conductive ball 230 to the side portion of the semiconductor chip 201, the thickness of the package is determined according to the size of the conductive ball. Therefore, the conductive balls 230 are formed not to be larger than the combined size of the semiconductor chip 201 and the molding body 220, and in order to manufacture a thinner package thickness, grinding the upper and lower ends of the conductive balls 230. It can also be grinded to flatten the contact surface.
이 후, 도 3d 및 도 4에 도시된 바와 같이, PCB기판(240) 위에 상기 패키지(P)를 실장시킨다. 이때, 상기 PCB기판(240)과 패키지(P) 사이에는 솔더 페이스트(210)를 개재시켜 이들 간의 접착력을 향상시킨다.Thereafter, as shown in FIGS. 3D and 4, the package P is mounted on the PCB substrate 240. At this time, the solder paste 210 is interposed between the PCB board 240 and the package P to improve adhesion between them.
도 5는 본 발명의 제 2실시예에 따른 비지에이 타입 패키지 제조 방법의 제조 방법을 설명하기 위한 단면도이다.5 is a cross-sectional view for describing a manufacturing method of a BG package manufacturing method according to a second exemplary embodiment of the present invention.
본 발명의 제 2실시예에 따른 비지에이 타입 패키지 제조 방법은, 도 5에 도시된 바와 같이, PCB기판 위에 본 발명의 제 1실시예에 따른 방법에 의해 제조된 제 1및 제 2패키지(P1)(P2)를 수직으로 2개 적층시킨다. 이때, 상기 PCB기판과 제 1패키지(P1) 사이와 제 1패키지(P1) 및 제 2패키지(P2) 사이에는 각각 솔더 페이스트(210)(211)을 개재시켜 이들 간의 접착력을 향상시킨다. 또한, 상기 적층 공정에서, 제 1패키지(P1)의 그라인딩된 도전성 볼 상단면과 제 2패키지(P2)의 그라인딩된 하단면을 서로 접촉시킨다. As shown in FIG. 5, the BAI type package manufacturing method according to the second embodiment of the present invention includes the first and second packages P1 manufactured by the method according to the first embodiment of the present invention on a PCB substrate. ) P2 is stacked vertically. At this time, the solder paste 210 and 211 are interposed between the PCB substrate and the first package P1 and between the first package P1 and the second package P2, respectively, to improve adhesion between them. In addition, in the lamination process, the ground top surface of the ground conductive ball of the first package P1 and the ground bottom surface of the second package P2 are contacted with each other.
도 5에서는 패키지를 2개 적층한 것을 보였으나, 2개 이상 적층하여도 무관하다.In FIG. 5, two packages were stacked, but two or more packages may be stacked.
이상에서 설명한 바와 같이, 본 발명에서는 반도체 칩의 일측면 또는 네측면으로 부터 상기 반도체 칩의 칩패드와 연결된 금속 패턴을 돌출시킨 다음, 상기 금속 패턴에 도전성 볼을 형성함으로써, 초박막 두께의 패키지 제조가 가능하다.As described above, in the present invention, by forming a conductive ball on the metal pattern protrudes from the one or four sides of the semiconductor chip connected to the chip pad of the semiconductor chip, it is possible to manufacture a package having an ultra-thin film thickness It is possible.
또한, 본 발명은 패키지 구조 및 공정을 단순화함으로써, 제품의 품질 및 생산성이 향상된다.In addition, the present invention simplifies the package structure and process, thereby improving product quality and productivity.
한편, 본 발명에서는 웨이퍼 상의 금속 패턴를 덮고 나머지 부분을 노출시키도록 몰딩체를 형성함으로써, 열방출 특성이 탁월한 이점이 있다.On the other hand, in the present invention by forming a molding to cover the metal pattern on the wafer and to expose the remaining portion, there is an advantage of excellent heat dissipation characteristics.
기타, 본 발명은 그 요지를 일탈하지 않는 범위에서 다양하게 변경하여 실시할 수 있다. In addition, this invention can be implemented in various changes within the range which does not deviate from the summary.
도 1은 종래 기술에 따른 비지에이 타입 패키지 제조 방법을 설명하기 위한 공정 단면도.1 is a cross-sectional view illustrating a method for manufacturing a BG package according to the prior art.
도 2는 본 발명의 제 1실시예에 따른 웨이퍼의 평면도.2 is a plan view of a wafer according to a first embodiment of the present invention;
또한, 도 3a 내지 도 3d는 본 발명의 제 1실시예에 따른 비지에이 타입 패키지 제조 방법을 도시한 공정 단면도.3A to 3D are cross-sectional views illustrating a method of manufacturing a BG package according to a first embodiment of the present invention.
도 4는 본 발명의 제 1실시예에 따른 웨이퍼 레벨 패키지의 저면도.4 is a bottom view of a wafer level package according to a first embodiment of the present invention.
도 5는 본 발명의 제 2실시예에 따른 비지에이 타입 패키지 제조 방법의 제조 방법을 설명하기 위한 단면도.Figure 5 is a cross-sectional view for explaining a manufacturing method of a manufacturing method of a busy type package according to a second embodiment of the present invention.
도면의 주요부분에 대한 부호의 설명Explanation of symbols for main parts of the drawings
W. 웨이퍼 200. 반도체 칩영역 W. Wafer 200. Semiconductor chip area
202. 칩패드 204. 금속 패턴 202. Chip Pad 204. Metal Pattern
210. 스크라이브라인 영역 205. 플럭스 210. Scribine area 205. Flux
220. 몰딩체 230. 도전성 볼220. Molding body 230. Conductive ball
240. PCB기판 P1,P2. 패키지 240. PCB boards P1, P2. package
Claims (9)
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| KR20010088322 | 2001-12-29 | ||
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| KR (1) | KR100532948B1 (en) |
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