KR100531466B1 - Method for manufacturing multi-interdielectric layer in semiconductor device - Google Patents
Method for manufacturing multi-interdielectric layer in semiconductor device Download PDFInfo
- Publication number
- KR100531466B1 KR100531466B1 KR10-1999-0058694A KR19990058694A KR100531466B1 KR 100531466 B1 KR100531466 B1 KR 100531466B1 KR 19990058694 A KR19990058694 A KR 19990058694A KR 100531466 B1 KR100531466 B1 KR 100531466B1
- Authority
- KR
- South Korea
- Prior art keywords
- insulating film
- porous
- forming
- polymer
- film
- Prior art date
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76835—Combinations of two or more different dielectric layers having a low dielectric constant
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Formation Of Insulating Films (AREA)
Abstract
본 발명은 절연막간 접착계면의 기계적강도를 증가시킨 층간절연막의 형성 방법에 관한 것으로, 이를 위한 본 발명은 반도체 기판 상부에 무기질절연막을 형성하는 단계, 상기 무기질절연막상에 다수개의 기공을 갖는 다공질절연막을 형성하는 단계, 상기 다공질절연막의 기공에 흡입되도록 저점도의 제1 고분자절연막을 도포하여 다공질-고분자 복합막을 형성하는 단계, 상기 다공질-고분자 복합막상에 제2 고분자절연막을 도포하는 단계를 포함하여 이루어진다.The present invention relates to a method of forming an interlayer insulating film having an increased mechanical strength of the interfacial adhesion layer. The present invention provides a porous insulating film having a plurality of pores on the inorganic insulating film. Forming a porous-polymer composite film by applying a low viscosity first polymer insulating film so as to be sucked into pores of the porous insulating film, and applying a second polymer insulating film on the porous-polymer composite film. Is done.
Description
본 발명은 반도체 소자의 제조 방법에 관한 것으로, 특히 저유전율 고분자절연막과 실리콘을 포함한 무기질절연막간의 접착성을 향상시키도록 한 다층 층간절연막의 형성 방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method for forming a multilayer interlayer insulating film to improve adhesion between a low dielectric constant polymer insulating film and an inorganic insulating film containing silicon.
일반적으로 반도체 소자의 집적도가 증가하고 금속배선간의 간격이 좁아짐에 따라 금속배선간의 캐패시턴스값이 높아지고, 이러한 캐패시턴스의 증가로 인해 신호지연(Signal delay)과 누화(Crosstalk)가 발생한다.In general, as the degree of integration of semiconductor devices increases and the spacing between metal wires becomes narrower, capacitance values between metal wires increase, and signal delay and crosstalk occur due to the increase in capacitance.
이처럼 금속배선 특성이 열화되는 현상을 최소화하기 위해 저유전율 절연막의 사용이 요구되고 있으며, 이러한 저유전율막으로 고분자박막(Spin-On Polymer)이 사용되고 있다.As such, the use of a low dielectric constant insulating film is required in order to minimize the phenomenon of deterioration of metallization characteristics, and a polymer film (Spin-On Polymer) is used as the low dielectric constant film.
한편 고분자막(Polymer)은 주로 탄소(Carbon; C)로 이루어지고 유기질막 표면의 화학구조가 실리콘(Si) 계통의 절연막들과 상이하여 강한 화학결합을 형성하기 힘드므로 계면 접합력이 약하다. 이로 인해 반복되는 후속열공정이나 강한 회전응력을 받는 화학적기계적연마(Chemical Mechanical Polishing; CMP) 공정후 절연막의 리프팅(Lifting)이나 딜래미네이션(Delamination)이 발생된다. On the other hand, the polymer film (Polymer) is mainly composed of carbon (Carbon; C) and the surface structure of the organic film is different from the silicon (Si) -based insulating film is difficult to form a strong chemical bond, so the interface bonding strength is weak. This results in lifting or delamination of the insulating film after repeated subsequent thermal processes or chemical mechanical polishing (CMP) processes subjected to strong rotational stresses.
상기의 문제를 해결하기 위해 강한 접착력을 갖는 절연막이 필요한데, 현재 주로 이용되는 고분자로는 실리콘이 함유된 무기질접착막을 사용하고 있다.In order to solve the above problem, an insulating film having a strong adhesive force is required, and an inorganic adhesive film containing silicon is used as a polymer which is currently used.
본 발명은 상기의 문제점을 해결하기 위해 안출한 것으로서, 무기질절연막의 탄소와 다공질절연막의 수산화탄소간 화학결합을 통해 기계적강도가 뛰어난 접착절연막을 형성하는데 적합한 다층 층간절연막의 형성 방법을 제공하는데 그 목적이 있다.The present invention has been made to solve the above problems, to provide a method for forming a multilayer interlayer insulating film suitable for forming an adhesive insulating film excellent in mechanical strength through the chemical bonding between the carbon of the inorganic insulating film and the carbon hydroxide of the porous insulating film. There is this.
상기의 목적을 달성하기 위한 본 발명의 층간절연막 형성 방법은 반도체 기판 상부에 무기질절연막을 형성하는 단계, 상기 무기질절연막상에 다수개의 기공을 갖는 다공질절연막을 형성하는 단계, 상기 다공질절연막의 기공에 흡입되도록 저점도의 제1 고분자절연막을 도포하여 다공질-고분자 복합막을 형성하는 단계, 상기 다공질-고분자 복합막상에 제2 고분자절연막을 도포하는 단계를 포함하여 이루어짐을 특징으로 한다.The interlayer insulating film forming method of the present invention for achieving the above object comprises the steps of forming an inorganic insulating film on the semiconductor substrate, forming a porous insulating film having a plurality of pores on the inorganic insulating film, suction in the pores of the porous insulating film Forming a porous-polymer composite film by applying a low-viscosity first polymer insulating film as much as possible, and applying a second polymer insulating film on the porous-polymer composite film.
이하, 본 발명이 속하는 기술분야에서 통상의 지식을 가진 자가 본 발명의 기술적 사상을 용이하게 실시할 수 있을 정도로 상세히 설명하기 위하여, 본 발명의 가장 바람직한 실시예를 첨부 도면을 참조하여 설명하기로 한다.Hereinafter, the most preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art may easily implement the technical idea of the present invention. .
도 1 내지 도 3 은 본 발명의 실시예에 따른 다층 층간절연막의 형성 방법을 나타낸 도면으로서, 다공질막-고분자막의 복합막을 접착향상막으로 이용한다.1 to 3 illustrate a method of forming a multilayer interlayer insulating film according to an embodiment of the present invention, wherein a composite film of a porous film-polymer film is used as an adhesion improving film.
도 1 에 도시된 바와 같이, 반도체 기판(11) 상부에 플라즈마인핸스드 화학적기상증착(Plasma Ehanced Chemical Vapor Deposition; PECVD)법으로 SiO, SiON, SiN 과 같은 실리콘(Si) 함유 무기질절연막(12)을 형성한다.As shown in FIG. 1, a silicon (Si) -containing inorganic insulating film 12 such as SiO, SiON, SiN, or the like is deposited on a semiconductor substrate 11 by plasma enhanced chemical vapor deposition (PECVD). Form.
도 2 에 도시된 바와 같이, 메틸실레인(Methl Silane) 계열의 수산화탄소 (CH-)가 함유된 Si(CH3)xHy 를 선택적산화시키므로써 상기 무기질절연막(12) 상에 수십 Å 두께의 다공질절연막(13) 즉, SiOCH막을 증착한다. 여기서 상기 다공질절연막(13)의 기공(14) 표면은 다량의 C-H 나 CH3등이 노출되어 후공정시 형성되는 고분자절연막(SOP) 표면의 탄소와 화학결합을 이루게 된다.As shown in FIG. 2, the Si (CH 3 ) x H y containing the methyl silane (CH-)-based carbon dioxide (CH-) is selectively oxidized to several tens of micrometers on the inorganic insulating film 12. A porous insulating film 13, i.e., a SiOCH film, is deposited. Here, the surface of the pores 14 of the porous insulating layer 13 is exposed to a large amount of CH or CH 3 to form a chemical bond with the carbon of the surface of the polymer insulating layer (SOP) formed during the post-process.
도 3 에 도시된 바와 같이, 상기 다공질절연막(13)의 기공(14) 속으로 삼투압에 의해 충분히 흡수될 정도의 저점도 제1 고분자절연막(15)을 상기 다공질절연막(13) 상에 형성한 후 경화시킨다. 이 때 상기 다공질절연막(13)의 기공 사이에 폴리머가 흡입되어 얇은 고분자-다공질 복합막(16)이 형성된다. 이처럼 상기 무기질절연막(12)과 후에 형성되는 제2 고분자절연막(17) 사이에 고분자-다공질 복합막 (16)을 형성하므로써 두 절연막간의 접착계면의 기계적 강도를 증가시킬 수 있다.As shown in FIG. 3, after forming the low-viscosity first polymer insulating film 15 on the porous insulating film 13 that is sufficiently absorbed by the osmotic pressure into the pores 14 of the porous insulating film 13. Harden. At this time, the polymer is sucked between the pores of the porous insulating film 13 to form a thin polymer-porous composite film 16. As such, by forming the polymer-porous composite film 16 between the inorganic insulating film 12 and the second polymer insulating film 17 formed later, the mechanical strength of the adhesion interface between the two insulating films can be increased.
이어 저점도 제2 고분자절연막(17)을 도포한다.Next, a low viscosity second polymer insulating film 17 is applied.
본 발명의 기술 사상은 상기 바람직한 실시예에 따라 구체적으로 기술되었으나, 상기한 실시예는 그 설명을 위한 것이며 그 제한을 위한 것이 아님을 주의하여야 한다. 또한, 본 발명의 기술 분야의 통상의 전문가라면 본 발명의 기술 사상의 범위 내에서 다양한 실시예가 가능함을 이해할 수 있을 것이다Although the technical idea of the present invention has been described in detail according to the above preferred embodiment, it should be noted that the above-described embodiment is for the purpose of description and not of limitation. In addition, those skilled in the art will understand that various embodiments are possible within the scope of the technical idea of the present invention.
상술한 본 발명은 반도체 소자에서 다른 무기질절연막과 고분자절연막간의 접착성을 향상시키므로써 저유전율막을 사용하여 형성된 다층간 금속배선의 기계적 특성을 향상시킬 수 있는 효과가 있다. The present invention described above has the effect of improving the mechanical properties of the multi-layer metal wiring formed by using a low dielectric constant film by improving the adhesion between the other inorganic insulating film and the polymer insulating film in the semiconductor device.
도 1 내지 도 3 은 본 발명의 실시예에 따른 다층 층간절연막의 형성 방법을 나타낸 도면.1 to 3 illustrate a method of forming a multilayer interlayer insulating film according to an embodiment of the present invention.
*도면의 주요부분에 대한 부호의 설명** Description of the symbols for the main parts of the drawings *
11 : 반도체 기판 12 : 무기질절연막11 semiconductor substrate 12 inorganic insulating film
13 : 다공질절연막 14 : 기공13 porous insulating film 14 pores
15 : 제1고분자절연막 16 : 다공질-고분자복합막15: first polymer insulating film 16: porous-polymer composite film
17 : 제2 고분자절연막17: second polymer insulating film
Claims (5)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR10-1999-0058694A KR100531466B1 (en) | 1999-12-17 | 1999-12-17 | Method for manufacturing multi-interdielectric layer in semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR10-1999-0058694A KR100531466B1 (en) | 1999-12-17 | 1999-12-17 | Method for manufacturing multi-interdielectric layer in semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| KR20010056979A KR20010056979A (en) | 2001-07-04 |
| KR100531466B1 true KR100531466B1 (en) | 2005-11-28 |
Family
ID=19626675
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| KR10-1999-0058694A KR100531466B1 (en) | 1999-12-17 | 1999-12-17 | Method for manufacturing multi-interdielectric layer in semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| KR (1) | KR100531466B1 (en) |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH1092804A (en) * | 1996-09-19 | 1998-04-10 | Sony Corp | Manufacture of porous dielectric film |
| KR19990011488A (en) * | 1997-07-23 | 1999-02-18 | 손욱 | Light emitting diodes and manufacturing method |
| JPH11200090A (en) * | 1997-11-12 | 1999-07-27 | Canon Inc | Nanostructural body and its production |
| JP2000195855A (en) * | 1998-12-25 | 2000-07-14 | Sony Corp | Manufacture of semiconductor device |
| US6156374A (en) * | 1997-10-09 | 2000-12-05 | Micron Technology, Inc. | Method of forming insulating material between components of an integrated circuit |
-
1999
- 1999-12-17 KR KR10-1999-0058694A patent/KR100531466B1/en not_active IP Right Cessation
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH1092804A (en) * | 1996-09-19 | 1998-04-10 | Sony Corp | Manufacture of porous dielectric film |
| KR19990011488A (en) * | 1997-07-23 | 1999-02-18 | 손욱 | Light emitting diodes and manufacturing method |
| US6156374A (en) * | 1997-10-09 | 2000-12-05 | Micron Technology, Inc. | Method of forming insulating material between components of an integrated circuit |
| JPH11200090A (en) * | 1997-11-12 | 1999-07-27 | Canon Inc | Nanostructural body and its production |
| JP2000195855A (en) * | 1998-12-25 | 2000-07-14 | Sony Corp | Manufacture of semiconductor device |
Also Published As
| Publication number | Publication date |
|---|---|
| KR20010056979A (en) | 2001-07-04 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| KR100571896B1 (en) | Method for manufacturing a semiconductor device | |
| US5435888A (en) | Enhanced planarization technique for an integrated circuit | |
| JP2589950B2 (en) | Metal via formation method | |
| TW584916B (en) | Method of manufacturing semiconductor device having multilevel wiring | |
| US20080166870A1 (en) | Fabrication of Interconnect Structures | |
| JP2002164428A5 (en) | ||
| KR20020095120A (en) | Semiconductor device having multiple wiring layers and manufacturing method thereof | |
| US6784485B1 (en) | Diffusion barrier layer and semiconductor device containing same | |
| KR100531466B1 (en) | Method for manufacturing multi-interdielectric layer in semiconductor device | |
| JP3657576B2 (en) | Manufacturing method of semiconductor device | |
| KR19990054912A (en) | Method of forming interlayer insulating film of semiconductor device | |
| JPH06267943A (en) | Manufacture of semiconductor device | |
| KR20050021895A (en) | Method for manufacturing electronic device | |
| JP3986674B2 (en) | Semiconductor device, method for manufacturing the same, and method for forming interlayer insulating film | |
| KR20100044227A (en) | Interlayer insulation film and wiring structure, and their manufacturing method | |
| KR100945500B1 (en) | Method of manufacturing semiconductor device | |
| US5837611A (en) | Production method for an insulation layer functioning as an intermetal dielectric | |
| JP2001035843A (en) | Method for formation of interlayer dielectric | |
| KR100640569B1 (en) | Method for forming a Cu line using a ALD type Al2O3 layer | |
| KR20090011950A (en) | Method for manufacturing semiconductor device | |
| US6806182B2 (en) | Method for eliminating via resistance shift in organic ILD | |
| KR100588636B1 (en) | Method for manufacturing inter-metal dielectric layer of the semiconductor device | |
| JPH11274296A (en) | Multilayer wiring structure and method of forming the same | |
| KR20040082295A (en) | Semiconductor Device and Method of Manufacturing The Same | |
| JP3368445B2 (en) | Method for manufacturing semiconductor device |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| A201 | Request for examination | ||
| E701 | Decision to grant or registration of patent right | ||
| GRNT | Written decision to grant | ||
| FPAY | Annual fee payment |
Payment date: 20101025 Year of fee payment: 6 |
|
| LAPS | Lapse due to unpaid annual fee |