KR100530737B1 - Fabrication method of metalization by electroplating in multi-chip module substrate manufacturing process - Google Patents
Fabrication method of metalization by electroplating in multi-chip module substrate manufacturing process Download PDFInfo
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- KR100530737B1 KR100530737B1 KR10-2000-0003865A KR20000003865A KR100530737B1 KR 100530737 B1 KR100530737 B1 KR 100530737B1 KR 20000003865 A KR20000003865 A KR 20000003865A KR 100530737 B1 KR100530737 B1 KR 100530737B1
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- electroplating
- insulating film
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- 238000004519 manufacturing process Methods 0.000 title claims abstract description 38
- 239000000758 substrate Substances 0.000 title claims abstract description 32
- 238000000034 method Methods 0.000 title claims abstract description 29
- 238000009713 electroplating Methods 0.000 title claims abstract description 26
- 238000001465 metallisation Methods 0.000 title description 2
- 239000002184 metal Substances 0.000 claims abstract description 54
- 229910052751 metal Inorganic materials 0.000 claims abstract description 54
- 229920002120 photoresistant polymer Polymers 0.000 claims abstract description 25
- 239000004020 conductor Substances 0.000 claims abstract description 4
- 239000000463 material Substances 0.000 claims abstract description 4
- 238000000059 patterning Methods 0.000 claims abstract description 3
- 239000010949 copper Substances 0.000 claims description 8
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 5
- 229910052802 copper Inorganic materials 0.000 claims description 5
- 229920000642 polymer Polymers 0.000 claims description 5
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 claims description 3
- 238000004544 sputter deposition Methods 0.000 claims description 3
- 239000010408 film Substances 0.000 description 43
- 238000007747 plating Methods 0.000 description 9
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- 239000011248 coating agent Substances 0.000 description 2
- 238000000576 coating method Methods 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- 238000001039 wet etching Methods 0.000 description 2
- 239000000853 adhesive Substances 0.000 description 1
- 230000001070 adhesive effect Effects 0.000 description 1
- 239000003054 catalyst Substances 0.000 description 1
- 238000006555 catalytic reaction Methods 0.000 description 1
- 239000000428 dust Substances 0.000 description 1
- 238000007772 electroless plating Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- -1 for example Substances 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 239000007788 liquid Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 230000000149 penetrating effect Effects 0.000 description 1
- 230000035515 penetration Effects 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- 239000010409 thin film Substances 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
- H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
- H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
- H01L21/0217—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material being a silicon nitride not containing oxygen, e.g. SixNy or SixByNz
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
- H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
- H01L21/02263—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
- H01L21/02271—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition
- H01L21/02274—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition in the presence of a plasma [PECVD]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
- H01L21/288—Deposition of conductive or insulating materials for electrodes conducting electric current from a liquid, e.g. electrolytic deposition
- H01L21/2885—Deposition of conductive or insulating materials for electrodes conducting electric current from a liquid, e.g. electrolytic deposition using an external electrical current, i.e. electro-deposition
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
- H01L21/76871—Layers specifically deposited to enhance or enable the nucleation of further layers, i.e. seed layers
- H01L21/76873—Layers specifically deposited to enhance or enable the nucleation of further layers, i.e. seed layers for electroplating
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Microelectronics & Electronic Packaging (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Power Engineering (AREA)
- Plasma & Fusion (AREA)
- Chemical & Material Sciences (AREA)
- Chemical Kinetics & Catalysis (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Electroplating Methods And Accessories (AREA)
- Manufacturing Of Printed Wiring (AREA)
Abstract
본 발명은, 멀티 칩 모듈 기판의 금속배선 형성을 위한 전기 도금공정에서 금속배선 제조 방법으로서, 상기 기판의 표면에 제 1 절연막을 형성하는 단계와, 상기 제 1 절연막의 표면에 시드금속을 형성하는 단계와, 상기 시드금속의 표면에 제 2 절연막을 형성하는 단계와, 상기 제 2 절연막의 표면에 감광막을 형성하는 단계와, 상기 감광막을 도금할 부분에 대응하여, 패터닝하고, 상기 패터닝된 표면을 노광 및 현상하는 단계와, 상기 도금할 패턴에 대응하여, 상기 감광막의 불필요한 부분을 제거하는 단계와, 상기 감광막 영역을 제외한 영역의 상기 제 2 절연막을 제거하는 단계와, 상기 시드금속의 드러난 표면에 전도체 물질로 전기 도금하는 단계와, 적층된 상기 감광막, 상기 제 2 절연막, 및 상기 시드금속을 제거하는 단계로 이루어진다.The present invention provides a method for manufacturing metal wiring in an electroplating process for forming metal wiring of a multi-chip module substrate, comprising: forming a first insulating film on a surface of the substrate, and forming a seed metal on the surface of the first insulating film Forming a second insulating film on the surface of the seed metal, forming a photosensitive film on the surface of the second insulating film, and patterning the patterned surface corresponding to a portion to be plated with the photosensitive film. Exposing and developing, removing an unnecessary portion of the photoresist film corresponding to the pattern to be plated, removing the second insulating film in an area excluding the photoresist area, and exposing the exposed surface of the seed metal. Electroplating with a conductor material, and removing the stacked photoresist, the second insulating film, and the seed metal.
Description
본 발명은 멀티 칩 모듈 기판 제작 시 전기 도금에 의한 금속배선 제조 방법에 관한 것이며, 특히, 절연막을 사용하여 시드금속(Seed Metal)과 감광막의 접착성을 향상시킬 수 있는 금속배선 제조 방법에 관한 것이다.The present invention relates to a method for manufacturing metal wiring by electroplating when manufacturing a multi-chip module substrate, and more particularly, to a method for manufacturing metal wiring capable of improving adhesion between seed metal and photoresist using an insulating film. .
종래의 기술에 따른 반도체의 금속배선방법의 일 실시예를 보면 다음과 같다.먼저, 실리콘 기판 위에 산화막과 포토레지스트(Photo Resist : PR)를 차례로 데포지션(deposition)한 후, 콘택홀(contact hole)을 형성하고, 표면 활성화를 위해 배선부 표면을 처리한다.무전해 도금액에 침지하여 촉매용 메탈필름을 형성시키는 제 1 차 도금공정을 수행한다.포토레지스터를 제거하고 무전해도금액에 다시 침지하여 자기 촉매 반응에 의해 소정 두께의 필름으로 성장시키는 제 2 차 도금공정을 수행한다.An embodiment of the metallization method of a semiconductor according to the related art is as follows. First, an oxide film and a photoresist (PR) are sequentially deposited on a silicon substrate, and then contact holes are formed. The first plating process is performed by immersing in the electroless plating solution to form a catalyst metal film. The photoresist is removed and immersed again in the electroless solution. A secondary plating process for growing a film of a predetermined thickness by self catalysis is performed.
이와 같은 종래의 기술에 따른 멀티 칩 모듈 기판의 금속배선 형성을 위한 도금공정은 시드금속을 스퍼터링(sputtering)하고 감광막 코팅 후, 노광(Exposure) 및 현상(Develop)에 의해 감광막 패턴을 형성한다. 이어, 전기 도금방법으로 금속배선을 형성한다. 이때, 형성된 패턴은 감광막에 의해 결정된다. 따라서, 감광막의 접착력이 좋지 않아 들뜨는 경우에, 형성된 패턴은 들뜬 감광막 밑으로 도금 액이 침투하여 넓게 도금되는 단점이 있다.In the plating process for forming the metal wiring of the multi-chip module substrate according to the conventional technology, the photoresist pattern is formed by sputtering the seed metal and coating the photoresist, followed by exposure and development. Subsequently, metal wiring is formed by an electroplating method. At this time, the formed pattern is determined by the photosensitive film. Therefore, when the adhesive force of the photoresist film is not good, the pattern formed is disadvantageous in that the plating liquid penetrates widely under the excited photoresist film.
본 발명은 상술한 종래 기술의 문제점을 해결하기 위하여 안출한 것으로, 멀티 칩 모듈 기판의 금속배선을 형성함에 있어, 시드금속과 감광막의 접착력을 증가시키는 절연막을 형성하여, 도금용액이 감광막의 밑으로 침투하는 것을 방지하는 전기 도금에 의한 금속배선 제조 방법을 제공하는 데 그 목적이 있다.이와 같은 목적을 달성하기 위한 본 발명은, 멀티 칩 모듈 기판의 금속배선 형성을 위한 전기 도금공정에서 금속배선 제조 방법으로서, 상기 기판의 표면에 제 1 절연막을 형성하는 단계와, 상기 제 1 절연막의 표면에 시드금속을 형성하는 단계와, 상기 시드금속의 표면에 제 2 절연막을 형성하는 단계와, 상기 제 2 절연막의 표면에 감광막을 형성하는 단계와, 도금할 부분에 대응하여 상기 감광막을 패터닝하고, 상기 패터닝된 표면을 노광 및 현상하는 단계와, 상기 도금할 부분에 대응하여 상기 감광막의 불필요한 부분을 제거하는 단계와, 상기 감광막 영역을 제외한 영역의 상기 제 2 절연막을 제거하는 단계와, 상기 시드금속의 드러난 표면에 전도체 물질로 전기 도금하는 단계와, 적층된 상기 감광막, 상기 제 2 절연막, 및 상기 시드금속을 제거하는 단계를 포함하는 것을 특징으로 한다.The present invention has been made to solve the above-described problems of the prior art, in forming the metal wiring of the multi-chip module substrate, by forming an insulating film to increase the adhesion between the seed metal and the photosensitive film, the plating solution under the photosensitive film It is an object of the present invention to provide a method for manufacturing metal wiring by electroplating that prevents penetration thereof. To achieve the above object, the present invention provides a method for manufacturing metal wiring in an electroplating process for forming metal wiring on a multi-chip module substrate. A method, comprising: forming a first insulating film on the surface of the substrate, forming a seed metal on the surface of the first insulating film, forming a second insulating film on the surface of the seed metal, and Forming a photoresist film on the surface of the insulating film, patterning the photoresist film corresponding to the portion to be plated, exposing the patterned surface and Removing the unnecessary portion of the photoresist film corresponding to the portion to be plated, removing the second insulating film in a region excluding the photoresist region, and electrically conducting a conductive material to the exposed surface of the seed metal. And plating, and removing the stacked photoresist, the second insulating film, and the seed metal.
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이와 같은 목적을 달성하기 위한 본 발명의 실시예를 첨부된 도면에 의하여 상세히 설명하면 다음과 같다.DETAILED DESCRIPTION Embodiments of the present invention for achieving the above object will be described in detail with reference to the accompanying drawings.
도 1은 본 발명에 따른 멀티 칩 모듈 기판 제조공정에서 전기 도금에 의한 금속배선 제조 방법의 일 실시예를 나타낸 단면도이고, 도 2는 본 발명에 따른 멀티 칩 모듈 기판 제조공정에서 전기 도금에 의한 금속배선 제조 방법의 일 실시예를 단계별로 나타낸 순서도이다.1 is a cross-sectional view showing an embodiment of a metal wiring manufacturing method by electroplating in a multi-chip module substrate manufacturing process according to the present invention, Figure 2 is a metal by electroplating in a multi-chip module substrate manufacturing process according to the present invention A flowchart showing step by step an embodiment of the wiring manufacturing method.
도 1 및 도 2에 있어서, 먼저, 실리콘 기판(1)을 조성비 4:1의 H2SO4/H2O2 용액에 담가서 기판(1) 표면의 모든 먼지와 불순물을 제거한 후, 기판(1)을 20:1의 HF에 침지하여 기판(1)을 세척한다. 기판(1)의 표면에 제 1 절연막으로서 폴리머(2)를 코팅한다(S1).폴리머(2)의 표면에 도금용 시드금속(3)으로서 Ti/Cu를 스퍼터링 방법으로 각각 1000/3000Å의 두께만큼 형성한다(S2).제 2 절연막(4)으로서 감광막(5)과의 접착력이 좋은 Si3N4를 약 0.1㎛ 이하의 두께 예로, 900Å의 두께로 시드금속(3)의 표면에 PECVD(Plasma Enhanced Chemical Vapor Deposition) 방법을 사용해서 250℃의 온도에서 형성한다(S3).제 2 절연막(4)의 표면에 도금용 후막 감광막(5)을 5㎛의 두께로 형성한다. 도금할 부분에 대응하여 감광막(5)을 패터닝하고, 패터닝된 표면을 노광 및 현상한다. 도금할 부분에 대응하여 감광막(5)의 불필요한 부분을 제거한다(S4).감광막(5) 영역을 제외한 영역의 제 2 절연막(4)을 습식식각 방법으로 제거한다(S5).시드금속(3)의 드러난 표면에 전도체 물질 예로, 구리(Cu)로 3㎛의 두께만큼 전기 도금한다(S6).적층된 감광막(5), 제 2 절연막(4), 및 시드금속(3)을 제거하여 금속배선을 형성한다(S7). 이때, 제 2 절연막(4) 및 시드금속(3)은 습식식각 방법으로 에칭한다.1 and 2, first, the silicon substrate 1 is immersed in a H 2 SO 4 / H 2 O 2 solution having a composition ratio of 4: 1 to remove all dust and impurities from the surface of the substrate 1, and then the substrate 1 ) Is immersed in 20: 1 HF to wash the substrate (1). The polymer 2 is coated on the surface of the substrate 1 as a first insulating film (S1). The thickness of 1000/3000 kPa is respectively applied to the surface of the polymer 2 by the sputtering method of Ti / Cu as the seed metal 3 for plating. Si 3 N 4 having good adhesion to the photosensitive film 5 as the second insulating film 4 is formed by PECVD on the surface of the seed metal 3 with a thickness of about 0.1 μm or less, for example, 900 μm. It is formed at a temperature of 250 ° C. using the Plasma Enhanced Chemical Vapor Deposition (S3). [0035] A thick film photosensitive film 5 for plating is formed on the surface of the second insulating film 4 to a thickness of 5 mu m. The photosensitive film 5 is patterned corresponding to the portion to be plated, and the patterned surface is exposed and developed. The unnecessary portion of the photoresist film 5 is removed corresponding to the portion to be plated (S4). The second insulating film 4 in the region excluding the photoresist film 5 region is removed by a wet etching method (S5). On the exposed surface of the electrode), an electroconductive material, for example, copper (Cu), is electroplated by a thickness of 3 μm (S6). The laminated photosensitive film 5, the second insulating film 4, and the seed metal 3 are removed to remove the metal. A wiring is formed (S7). At this time, the second insulating film 4 and the seed metal 3 are etched by a wet etching method.
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따라서, 전기 도금방식으로 구리도금을 행할 때, 감광막(5)과 시드금속(3)의 사이에 절연막(4)이 형성되어 감광막(5)과 시드금속(3)의 접착성을 더욱 좋게 하고 도금용액 즉, 구리가 감광막(5)과 시드금속(3)의 사이로 침투하는 것을 방지할 수 있다.Therefore, when copper plating is performed by the electroplating method, an insulating film 4 is formed between the photosensitive film 5 and the seed metal 3 to further improve the adhesion between the photosensitive film 5 and the seed metal 3 and to plate the copper. The solution, ie, copper, can be prevented from penetrating between the photosensitive film 5 and the seed metal 3.
그리고, 감광막(5)은 코팅되는 두께에 따라 1~2㎛로 도포되는 일반 박막 감광 용액과 3~5㎛의 두께로 도포되는 후막(厚幕) 감광 용액으로 구분되는데, 멀티 칩 모듈 기판의 금속배선 두께는 3㎛로 후막 감광 용액을 사용하여 금속배선을 전기 도금한다.The photoresist film 5 is classified into a general thin film photoresist solution applied at a thickness of 1 to 2 μm and a thick film photoresist solution applied at a thickness of 3 to 5 μm, depending on the thickness of the coating. The wiring thickness is 3 占 퐉 and the metal wiring is electroplated using a thick film photosensitive solution.
이상에서 설명한 바와 같이, 본 발명의 멀티 칩 모듈 기판 제조공정에서 전기 도금에 의한 금속배선 제조 방법은 감광막과 시드금속 사이의 감광막과의 접착력이 좋은 절연막으로 인하여 정확한 패턴 모양을 가지는 멀티 칩 모듈 기판을 제조할 수 있다는 장점이 있다.As described above, in the multi-chip module substrate manufacturing process of the present invention, the metal wire manufacturing method by electroplating uses a multi-chip module substrate having an accurate pattern shape due to an insulating film having good adhesion between the photosensitive film and the seed metal. There is an advantage that it can be manufactured.
이상에서 본 발명의 멀티 칩 모듈 기판 제조공정에서 전기 도금에 의한 금속배선 제조 방법에 대한 기술사상을 첨부도면과 함께 서술하였지만, 이는 본 발명의 가장 양호한 실시예를 예시적으로 설명한 것이지 본 발명을 한정하는 것은 아니다. 또한, 이 기술분야의 통상의 지식을 가진 자이면 누구나 본 발명의 기술사상의 범주를 이탈하지 않는 범위 내에서 다양한 변형 및 모방이 가능함은 명백한 사실이다.In the above, the technical idea of the method for manufacturing metal wiring by electroplating in the manufacturing process of the multi-chip module substrate of the present invention has been described with the accompanying drawings. It is not. In addition, it is obvious that any person skilled in the art can make various modifications and imitations without departing from the scope of the technical idea of the present invention.
도 1은 본 발명에 따른 멀티 칩 모듈 기판 제조공정에서 전기 도금에 의한 금속배선 제조 방법의 일 실시예를 나타낸 단면도,1 is a cross-sectional view showing an embodiment of a metal wiring manufacturing method by electroplating in a multi-chip module substrate manufacturing process according to the present invention;
도 2는 본 발명에 따른 멀티 칩 모듈 기판 제조공정에서 전기 도금에 의한 금속배선 제조 방법의 일 실시예를 단계별로 나타낸 순서도.Figure 2 is a flow chart showing step by step an embodiment of a method for manufacturing metal wiring by electroplating in a multi-chip module substrate manufacturing process according to the present invention.
<도면의 주요부분에 대한 부호의 설명><Description of Symbols for Main Parts of Drawings>
1 : 기판 2 : 폴리머1 substrate 2 polymer
3 : 시드금속 4 : 절연막3: seed metal 4: insulating film
5 : 감광막5: photosensitive film
Claims (9)
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| Application Number | Priority Date | Filing Date | Title |
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| KR10-2000-0003865A KR100530737B1 (en) | 2000-01-27 | 2000-01-27 | Fabrication method of metalization by electroplating in multi-chip module substrate manufacturing process |
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| KR10-2000-0003865A KR100530737B1 (en) | 2000-01-27 | 2000-01-27 | Fabrication method of metalization by electroplating in multi-chip module substrate manufacturing process |
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Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH036023A (en) * | 1989-06-02 | 1991-01-11 | Nec Corp | Formation of fine metal patter |
| JPH0918118A (en) * | 1995-06-30 | 1997-01-17 | Daewoo Electron Co Ltd | Conductor stratification method |
| KR970002878A (en) * | 1995-06-30 | 1997-01-28 | 배순훈 | Pattern flattening method of thin film head |
| JPH11204531A (en) * | 1997-11-12 | 1999-07-30 | Internatl Business Mach Corp <Ibm> | Wiring method for integrated circuit |
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2000
- 2000-01-27 KR KR10-2000-0003865A patent/KR100530737B1/en not_active IP Right Cessation
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH036023A (en) * | 1989-06-02 | 1991-01-11 | Nec Corp | Formation of fine metal patter |
| JPH0918118A (en) * | 1995-06-30 | 1997-01-17 | Daewoo Electron Co Ltd | Conductor stratification method |
| KR970002878A (en) * | 1995-06-30 | 1997-01-28 | 배순훈 | Pattern flattening method of thin film head |
| JPH11204531A (en) * | 1997-11-12 | 1999-07-30 | Internatl Business Mach Corp <Ibm> | Wiring method for integrated circuit |
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