KR100523604B1 - Method for processing imd cmp to reduce processing time - Google Patents
Method for processing imd cmp to reduce processing time Download PDFInfo
- Publication number
- KR100523604B1 KR100523604B1 KR10-2003-0029314A KR20030029314A KR100523604B1 KR 100523604 B1 KR100523604 B1 KR 100523604B1 KR 20030029314 A KR20030029314 A KR 20030029314A KR 100523604 B1 KR100523604 B1 KR 100523604B1
- Authority
- KR
- South Korea
- Prior art keywords
- platen
- polishing
- cmp
- imd
- cmp process
- Prior art date
Links
- 238000000034 method Methods 0.000 title claims abstract description 41
- 238000005498 polishing Methods 0.000 claims abstract description 27
- 239000002002 slurry Substances 0.000 claims description 7
- 238000004140 cleaning Methods 0.000 claims description 5
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 claims description 2
- 101100366711 Arabidopsis thaliana SSL13 gene Proteins 0.000 description 3
- 101100366561 Panax ginseng SS11 gene Proteins 0.000 description 3
- 239000011229 interlayer Substances 0.000 description 3
- 239000004065 semiconductor Substances 0.000 description 3
- 238000004904 shortening Methods 0.000 description 2
- 238000010586 diagram Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000007517 polishing process Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/31051—Planarisation of the insulating layers
- H01L21/31053—Planarisation of the insulating layers involving a dielectric removal step
-
- B—PERFORMING OPERATIONS; TRANSPORTING
- B24—GRINDING; POLISHING
- B24B—MACHINES, DEVICES, OR PROCESSES FOR GRINDING OR POLISHING; DRESSING OR CONDITIONING OF ABRADING SURFACES; FEEDING OF GRINDING, POLISHING, OR LAPPING AGENTS
- B24B37/00—Lapping machines or devices; Accessories
- B24B37/04—Lapping machines or devices; Accessories designed for working plane surfaces
- B24B37/042—Lapping machines or devices; Accessories designed for working plane surfaces operating processes therefor
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Mechanical Engineering (AREA)
- Mechanical Treatment Of Semiconductor (AREA)
- Finish Polishing, Edge Sharpening, And Grinding By Specific Grinding Devices (AREA)
Abstract
본 발명은 IMD CMP 공정의 변화를 통해 공정 시간을 단축시킨 IMD CMP 공정 수행 방법에 관한 것이다. 즉, 본 발명은 IMD CMP 공정에서 플래튼1, 2에서 주 연마와 버핑 연마가 모두 진행되도록 하고, 옥사이드 막질을 연마하는 곳을 플래튼1과 플래튼2만으로 장비를 구현함으로써, 종래 버핑 연마를 위한 플래튼3을 생략가능하여 장비의 풋프린트를 줄일 수 있으며, 플래튼3으로의 이동시간이 생략되어 전체적인 CMP 공정시간을 줄일 수 있게 된다.The present invention relates to a method for performing an IMD CMP process, which shortens the process time through a change in the IMD CMP process. That is, according to the present invention, the main buffing and the buffing polishing are performed in the platen 1 and 2 in the IMD CMP process, and the conventional buffing polishing is implemented by implementing the equipment using only the platen 1 and the platen 2 to polish the oxide film. By eliminating the platen 3, the footprint of the equipment can be reduced and the transfer time to the platen 3 can be omitted, thereby reducing the overall CMP process time.
Description
본 발명은 반도체 소자의 평탄화 방법에 관한 것으로, 특히 IMD(Insulator Metal Dielectric) CMP(Chemical-Mechanical Polishing) 공정의 변화를 통해 공정 시간을 단축시킨 IMD CMP 공정 수행 방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a planarization method of a semiconductor device, and more particularly, to a method of performing an IMD CMP process by shortening a process time by changing an insulator metal dielectric (IMD) chemical-mechanical polishing (CMP) process.
현재 반도체 제조 공정에 있어서 반도체 소자가 고집적화 되어가고 배선의 수가 많아짐에 따라 층간 절연막의 평탄화 정도가 후속 공정에 미치는 영향이 점점 커지고 있어 층간 절연막에 대한 평탄화 공정의 중요성이 부각되고 있다.In the current semiconductor manufacturing process, as semiconductor devices are highly integrated and the number of wirings increases, the leveling effect of the planarization of the interlayer insulating film is increasing in subsequent processes, and the importance of the planarization process for the interlayer insulating film is highlighted.
상기 층간 절연막에 대한 평탄화를 위해서 종래에는 주로 에치백(Etch back), SOG(Spin On Glass) 등의 방법이 사용되어 왔으며, 현재는 글로벌 평탄화를 얻을 수 있는 CMP공정이 주로 사용되고 있다.In order to planarize the interlayer insulating film, methods such as etch back and spin on glass (SOG) have been mainly used in the past, and at present, a CMP process capable of obtaining global planarization is mainly used.
도 1은 상기 CMP 공정 중 하나인 종래 IMD CMP 공정 순서도를 도시한 것으로, 먼저 CMP 장치(200)로 CMP 수행될 웨이퍼(Wafer) 로트(Lot)를 로딩하여 로트내 웨이퍼를 스캔한 후(S100), HCLU(Head Clean Load Unload) 로딩을 수행하여 HCLU 각 헤드에 CMP 수행할 웨이퍼를 위치시킨다(S102). 이어 도 2에서 보여지는 바와 같이 플래튼(Platen) 1(202), 플래튼 2(204)에서는 상기 HCLU에 로딩된 웨이퍼에 대해 SS11 슬러리를 사용하여 주 연마가 수행되며(S104, S106), 플래튼 3(206)에서는 버핑 연마(Buffing polish)가 수행된다(S108). 이때 상기 플래튼 1, 2(202, 204)에서 사용되는 연마패드(Polish pad)는 로델(Rodel)사의 IC1010 이 사용되며, 플래튼 3(206)에서는 버프패드(Buff pad)를 이용하여 DI 워터로 연마개념이 아닌 막질 표면의 클리닝 개념의 연마가 진행된 후, 클리닝 공정을 수행하여 CMP 공정을 마치게 된다(S110).1 is a flowchart illustrating a conventional IMD CMP process flow chart, which is one of the CMP processes. First, a wafer lot to be CMP is loaded into the CMP apparatus 200 to scan a wafer in the lot (S100). In step S102, a HCLU (Head Clean Load Unload) loading is performed to position the wafer to be CMPed on each head of the HCLU. Subsequently, as shown in FIG. 2, in Platen 1 202 and Platen 2 204, main polishing is performed using SS11 slurry on the wafer loaded on the HCLU (S104 and S106). In turn 3 206, buffing polish is performed (S108). At this time, the polishing pad used in the platens 1 and 2 202 and 204 is a rod of IC1010 manufactured by Rodel, and the platen 3 206 uses DI water using a buff pad. After the polishing of the cleaning concept of the film surface rather than the polishing concept is performed, the cleaning process is performed to complete the CMP process (S110).
그러나 상기한 종래 IMD CMP 공정에서는 플래튼1, 2에서만 주 연마가 진행되므로, 플래튼3에서 버핑 연마를 별도의 공정으로 진행하여야 함에 따라 공정상 효율적이지 못한 문제점이 있었다.However, in the above-described conventional IMD CMP process, since the main polishing is performed only on the platens 1 and 2, there is a problem in that the buffing polishing is performed in a separate process in the platen 3, which is not efficient in the process.
따라서, 본 발명의 목적은 IMD CMP 공정의 변화를 통해 공정 시간을 단축시킨 IMD CMP 공정 수행 방법을 제공함에 있다.Accordingly, an object of the present invention is to provide a method for performing an IMD CMP process, which shortens the process time by changing the IMD CMP process.
상술한 목적을 달성하기 위한 본 발명은 IMD CMP 공정 수행 방법에 있어서, (a)상기 CMP 수행할 웨이퍼를 HCLU로 로딩시키는 단계와; (b)상기 HCLU로 로딩된 웨이퍼에 대해 플래튼1에서 주 연마를 수행시키는 단계와; (c)상기 플래튼1에서 주 연마 수행된 웨이퍼에 대해 플래튼2에서 주 연마와 버핑 연마를 수행시키는 단계와; (d)상기 연마 수행된 웨이퍼를 클리닝 수행하여 언로딩시키는 단계;를 포함하는 것을 특징으로 한다.In order to achieve the above object, the present invention provides a method for performing an IMD CMP process, comprising: (a) loading a wafer to be subjected to CMP with HCLU; (b) performing main polishing on platen 1 for the wafer loaded with HCLU; (c) performing main polishing and buffing polishing on platen 2 for the wafer subjected to main polishing on platen 1; and (d) cleaning and unloading the polished wafer.
이하, 첨부된 도면을 참조하여 본 발명에 따른 바람직한 실시 예의 동작을 상세하게 설명한다.Hereinafter, with reference to the accompanying drawings will be described in detail the operation of the preferred embodiment according to the present invention.
도 3은 본 발명의 실시 예에 따른 IMD CMP 공정 순서도를 도시한 것이다. 이하 상기 도 3을 참조하여 본 발명의 실시 예에 따라 CMP 공정 시간을 단축시키는 IMD CMP 공정을 상세히 설명하기로 한다.3 is a flowchart illustrating an IMD CMP process according to an embodiment of the present invention. Hereinafter, an IMD CMP process for shortening a CMP process time according to an embodiment of the present invention will be described in detail with reference to FIG. 3.
먼저 CMP 장치로 CMP 수행될 웨이퍼 로트를 로딩하여 로트내 웨이퍼를 스캔한 후(S300), HCLU 로딩을 수행하여 HCLU 각 헤드에 CMP 수행할 웨이퍼를 위치시킨다(S302). First, a wafer lot to be CMP is loaded into a CMP apparatus to scan a wafer in a lot (S300), and then HCHC loading is performed to place a wafer to be CMP on each head of the HCLU (S302).
이어 도 4에서 보여지는 바와 같이 플래튼 1(402)에서 상기 HCLU에 로딩된 웨이퍼에 대해 SS11 슬러리를 사용하여 주 연마를 수행하며(S304), 플래튼 2(404)에서는 본 발명에 따라 상기 HCLU에 로딩된 웨이퍼에 대해 SS11 슬러리를 사용하여 주 연마 및 버핑 연마를 동시에 수행시킨 후(S306), 클리닝 공정을 수행하여 CMP 공정을 마치게 된다(S308). 상기 버핑연마는 상기 플래튼2에서 주 연마 이후 상기 플래튼2로 연마 슬러리의 공급을 차단하고 DI를 공급하여 수행한다.Subsequently, as shown in FIG. 4, main polishing is performed on the wafer loaded on the HCLU in platen 1 402 using an SS11 slurry (S304), and in the platen 2 404, the HCLU according to the present invention. After performing the main polishing and the buffing polishing using the SS11 slurry on the wafer loaded at the same time (S306), the CMP process is completed by performing the cleaning process (S308). The buffing polishing is performed by interrupting the supply of the polishing slurry to the platen 2 after the main polishing in the platen 2 and supplying DI.
이때, 상기 도 4에서와 같이 옥사이드 막질을 연마하는 곳을 플래튼 1(402)과 플래튼 2(404)만으로 CMP 장비를 구현하고, 종래 행하던 플래튼 3의 버핑 연마는 플래튼 2(404)의 연마 공정의 레서피(Recipe)를 변경(Tuning)하여 사용한다. 즉, 고속 RPM을 유지하면서 연마 후, DI 린스(Rinse) 개념으로 진행하게 되는 것이다. In this case, as shown in FIG. 4, the CMP device is implemented using only the platen 1 402 and the platen 2 404 as the place where the oxide film is polished, and the buffing polishing of the platen 3 that is conventionally performed is platen 2 404. The recipe of the polishing process is changed. That is, after polishing while maintaining a high RPM, it will proceed to the DI rinse (Rinse) concept.
이에 따라 CMP 장비의 크기를 줄일 수 있으며, 종래에 비해 공정 시간을 줄일 수 있게 된다. Accordingly, it is possible to reduce the size of the CMP equipment, and to reduce the process time compared to the conventional.
한편 상술한 본 발명의 설명에서는 구체적인 실시 예에 관해 설명하였으나, 여러 가지 변형이 본 발명의 범위에서 벗어나지 않고 실시될 수 있다. 따라서 발명의 범위는 설명된 실시 예에 의하여 정할 것이 아니고 특허청구범위에 의해 정하여져야 한다.Meanwhile, in the above description of the present invention, specific embodiments have been described, but various modifications may be made without departing from the scope of the present invention. Therefore, the scope of the invention should be determined by the claims rather than by the described embodiments.
이상에서 설명한 바와 같이, 본 발명은 IMD CMP 공정에서 플래튼1, 2에서 주 연마와 버핑 연마가 모두 진행되도록 하고, 옥사이드 막질을 연마하는 곳을 플래튼 1과 플래튼 2만으로 장비를 구현함으로써, 종래 버핑 연마를 위한 플래튼 3을 생략가능하여 장비의 풋프린트를 줄일 수 있으며, 플래튼 3으로의 이동시간이 생략되어 전체적인 CMP 공정시간을 줄일 수 있게 되는 이점이 있다.As described above, the present invention is to perform both the main polishing and buffing polishing in the platen 1, 2 in the IMD CMP process, by implementing the equipment only in the platen 1 and platen 2 to polish the oxide film, It is possible to omit the platen 3 for the conventional buffing polishing to reduce the footprint of the equipment, there is an advantage that can be reduced the overall CMP process time by eliminating the travel time to the platen 3.
도 1은 종래 IMD CMP 공정 수순도,1 is a flow chart of a conventional IMD CMP process;
도 2는 종래 IMD CMP 장비에서 IMD CMP 수행 예시도,2 is an exemplary view of performing IMD CMP in the conventional IMD CMP apparatus;
도 3은 본 발명의 실시 예에 따른 IMD CMP 공정 수순도,3 is an IMD CMP process purity diagram according to an embodiment of the present invention;
도 4는 본 발명의 실시 예에 따른 IMD CMP 장비에서 IMD CMP 수행 예시도.Figure 4 is an illustration of performing IMD CMP in IMD CMP equipment according to an embodiment of the present invention.
Claims (3)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR10-2003-0029314A KR100523604B1 (en) | 2003-05-09 | 2003-05-09 | Method for processing imd cmp to reduce processing time |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR10-2003-0029314A KR100523604B1 (en) | 2003-05-09 | 2003-05-09 | Method for processing imd cmp to reduce processing time |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| KR20040096336A KR20040096336A (en) | 2004-11-16 |
| KR100523604B1 true KR100523604B1 (en) | 2005-10-24 |
Family
ID=37375074
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| KR10-2003-0029314A KR100523604B1 (en) | 2003-05-09 | 2003-05-09 | Method for processing imd cmp to reduce processing time |
Country Status (1)
| Country | Link |
|---|---|
| KR (1) | KR100523604B1 (en) |
-
2003
- 2003-05-09 KR KR10-2003-0029314A patent/KR100523604B1/en not_active IP Right Cessation
Also Published As
| Publication number | Publication date |
|---|---|
| KR20040096336A (en) | 2004-11-16 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US6350694B1 (en) | Reducing CMP scratch, dishing and erosion by post CMP etch back method for low-k materials | |
| US6946397B2 (en) | Chemical mechanical polishing process with reduced defects in a copper process | |
| US20060057945A1 (en) | Chemical mechanical polishing process | |
| JP3197830B2 (en) | Method for forming metal pattern on semiconductor wafer | |
| Malik et al. | Manufacturability of the CMP process | |
| US9511475B2 (en) | Polishing device for removing polishing byproducts | |
| US6227949B1 (en) | Two-slurry CMP polishing with different particle size abrasives | |
| US6191039B1 (en) | Method of CMP of polysilicon | |
| US6443807B1 (en) | Polishing process for use in method of fabricating semiconductor device | |
| US20240217052A1 (en) | Zone-based cmp target control | |
| US6660627B2 (en) | Method for planarization of wafers with high selectivities | |
| US7297632B2 (en) | Scratch reduction for chemical mechanical polishing | |
| KR100523604B1 (en) | Method for processing imd cmp to reduce processing time | |
| US6248002B1 (en) | Obtaining the better defect performance of the fuse CMP process by adding slurry polish on more soft pad after slurry polish | |
| US6548409B1 (en) | Method of reducing micro-scratches during tungsten CMP | |
| US20060157080A1 (en) | Cleaning method for semiconductor wafer | |
| KR100523660B1 (en) | Method for processing hss cmp to reduce processing time | |
| US20070062910A1 (en) | Complex CMP process and fabricating methods of STI structure and interconnect structure | |
| US6482732B1 (en) | Method and apparatus for polishing semiconductor wafer | |
| US7025661B2 (en) | Chemical mechanical polishing process | |
| US20090286453A1 (en) | Method and apparatus for chemical-mechanical polishing | |
| KR100880108B1 (en) | Method of polishing semiconductor wafer and apparatus for the same | |
| US7361602B1 (en) | CMP process | |
| US20110275216A1 (en) | Two step chemical-mechanical polishing process | |
| KR20070002547A (en) | Method of manufacturing semiconductor device |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| A201 | Request for examination | ||
| E902 | Notification of reason for refusal | ||
| E701 | Decision to grant or registration of patent right | ||
| GRNT | Written decision to grant | ||
| FPAY | Annual fee payment |
Payment date: 20100915 Year of fee payment: 6 |
|
| LAPS | Lapse due to unpaid annual fee |