KR100523335B1 - GPS Receiver having Precise-Controlled Local Oscillator, GPS Clock Device and Duplexed GPS Clock Device using the GPS Receiver - Google Patents

Abstract

The present invention relates to a GPS receiver and a GPS clock device using the same, by providing a circuit and an algorithm capable of controlling a local oscillator of a GPS receiver and supplying time and frequency having an accuracy and stability of atomic clock. Local oscillator including a local oscillator and a signal processor for controlling the local oscillator, and using the phase difference information of the internal 1PPS (Pulse Per Second) signal generated from the GPS signal and the output 1PPS signal generated by dividing the local oscillator. It is possible to predict the error of time and frequency of the local oscillator, output the control value of the local oscillator, and control the control value more precisely using temperature characteristic data and / or age characteristic data of the local oscillator.

According to the present invention, the local oscillator of the GPS receiver can be directly controlled to further improve the efficiency and economy of the system as compared to the conventional GPS clock device having a separate local oscillator and microprocessor in addition to the GPS receiver. This guarantees accurate and stable visual information even under unstable tracking conditions.

Description

GPS receiver, GPS clock device and duplexed GPS clock device using the GPS receiver with precision controllable local oscillator {GPS Receiver having Precise-Controlled Local Oscillator}

The present invention provides a GPS receiver having a precisely controllable local oscillator, a GPS clock device and a redundant GPS clock device, and more particularly a GPS receiver having a local oscillator capable of precise control by a predetermined control circuit, and a separate view. The present invention relates to a GPS clock device including a GPS receiver having a local oscillator capable of precise control without using a dedicated GPS receiver, and a redundant GPS clock device including two or more GPS clock units using the aforementioned GPS receiver.

In general, a local oscillator (LO) of a GPS receiver is a device that supplies a reference frequency to an RF unit of a receiver. In general, GPS receiver measurements are based on the time of arrival (TOA) based on the phase of the Pseudo Random Noise (PRN) code unique to each GPS satellite, the phase and frequency information of the received carrier. The local oscillator of a GPS receiver is a very important part because it is based.

However, the oscillator with excellent stability is slower than other parts of the GPS receiver, making it the most expensive and largest component of any GPS receiver. Considering the cost or the size of the device, in today's general GPS receivers, although the stability is not good, the low cost and small size-compensated crystal oscillator (TCXO) is mainly used as a local oscillator. Algorithms for analyzing the relationship and compensating for the frequency error are well known. However, special purpose GPS receivers need to use an oscillator having better stability than the aforementioned TCXO.

The present invention proposes a GPS receiver capable of supplying time and frequency with atomic clock accuracy and stability using circuits and algorithms that can control the frequency of the local oscillator of the GPS receiver.

In addition, the present invention proposes a GPS clock device using a GPS receiver according to the present invention for controlling a local oscillator in place of a conventional GPS clock device using a GPS clock core.

First, the configuration of a conventional GPS receiver and a GPS clock device will be described.

GPS receiver

GPS is a new satellite navigation system developed for military use by the US Department of Defense and currently provides free navigation service using 24 GPS satellites worldwide. GPS has the advantage of being more accurate and easy to use than the existing navigation system, and can be used regardless of time, place and weather conditions. In addition, it has the function to simultaneously provide 10 kinds of information about the moving user's three-dimensional position, speed, posture, and time. Location information is a reference coordinate called WGS84, and time is provided unified with a reference time called GPS time. Therefore, users can get information about their time and space very easily anytime and anywhere with a GPS receiver.

1 is a functional block diagram of a conventional GPS receiver, which includes a GPS antenna 11, a down convertor 12, a correlation system 13, and an oscillator 14 that receive a GPS signal largely. ), A temperature sensor 15, an antenna check circuit 16, and a signal processor (microprocessor) 17.

The GPS receiver first converts the received GPS signal into an intermediate frequency through a down-converter and delivers the signal to a correlation system. The downconverter is composed of several mixers, which receive a reference frequency from the oscillator to form a phase locked loop (PLL) that controls a voltage controlled oscillator (VCO) and synthesizes the synthesized frequency. To each mixer. The correlator removes a carrier from an IF signal input by using a carrier tracking loop, and the PRN code constituting the GPS signal is correlated with the same code generated inside the receiver. (Correlation) delivers the integrated data to the microprocessor.

The microprocessor calculates the pseudorange and pseudorange rate from each satellite and extracts GPS satellite data by using the integral and measured data input from the correlation system. Through the predetermined navigation algorithm, information such as the position, speed, and time of the receiver is calculated.

In today's general GPS receivers, although the stability is not good, the low cost and compact Temperature-Compensated Crystal Oscillator (TCXO) is mainly used as a local oscillator, and the algorithm that compensates for the frequency error by analyzing the temperature and frequency correlation of TCXO Already known.

GPS clock core and GPS clock device using the same

In general, GPS is known to be used only for location tracking, but the 1PPS signal and TOD (Time Of Date) that can be obtained from GPS can be used as a very stable time source in the long term.

The 24 GPS satellites, orbiting 22,000 km, are equipped with a cesium atomic clock and a rubidium atomic clock, respectively, which are monitored and controlled by a ground station (Control Segment). In addition, each satellite transmits its own navigation message with the error of the atomic clock against UTC (Universal Time Coordinate).

In general, the 1PPS that can be obtained from a TCXO-enabled GPS receiver is less than about 100 nsec, which is not so good as 1.0 × 10 ^{-8 in} terms of short Term Stability. However, GPS's 1PPS has little phase drift to UTC, making it a very accurate time and frequency source that can replace atomic clocks in terms of long term stability.

General GPS clock cores use interval averages or Kalman filters to filter 1PPS of unstable GPS in the short term. Such a filter is implemented such that the output of the GPS lock core maintains excellent oscillator characteristics in terms of short-term stability and shows 1PPS characteristics of GPS in terms of long-term stability. As a result, GPS can be used to obtain time and frequency with excellent long-term and short-term stability.

The conventional GPS clock core has the configuration as shown in FIG. 2, and includes a GPS receiver 21 for providing time information such as 1PPS and TOD included in the GPS signal, a self-oscillator 22 of the clock core, and a GPS receiver. Phase Detector (23) for detecting the difference between the time information and the output of the self-oscillator, and a signal processor 24 including a filter for controlling the frequency and time of the self-oscillator according to the phase difference . The signal processor controls the frequency and time of the self oscillator according to the phase difference by a predetermined control algorithm and appropriate filtering.

As such, most of the GPS clock cores currently used are equipped with a time-only GPS receiver supplied by a GPS receiver manufacturer as a reference time source, as shown in FIG. An oscillator for a GPS clock core is provided separately. Therefore, the controller for measuring the time difference from the output of the time-only GPS receiver and the output of the GPS clock core oscillator separate from the output and accordingly controls the oscillator for the GPS clock core is independently implemented. Independent means that the two parts are connected in a physically separable input and output relationship, that is, there are independent microprocessors that manage the operation of the two parts of the GPS clock core and the GPS clock core. do.

In other words, as shown in FIG. 2, after receiving the time information from the time-only GPS receiver and comparing the output with the oscillator, the oscillator is controlled according to the difference. There are many products that use common GPS receivers (GPS clock devices, etc.). However, most of them implement only simple interface circuit with GPS receiver and use only protocol of receiver.

As described above, the GPS clock core having the structure independent of the GPS receiver has the following disadvantages. First, since the GPS peripheral band process part and the control process part of the oscillator are separated from each other and the hardware peripherals are overlapped, it is difficult to overcome the current trend of miniaturization and integration. Second, since the information supplied to the GPS clock core is limited in most visual GPS receivers, application fields are limited because the GPS navigation message information cannot be shared and processed. Third, if the receiver's 1PPS is momentarily out of UTC in an environment where satellite tracking is unstable, it can have a fatal effect on the control of the oscillator.

The present invention has been proposed to overcome the disadvantages of the conventional GPS receiver and GPS clock device has the following object.

SUMMARY OF THE INVENTION An object of the present invention is to provide a GPS receiver and a GPS clock device using the same, by adding a circuit and an algorithm capable of directly controlling a local oscillator provided in a GPS receiver to supply time and frequency with atomic clock accuracy and stability. will be.

Another object of the present invention is to directly control the local oscillator of the GPS receiver, when the GPS satellite signal is received in the GPS lock mode, and when there is no GPS satellite signal or the error operating in the holdover mode GPS It is to provide a local oscillator control method of a receiver.

Another object of the present invention is to provide a GPS clock device comprising two or more GPS clock units having a local oscillator directly and precisely controlled, and a duplication method using the same, thereby providing more stable and accurate time information.

GPS receiver including a precisely controllable local oscillator according to the present invention has the following configuration.

One or more GPS signal receiving antennas, a downconverter for converting GPS signals received from the antenna into intermediate frequency band signals, a local oscillator precisely controlled by a predetermined signal processor, and an intermediate frequency band from the downconverter Correlation system for extracting the PRN code included in the GPS signal by removing the carrier of the signal, performing correlation with the corresponding code generated by itself, and delivering the generated integral data to the signal processor, and the correlation A reference time generator (1PPS Generator) for generating an internal reference time (1PPS) based on data from a base, and an output 1PPS signal generated by dividing an output of the local oscillator and an internal 1PPS from the reference time generator. Check the connection between phase detection system, temperature sensor, and antenna to detect phase difference A signal processor (or microprocessor) having a function of receiving data from at least one of an antenna check circuit, a phase detector, a temperature sensor, and an antenna check circuit and outputting control values of a local oscillator, and a control of a local oscillator It includes a storage unit for storing information about the algorithm.

Of course, the signal processing unit calculates a pseudo distance from the satellite using integrated data and measurement data from the correlator, which is a basic function of the GPS receiver, in addition to the above-described functions, and uses a predetermined navigation algorithm to determine its current position and time. A navigation solution calculation function for calculating a navigation solution including a is further provided.

The local oscillator is an OCXO (Oven Controlled Crystal Oscillator), it is preferable that each of the OCXO unique temperature characteristics, menopausal characteristics data is stored in the storage unit.

The signal processor estimates the error of time and frequency of the local oscillator using the phase difference information of the internal 1PPS signal input from the phase detector and the output 1PPS signal generated by dividing the output of the local oscillator. In this case, the control value may be more precisely calculated using temperature characteristic data and / or Aging characteristic data of the local oscillator stored in the storage.

When the signal processing unit normally receives one or more GPS signals and outputs an appropriate internal 1PPS signal, the signal processor calculates a local oscillator control value according to the GPS lock mode as described above, and when the GPS signal is not received or an antenna fails. Alternatively, when the internal 1PPS differs from the output 1PPS by more than a threshold value, the local oscillator control value is calculated in the holdover mode.

In detail, the signal processing unit receives a state signal in which all antennas do not operate or a state signal for limiting input of a GPS signal from an antenna check circuit, or a difference between an internal 1PPS signal and an output 1PPS signal exceeds a predetermined threshold. In this case, instead of calculating a control value using an internal 1PPS signal calculated from a received GPS signal, a hold for calculating a control value of the local oscillator using only temperature characteristic data and / or aging characteristic data of the local oscillator stored in the storage unit. It is desirable to operate in Holdover Mode.

In addition, the signal processing unit operates in the GPS lock mode when a signal is received from one or more GPS satellites, and the GPS lock mode is based on the location information during the predetermined time when three or more GPS satellite signals are received for a predetermined time or more. Position Hold Mode, which calculates the control value after determining the current position of the receiver, and when receiving signals from less than three GPS satellites, determines the receiver position at that point in time. It is preferable that the calculation is made in a quick position hold mode.

Looking at the method of calculating the local oscillator control value in the GPS lock mode in more detail, in the GPS lock mode, the microprocessor receives a time interval value between the internal 1PPS signal and the output 1PPS signal every predetermined time from the phase detector. The interval average value is calculated during the preheating time period according to the control period, and the interval average value and the Kalman Filter are used to predict the error of time and frequency, and the temperature coefficient of the oscillator is calculated to determine the control value. At this time, in consideration of the frequency characteristics of the oscillator, the control is initially performed in a short cycle, and when a certain amount of time (about 1 hour) has elapsed, the control cycle can be lengthened to ensure the accuracy and stability of the frequency. Adjusting the control period in this way has the effect of adjusting the bandwidth of the response characteristics of the control loop. In other words, a shorter period of time widens the response characteristic band to increase the response speed, but it is sensitive to noise of 1PPS, and a longer period of time narrows the response band width to slow the response speed, resulting in the elimination of 1PPS noise. Has the effect.

In holdover mode, the microprocessor records the control values for controlling the oscillator, the current surface temperature of the oscillator, or the current consumption of the oscillator once per control period, along with the time, during the GPS lock mode prior to the holdover mode. In the holdover mode, the oscillator is estimated after estimating the age coefficient and temperature coefficient of the oscillator using the least square algorithm using the recorded square algorithm. Calculate the control value of.

The control value calculation in the holdover mode first determines the suitability of the estimated aging coefficient and the temperature coefficient and, if appropriately, measures one or more of elapsed time (dt), temperature change (dT), and aging coefficient. The increment of the control value DAC (PRE_dDAC) is obtained, and the control value DAC_k-1 is obtained by adding the increment of the control value with the control value DAC_k-1 in the previous control period, and the temperature characteristic table of the oscillator is obtained. Calculated by adding the temperature characteristic control value increment (TEMP_DAC) mapped from the current temperature to the current temperature.

The apparatus may further include a time / frequency driver for outputting necessary information based on data from the local oscillator and the phase detector. That is, the time / frequency driver receives frequency-related data from the local oscillator, receives time-related data from the phase detector, and generates and outputs a frequency output, a time output, a TOD output, and the like, such as a required system clock signal.

The apparatus may further include a D / A converter and / or filter means for converting and filtering the control value from the signal processor into an analog signal to generate an analog control signal.

When the analog control signal S_con is greater than or equal to N and less than N + 1, the signal processor outputs a control value of N for (N + 1-S_con) time and outputs a control value of N + 1 to (S_con-N). It is preferable to use a software pulse width modulation scheme that outputs as time, but distributes each control value evenly by dividing each control value into short cells.

The GPS clock device according to the present invention is to provide a precise clock to a predetermined device or to provide time information. The GPS clock device according to the present invention receives a reference frequency from the GPS receiver and the GPS receiver of the above-described configuration, and generates clock or time information having a required specification. It can be configured to include a frequency synthesizer.

In addition, the GPS clock device of the redundant structure according to the present invention is composed of two or more GPS clock unit, each GPS clock unit receives the GPS receiver of the above-described configuration, and the reference frequency from the GPS receiver to generate a clock of the required specification Frequency Synthesizer, Redundancy Interface for transmitting / receiving each other's self-diagnostic data, and Output Driver which outputs clock or time information to the outside and is activated or deactivated. If a failure occurs in the currently activated clock unit, the clock driver deactivates the output driver of the corresponding clock unit and activates the output driver of the other clock unit.

Hereinafter, with reference to the accompanying drawings will be described in detail an embodiment of the present invention. First of all, in adding reference numerals to the components of each drawing, it should be noted that the same reference numerals are used as much as possible even if displayed on different drawings. In addition, in describing the present invention, when it is determined that the detailed description of the related well-known configuration or function may obscure the gist of the present invention, the detailed description thereof will be omitted.

First, the performance (or required specification) of the GPS receiver or GPS clock device according to the present invention and the basic control algorithm of the GPS receiver and GPS clock device according to the present invention will be briefly described.

Performance (required specification) of GPS clock core and GPS clock device according to the present invention

1) visual and frequency performance

In order to replace the existing GPS clock core, the accuracy and stability of the basic output time and frequency must be secured.

First of all, frequency accuracy is basically the most important performance. The results of FIG. 3 are measured using a frequency counter to measure the accuracy of 10 MHz, which is the fundamental frequency of the GPS clock core according to the present invention. The reference frequency of the frequency counter used 10 MHz of cesium atomic clock.

Spec. <5.8 10 ^-13   (1 day Average)

The stability of the frequency can be obtained by post-processing the above measurement results. The results are shown in the following FIG. 4.

Spec. <1.0 10 ^-11   (ADEV: 4 << 8103,: Sampling Time)

In order to measure the accuracy of the basic clock (1PPS) of the GPS clock core, the time difference was measured using a frequency counter for 5 days based on the 1PPS output of the cesium atomic clock synchronized with the GPS 1PPS. 5 is shown. Here, the visual error bias (Bias) by the antenna cable and the 1PPS connection cable is assumed as the average of the measurement error and removed. The results are summarized as follows.

Spec. : 10ns (1σ), 22ns (2σ)

2) Oscillator Control Algorithm

In the oscillator control of the GPS clock core according to the present invention, as shown in FIG. 6, there are two types of GPS locked states for using a GPS signal and a holdover mode for not using a GPS signal. Requires a control algorithm of.

In the GPS lock mode, the time difference between 1PPS of the GPS receiver and 1PPS divided by the oscillator's output frequency is measured and averaged over a few tens to hundreds of seconds, or a probability filter is generated from UTC and the GPS clock core. The visual error of 1PPS can be estimated. Also, by looking at the variation of the estimated time error, the frequency error output from the current GPS clock core self oscillator can be estimated. The oscillator controller is implemented as a proportional or proportional and integral controller to minimize this estimation error.

If the GPS satellite signal cannot be received, the 1PPS of the receiver is unreliable, so the GPS clock core should be operated in a holdover state. When using an oscillator with good disturbance sensitivity and aging performance, such as rubidium, the final control value of the GPS lock mode is maintained. However, the disturbance sensitivity and aging rate performance, such as OCXO (Oven Controlled Crystal Oscillator) In the case of not being superior to the required performance, it is necessary to improve the performance by modeling and controlling the temperature characteristics of the OCXO and the characteristics of aging change for each OCXO.

3) Required output performance of GPS clock device

In general, the GPS clock device used in the wireless communication network system is 10MHz output from the GPS clock core. In addition to 1PPS and TOD output, it should be able to output system clock, 1PP2S, etc., and each output performance should be guaranteed even in the holdover state where satellites cannot be tracked normally except in the GPS lock mode. The required output performance of general GPS clock device is shown in <Table 1>.

 Output performance of GPS clock device Item Specification 10 MHz Accuracy <1.0 10 ^-11 (GPS Locked, 1 day Average) <1.0 10 ^-10 (Holdover, 1 day Average) Stability <1.0 10 ^-11 (ADEV: = 100sec,: Sampling Time) 1PPS Accuracy <200 ns (GPS Locked, 2) <8sec (after 24hr of Holdover) System clock Accuracy <1.0 10 ^-11 (1 day Average) <1.0 10 ^-10 (Holdover, 1 day Average) Stability <1.0 10 ^-11 (ADEV: = 100sec,: Sampling Time) 1PP2S  Accuracy <100ns (Time Difference with 1PPS)

In addition, the GPS clock device should perform a redundant operation as necessary. Redundancy operation means that when two GPS clock outputs are connected to each other, when a problem occurs in the operation of the software and / or hardware, the troubled time and frequency outputs are continuously switched to be replaced with the normal time and frequency outputs. It means action. Basically, since the GPS clock device is the core equipment of the wireless communication network system, it is designed in such a redundancy method to enhance the stability of the whole system. In order to perform the redundancy operation, the GPS clock device must have various self-diagnostic functions including the tracking status of GPS satellites, and inform the counterpart system to which its output is connected and perform the function of reading the counterpart's diagnosis result. do.

Configuration of the System According to the Invention

As illustrated in FIG. 7, the system according to the present invention, that is, a GPS receiver, includes one or more GPS signal receiving antennas (GPS antennas) 110 and a down converter for converting GPS signals received from the antennas into intermediate frequency band signals. 111, a local oscillator 112 precisely controlled by a predetermined signal processor, and a carrier of an intermediate frequency band signal from the downconverter are removed to extract a PRN code included in the GPS signal. A correlator (113) for performing the correlation with the generated corresponding code and transferring the generated integral data to the signal processor, and generating an internal reference time (1PPS) based on the data from the correlator. Phase difference between the 1PPS generator 114 and the output 1PPS signal generated by dividing the output of the local oscillator and the internal 1PPS from the reference time generator. Phase detection unit (Phase Detection System; 115), temperature sensor (Temperature Sensor; 116), antenna check circuit (Antenna Check Circuit 117) for checking the connection state of the antenna, phase detection unit, temperature sensor And a microprocessor (118) as a signal processor having a function of receiving data from at least one of the antenna check circuits and outputting control values of the local oscillator, and a storage unit storing information on the control algorithm of the local oscillator. Non-volatile memory (Non-Volatile Memory) 119 as an example.

Of course, time for generating and outputting necessary frequency / time information based on inputs from the D / A converter 120 and the filter 121, the phase detector and the local oscillator for converting and filtering the local oscillator control values. A frequency driver 122 may further include an interface circuit 123 connecting the antenna check circuit and the microprocessor.

In addition, the GPS clock device according to the present invention may further include a frequency synthesizer for receiving accurate time or frequency information from the GPS receiver as described above and synthesizing the clock, time information, and frequency information required for the device to which the clock device is applied. . This clock can be any system clock or the like.

The operation of the GPS receiver or GPS receiver included in the GPS clock device is as follows.

The GPS receiver controlling the local oscillator 112 first converts the received GPS signal down to an intermediate frequency band signal (IF signal) through a down-converter (111) and then correlates (Correlation System) 113. To pass on. The down-converter 111 includes a plurality of mixers. The down-converter 111 receives a reference frequency from an oscillator under control and configures a PLL to control a voltage controlled oscillator (VCO) and synthesizes the synthesized frequency. Is supplied to each mixer.

The correlator system 113 removes a carrier (or carrier) of the input IF signal using a predetermined carrier tracking loop and removes the PRN code constituting the GPS signal. Extract. Thereafter, the same code generated inside the receiver and the extracted PRN code are correlated to generate integrated data, and then deliver the integrated data to the microprocessor 118. In addition, the correlation system 113 provides a basic clock so that the reference time generator 1PPS 114 may provide a reference time 1PPS for controlling the oscillator.

The phase detection system 115 inputs an internal 1PPS synchronized with UTC and a 10MHz clock from the local oscillator from the reference time generator 1PPS Generator 114. The 10MHz clock input from the local oscillator is divided to generate 1PPS output and synchronized with the internal 1PPS at the beginning of control. Once synchronized, thereafter, a phase difference occurs between the internal 1PPS and the output 1PPS due to the drift of the oscillator, and the phase difference data is transferred to the microprocessor 118.

The temperature sensor 116 measures the temperature of the oscillator and transmits the temperature to the microprocessor 118 through the interface circuit 123, and the antenna check circuit 117 connects the GPS antenna. Monitoring status is transmitted to the microprocessor 118 through the interface circuit 123 to indicate the antenna status signal indicating whether the antenna connection is normal or open or short (short).

The time / frequency driver 122 receives a frequency from the local oscillator 112 and receives a time from a phase detection system 115 and outputs the time according to the output specification.

The D / A converter 120 and the filter 121 convert a control value of the oscillator received from the microprocessor 118 into an analog value and filter it to generate a control signal that can be used for oscillator control.

The microprocessor 118 calculates the pseudorange and pseudorange rate from each satellite using the integrated data and the measurement data inputted from the correlation system 113, and calculates the GPS satellites. It extracts data, and outputs information such as receiver's position and time through navigation algorithm. In addition, the phase detection unit 115 receives a phase difference between the internal 1PPS and the output 1PPS to predict and correct errors of time and frequency, and outputs control values of the oscillator.Non-Volatile Memory (119) The temperature control data of the oscillator and the secular data are used to determine more precise control values.

At this time, if the antenna is open or the satellite is no longer tracked or if the internal 1PPS deviates by a certain value from the relatively stable output 1PPS, the holdover control is not performed based on the internal 1PPS. At this time, the oscillator is controlled by using a holdover algorithm that utilizes only the aged and temperature characteristics of the oscillator. The control algorithm of the holdover mode will be described later.

Operating software of the GPS receiver according to the present invention

The operation software of the GPS receiver or the GPS clock device using the same is based on a task switching operating system (OS), and is mainly composed of an interrupt routine (ISR) and a multitasking routine. The tasking routine is based on a TIC that occurs every 100ms, and there are 100ms and 1s tasks.

The interrupt routine has priority over the multitasking routine and is performed by an interrupt signal generated every 900 ms in the correlation system. 8 illustrates the operation of each task by the multitasking routine in order of priority.

The actions of each prioritized task are as follows:

1.Measurement data is collected by a measurement task and a local carrier frequency is updated (S81).

The navigation data is processed by the navigation task to find the navigation solution and update the position. However, in the position hold mode in which the position calculated for one hour is averaged and the receiver is determined as the average position due to the nature of the GPS clock core, the position is no longer updated (S82).

3. If GPS Locked Condition is satisfied by Control Task, GPS Locked Control is performed. Otherwise, Holdover Mode is used to consider the oscillator's temperature characteristics and Aging characteristics. Control is performed (S83, S84, S85). The GPS locking condition is a case where the number of satellites being tracked is one or more and the internal 1PPS is determined to be normal by an enhanced T-RAIM algorithm.

4. The display task (Display Task) transmits the monitoring data through the UART (S86).

5. It is a conversation task (Diag. Task) to get the information related to the temperature of the oscillator and the antenna connection state and processing. In addition, it checks the command input by the user and if the event is found and stores the contents in the flash memory (S87).

6. Process and store the navigation message information received by the processing task (ProcSbf.Task) (S88).

7. Assign task (Alloc.Task) serves to allocate the GPS satellites (S89).

9 illustrates each operation by the interrupt routine in chronological order.

The interrupt routine has priority over the multitasking routine and is executed by the interrupt signal generated every 900 ms in the Correlation System. The operation of each step of the interrupt routine will be described in detail as follows.

1. The correlation value of the PRN code is integrated in the Correlation System for one period (1 ms) of the code. Therefore, the microprocessor is treated as an interrupt that occurs every 900 ms because it must read the integral value at a period not exceeding 1 ms. The integral value input from each channel is used to update the carrier tracking loop and the code tracking loop, which may be an essential part for tracking satellites (S91).

2. In order to generate the internal 1PPS synchronized to the UTC, the period of the TIC, which is a basic clock required for generating the internal 1PPS, is adjusted, and the internal 1PPS is output at an appropriate timing (S92).

3. After the internal 1PPS is generated, the TOD is updated and output at an appropriate timing (S93).

4. The control task reads the control value (DAC) of the updated oscillator and performs PWM (Pulse Width Modulation) and outputs it (S94).

The control value of the oscillator output from the microprocessor is input to the D / A converter to generate the control voltage of the oscillator. The D / A converter used in the present invention takes 16-bits of serial data as input. Thus, the range of oscillator control values is an integer from 0 to 65535. However, the present invention has devised a method that can make the step of the control value to 0.01 for more precise control. Therefore, the microprocessor transfers the control value to the D / A converter every 10ms. If it outputs the control value of 30000.46, the method of software pulse width modulation (Software PWM) outputs 30000 value for 540ms and 30001 value for 460ms. Was used. However, since this method may bring about a result of lowering the stability of the oscillator, the present invention uses an application method of PWM to regularly distribute evenly by dividing by 10ms instead of continuously outputting the time of 540ms and 460ms.

5. If the TIC is generated, it stores the task in progress and executes the highest priority task (S95).

Oscillator Control Action

10 is a transition diagram illustrating an oscillator control operation of a GPS receiver or a GPS clock device according to the present invention.

According to FIG. 10, a GPS locked mode is a case where a GPS satellite is normally tracked and controls an oscillator based on an internal 1PPS. When the system is powered up and the satellite is normally tracked and 3D-Fixed, the system performs automatic site surveying for a period of time, eg 1 hour, and calculates the average of the collected locations. Position hold mode to fix the position of the system. This is to obtain more accurate visual information by accurately determining the position. However, if the number of visible satellites is less than 3 due to poor reception status of GPS satellite signals during the site survey, it is possible to quickly fix the position to the surveyed position until that time. It is desirable to operate in a guaranteed Quick Position Hold Mode.

On the other hand, holdover mode is applied when a single GPS satellite cannot be tracked, or when an internal 1PPS differs from the output 1PPS by more than a threshold value, and in holdover mode, stored aging information and Only the temperature characteristic information is used to control the oscillator.

Recovery Mode performs the task of checking the satellite again in Holdover Mode, synchronizing the output 1PPS with the internal 1PPS, and automatically switching to GPS Locked Mode. Do it.

The microprocessor performs the control operation as shown in FIG. 11 in the GPS lock mode.

Referring to the operation of the microprocessor in the GPS lock mode, the microprocessor receives a time interval value every second from the phase detector and averages the signals for 5 seconds, 20 seconds, and 50 seconds according to the control period (S111 to S113). ). In consideration of the frequency characteristics of the oscillator, the control is performed initially at a short cycle, and when the time of about 1 hour has elapsed, the control cycle is extended to ensure the accuracy and stability of the frequency. When the average value of the interval is calculated, the Kalman Filter is used to predict the error of time and frequency, and the temperature coefficient of the oscillator is predicted to determine the control value (control voltage) and perform the control (S114 to S117).

In addition, the microprocessor performs the control operation as shown in FIG. 12 in the holdover mode.

Looking at the microprocessor's operation in holdover mode, the microprocessor has to adjust the DAC value and oscillator surface temperature or current consumption of the oscillator along with the time to control the oscillator during the GPS lock mode prior to the holdover mode. Record once every control cycle. When the changeover to the holdover mode is performed, the age coefficient and temperature coefficient (frequency change rate of the oscillator according to temperature) of the oscillator are estimated using the least square algorithm using the least square algorithm (S121).

The local oscillator generally exhibits nonlinear frequency output change characteristics with respect to temperature change, and thus, the present invention applies this nonlinear characteristic to a table and applies the oscillator control.

In the holdover mode, the age coefficient and the temperature coefficient are estimated all at once or only the age coefficient is estimated. In addition, the suitability of the estimated Aging coefficient and the temperature coefficient are judged at the same time, and when it is properly estimated, the elapsed time (dt) and the temperature change (dT) are measured to obtain an increment of the DAC (PRE_dDAC). If it is determined that the temperature coefficient is incorrectly estimated in the suitability judgment, the increment (PRE_dDAC) of the DAC is obtained using only the Aging coefficient and the elapsed time dt (S122 to S124).

 To control the D / A converter by adding the previously obtained increment (PRE_dDAC) to DAC_k-1 in all control periods and obtaining the current DAC_k, and adding TEMP_DAC which is mapped with the current temperature from the temperature characteristic table of the oscillator. A CONTROL DAC value as a control value for the control is obtained (S125).

Internal 1PPS monitoring operation

To provide time and frequency with atomic clock accuracy and stability, the accuracy of the internal 1PPS must be guaranteed. In the system developed through the present invention, the T-RAIM algorithm and the method using the frequency output of the oscillator having high short-term stability are used to monitor the internal 1PPS. FIG. 13 illustrates an operation method of monitoring an internal 1PPS when an exceptional problem occurs in GPS satellites or an exceptional change in the surrounding environment of the antenna.

Referring to FIG. 13, first, a time interval between an internal 1PPS and an output 1PPS generated by dividing a frequency of an oscillator having high short-term stability is measured every second and averaged for 10 seconds (S131). If the average value has a value of 300 ns or more, it is determined whether the T-RAIM algorithm can be applied (S132, S133). The condition is that the position of the system must be fixed first, the number of satellites to be tracked must be 8 or more, and the pseudorange residual must be 300ns or more. If such a condition is satisfied, the satellite in error can be found and removed (S134). If the above conditions are not satisfied, the oscillator control mode is changed to the holdover mode (S135).

After that, the time interval is continuously monitored in the same manner, and when the time interval is less than 300ns, the control mode of the oscillator is changed again to the GPS locked mode (S136 to S140). ). If it keeps more than 300ns, check if T-RAIM algorithm application condition is satisfied again. If it is satisfied, find and remove the satellite that has error and change it to GPS lock mode. Otherwise, continue to set the time interval. Monitor and maintain Holdover Mode.

Configuration of GPS Clock Device According to the Present Invention

An example of the configuration of a GPS clock device using a GPS receiver according to the present invention for controlling a local oscillator is shown in FIG. 14.

First, a GPS clock device having a redundancy function according to the present invention comprises two GPS clock units (A and B) 140, and each GPS clock unit is a GPS receiver according to the present invention as shown in FIG. Receiver controlling Local Oscillator (141), Frequency Synthesizer (142), Redundancy Interface (143) for exchanging diagnostic data with other GPS clock units, Output Driver (144) It is configured by. In addition, if necessary, it may further include a divider 145 for generating 1PPS2S.

The operation of each component is as follows.

The GPS receiver 141 according to the present invention for controlling a local oscillator supplies a reference frequency (10 MHz) to a frequency synthesizer (142) and outputs a signal for initializing a PLL inside the frequency synthesizer (Frequency Synthesizer). The frequency of the oscillator (10MHz), the output 1PPS, the output of the TOD is transmitted to the output driver (Output Driver). In addition, the redundancy interface 143 transmits the self-diagnosis result of the GPS clock unit to the relative GPS clock unit, receives the diagnosis result of the relative GPS clock unit, and outputs the output driver 144 according to the diagnosis result. It will play a role of enabling or disabling.

The frequency synthesizer 142 receives a reference frequency (10 MHz) from a GPS receiver controlling a local oscillator, generates a necessary system clock, and generates 1PP2S through a divider 145. The generated system clock and 1PP2S are output through the output driver 144.

When a power is applied to the GPS clock device, an output driver of one of the GPS clock units is enabled and the other is disabled. If the output driver of one GPS clock unit (Clock A) is enabled, the other GPS clock unit (Clock B) tracks the frequency of the GPS clock unit A to generate the frequency and time of the same phase. . If a problem is diagnosed in the software or hardware of the GPS clock unit A, the output driver of the GPS clock unit A is deactivated, and at the same time, the output driver of the other GPS clock unit B is activated. The frequency and time outputs are switched in such a redundant manner so that a function can be performed without a problem even when a GPS clock unit fails.

Of course, a simple GPS clock device having no redundancy function may be configured to include a frequency synthesizer for generating a predetermined time / frequency signal in addition to the GPS receiver according to the present invention by receiving time / frequency information from the GPS receiver. Could be

FIG. 15 is a view illustrating a comparison between a GPS clock device using a conventional GPS receiver and a GPS clock device using a GPS receiver according to the present invention. The block on the left shows a GPS clock device 150 according to a conventional method. The block shows a GPS clock device 150 'in accordance with the present invention.

In the case of a GPS clock device having a conventional GPS receiver for vision only, in addition to a GPS receiver having an oscillator, a storage unit and a microprocessor, a microprocessor, a storage unit (not shown) and an oscillator (control unit) for a separate GPS clock core are provided. Since the device is complicated and the manufacturing cost is increased by additionally providing components, the GPS clock device 150 'according to the present invention has a GPS having a local oscillator which can be precisely controlled according to the present invention. In addition to the receiver, only the necessary components such as a frequency synthesizer and a redundant interface can simplify the device.

FIG. 16 is a hardware configuration diagram of a conventional GPS clock core using a separate time-only GPS receiver, and includes a GPS antenna, a digital signal processor (DSP) having a self-oscillator, a GPS receiver controller, and a RAM. In addition, it is provided with a GPS receiver for vision only, which is composed of a flash memory, an antenna check circuit, and the like, and further includes a GPS clock core controller, a clock core flash memory and a RAM, and a clock core oscillator. In this case, the control unit of the GPS receiver simply serves to pass the frequency or time data calculated from the GPS signal to the control unit for the clock core, and the execution of the algorithm for precise time control is performed by a separate control unit for the clock core and the flash memory (or RAM). Thus, it can be seen that multiple components are redundantly consumed, thereby reducing the efficiency of the system.

In contrast, FIG. 17 is a hardware configuration diagram of a GPS receiver having a precisely controllable local oscillator according to the present invention. Compared with the conventional GPS clock core of FIG. 16, a plurality of components such as an oscillator, a controller, and a storage unit are integrated. It can be seen that the structure is much simpler.

FIG. 18 is a hardware configuration diagram of a signal processing unit (processing unit) of a GPS receiver having a local oscillator which can be precisely controlled according to the present invention. It consists of processor, MPC, internal RAM, PLC, RTC, GPIO, etc.

19 is a block diagram of the hardware constituting the FPGA of the GPS receiver having a local oscillator which can be precisely controlled according to the present invention. The FPGA shown in FIG. 17 is an antenna for transmitting a 10 MHz counter and an antenna open / short detection signal. It consists of a check interface, a temperature sensor interface for transferring temperature data of the oscillator, a PLL interface, a lead / right interface, a diagnostic indicator, and a 1PPS generator.

20 is a software configuration diagram of a GPS receiver having a precisely controllable local oscillator according to the present invention, which is a bit and frame synchronization module for synchronizing accumulated data, an FLL or PLL module as a carrier tracking loop, and a DLL as a code tracking rope. Modules, pseudorange and pseudorange ratio acquisition modules, holdover control algorithm modules, oscillator control modules, time / frequency error prediction modules, TOD generation modules, navigation solution calculation modules, satellite data extraction modules, and more.

The above description is merely illustrative of the present invention, and those skilled in the art to which the present invention pertains may various modifications without departing from the essential characteristics of the present invention. Accordingly, the embodiments disclosed herein are not intended to limit the present invention but to describe the present invention, and the spirit and scope of the present invention are not limited by these embodiments. It is intended that the scope of the invention be interpreted by the following claims, and that all descriptions within the scope equivalent thereto shall be construed as being included in the scope of the present invention.

The GPS receiver or GPS clock device according to the present invention can supply time and frequency that can replace the existing GPS clock device having a separate local oscillator and microprocessor in addition to the GPS receiver by directly controlling the local oscillator of the GPS receiver. have.

Therefore, the conventional GPS clock device has solved many disadvantages by using a separate GPS receiver.

First, the GPS baseband process portion and the oscillator control process portion are integrated to further improve the system's utility and economics.

Second, since the information supplied to the GPS clock device or the GPS clock core is limited in most visual GPS receivers, the GPS navigation message information and the like cannot be shared and processed, whereas the system proposed by the present invention solves this problem. It can be widely used in applications.

Third, the existing GPS clock device or clock core can have a fatal effect on the control of the oscillator when the receiver's 1PPS is momentarily out of UTC in an environment where satellite tracking is unstable. One internal 1PPS monitoring algorithm can be applied to ensure highly stable visual information.

Fourth, since the oscillator of the GPS receiver is directly controlled, the clock error in the navigation algorithm is minimized to ensure more accurate position and visual information.

In conclusion, when developing an embedded application system, it is possible to further improve the utility and economic efficiency of the system by using a GPS chip set including a GPS receiver function that can be precisely controlled, rather than using an already constructed GPS receiver.

1 is a block diagram of a conventional GPS receiver,

2 is a view showing the structure of a conventional GPS clock core (GPS Clock Core),

3 is a frequency measurement result of the GPS clock core, specifically, a measurement result graph for accuracy;

4 is a frequency measurement result of the GPS clock core, specifically, a measurement result graph for stability;

5 is a time measurement result of the GPS clock core, specifically, a measurement result graph for accuracy;

6 is an oscillator control block diagram of a GPS clock core using a general GPS receiver;

7 is a block diagram of a GPS receiver having a precisely controllable local oscillator according to the present invention;

8 is a flowchart illustrating operations by a multitasking routine of a GPS receiver or a GPS clock device according to the present invention;

9 is an operation flowchart by an interrupt routine of a GPS receiver or a GPS clock device according to the present invention;

10 is a transition diagram of an oscillator control operation of a GPS receiver or a GPS clock device according to the present invention;

11 is a flowchart illustrating an oscillator control in a GPS locked mode of a GPS receiver or a GPS clock device according to the present invention;

12 is a flowchart illustrating an oscillator control in a holdover mode of a GPS receiver or a GPS clock device according to the present invention;

13 is a flowchart illustrating an internal 1PPS monitoring operation of a GPS receiver or a GPS clock device according to the present invention;

14 is a block diagram of a GPS clock device using a GPS receiver having a local oscillator which can be precisely controlled according to the present invention;

FIG. 15 is a view showing a comparison of the configuration of a GPS clock device using a GPS receiver according to the present invention and a GPS clock device using a conventional GPS receiver; FIG.

16 is a hardware configuration diagram of a conventional GPS clock core using a separate time-only GPS receiver;

17 is a hardware configuration diagram of a GPS receiver having a local oscillator capable of precise control according to the present invention;

18 is a hardware configuration diagram of a signal processing unit (processing unit) of the GPS receiver having a local oscillator capable of precise control according to the present invention;

19 is a configuration diagram of hardware constituting an FPGA of a GPS receiver having a local oscillator which can be precisely controlled according to the present invention;

20 is a software configuration diagram of a GPS receiver having a local oscillator capable of precise control according to the present invention.

Claims (16)

One or more GPS signal receiving antennas; A down converter for converting the GPS signal received from the antenna into an intermediate frequency band signal; A local oscillator precisely controlled by a predetermined signal processor; A correlator unit which removes the carrier of the intermediate frequency band signal from the downconverter, extracts the PRN code included in the GPS signal, performs a correlation with the corresponding code generated by itself, and delivers the generated integrated data to the signal processor. (Correlation System); A reference time generator (1PPS Generator) for generating an internal reference time (1PPS) signal based on the data from the correlator; A phase detection unit detecting a phase difference between the output 1PPS signal generated by dividing the output of the local oscillator and the internal 1PPS signal from the reference time generator; A temperature sensor measuring a surface temperature of the local oscillator and calculating a temperature coefficient of the local oscillator using temperature characteristic data; An antenna check circuit for checking a connection state of the antenna; Receiving one or more of the phase difference data from the phase detection unit, the temperature coefficient data from the temperature sensor, and the antenna connection state data from the antenna check circuit to check whether there is an abnormality, and output a control value of the local oscillator; And a navigation solution calculation function for calculating a pseudo distance from the satellite using integrated data and measured data from the correlator and calculating a navigation solution including a current position and time using a least-squares navigation algorithm. A signal processor having a function of precisely correcting the frequency and visual error of the local oscillator using the navigation solution and the control value of the local oscillator; And It includes a storage unit for storing information about the control algorithm of the local oscillator, The local oscillator is a controllable oscillator (oscillator) including an Oven Controlled Crystal Oscillator (OCXO), wherein at least one of temperature and menopausal characteristic data unique to each oscillator (oscillator) is stored in the storage unit. GPS receiver having a precisely controllable local oscillator. delete delete The method of claim 1, The signal processor estimates the time and frequency error of the local oscillator using the phase difference information between the internal 1PPS signal and the output 1PPS signal input from the phase detector, calculates and outputs the control value of the local oscillator, and outputs the control value. In the calculation, a precision controllable local oscillator having at least one of temperature characteristic data and age characteristic data of the corresponding local oscillator stored in the storage unit is used to calculate the control value more precisely. GPS receiver. The method of claim 1, The signal processor localizes to the holdover mode when at least one of a GPS signal is not received, an antenna failure occurrence signal is input from the antenna check circuit, and an internal 1PPS is greater than or equal to the output 1PPS. The oscillator control value is calculated, and in the holdover mode, the temperature characteristic data and / or aging of the local oscillator stored in the storage unit, instead of the GPS lock mode for calculating the control value using the internal 1PPS signal calculated from the received GPS signal. A GPS receiver having a precise controllable local oscillator, characterized in that the control value of the local oscillator is calculated using only the characteristic data. The method of claim 1, The signal processing unit calculates the local oscillator control value by operating in a GPS lock mode when a signal is received from at least one GPS satellite. In the GPS lock mode, when three or more GPS satellite signals are received for a predetermined time or more, a position hold mode for determining a position of the current GPS receiver based on the position information for a predetermined time and calculating a control value (Position Hold Mode) Wow, When signals from less than three GPS satellites are received, calculating the control value by one or more of the Quick Position Hold Modes, which determine the receiver position at that point and then calculate the control value. GPS receiver with precision controllable local oscillator. The method according to claim 5 or 6, In the GPS lock mode, the signal processor receives a time interval value between an internal 1PPS signal and an output 1PPS signal at a predetermined time from a phase detector and calculates a section average value for a predetermined time period according to a control period. And Kalman Filter to predict the error of time and frequency, calculate the temperature coefficient of the oscillator, and use the predicted error value and the calculated temperature coefficient to control precisely. GPS receiver with local oscillator. The method of claim 7, wherein GPS receiver having a precisely controllable local oscillator characterized in that the control is performed in a short period at the beginning of the control in consideration of the frequency characteristics of the local oscillator and the control period is extended after a predetermined period of time to ensure the accuracy and stability of the frequency. . The method of claim 5, In the holdover mode, the signal processor records the control value for controlling the oscillator, the current surface temperature of the oscillator, or the current consumption of the oscillator once per control period with the corresponding time during the GPS lock mode before the holdover mode. In the transition to the holdover mode, at least one of the estimated age coefficient and the temperature coefficient is estimated after estimating the aging coefficient and the temperature coefficient of the oscillator using the least square algorithm using the recorded square algorithm. GPS receiver having a precisely controllable local oscillator, characterized in that for calculating the control value of the oscillator. The method of claim 9, The control value in the holdover mode determines the suitability of the estimated aging coefficient and the temperature coefficient, and if appropriately requested, one or more of the elapsed time (dt), the temperature change (dT), and the aging coefficient of the local oscillator. To obtain an increment (PRE_dDAC) of the control value (DAC), obtain the current control value (DAC_k) by adding the increment of the control value with the control value (DAC_k-1) in the previous control period, and store the data in the storage unit. GPS receiver having a precisely controllable local oscillator, which is calculated by adding a temperature characteristic control value increment (TEMP_DAC) mapped to the temperature of the current local oscillator from a temperature characteristic table of the local oscillator. . The method of claim 1, GPS having a precisely controllable local oscillator further comprising a D / A converter and / or filter means for converting and filtering the local oscillator control value from the signal processor into an analog signal to generate an analog control signal. receiving set. The method of claim 11, When the analog control signal S_con is greater than or equal to N and less than N + 1, the signal processor outputs a control value of N for (N + 1-S_con) time and outputs a control value of N + 1 to (S_con-N). A GPS receiver having a precisely controllable local oscillator for outputting as much as time, but using a software pulse width modulation method that divides each control value into short cells and distributes the result evenly. One or more GPS signal receiving antennas; A down converter for converting the GPS signal received from the antenna into an intermediate frequency band signal; A local oscillator precisely controlled by a predetermined signal processor; A correlator unit which removes the carrier of the intermediate frequency band signal from the downconverter, extracts the PRN code included in the GPS signal, performs a correlation with the corresponding code generated by itself, and delivers the generated integrated data to the signal processor. (Correlation System); A reference time generator (1PPS Generator) for generating an internal reference time (1PPS) signal based on the data from the correlator; A phase detection unit detecting a phase difference between the output 1PPS signal generated by dividing the output of the local oscillator and the internal 1PPS signal from the reference time generator; A temperature sensor measuring a surface temperature of the local oscillator and calculating a temperature coefficient of the local oscillator using temperature characteristic data; An antenna check circuit for checking a connection state of the antenna; Receiving one or more of the phase difference data from the phase detection unit, the temperature coefficient data from the temperature sensor, and the antenna connection state data from the antenna check circuit to check whether there is an abnormality, and output a control value of the local oscillator; And a navigation solution calculation function for calculating a pseudo distance from the satellite using integrated data and measured data from the correlator and calculating a navigation solution including a current position and time using a least-squares navigation algorithm. A signal processor having a function of precisely correcting the frequency and visual error of the local oscillator using the navigation solution and the control value of the local oscillator; And It includes a storage unit for storing information about the control algorithm of the local oscillator, The local oscillator is a controllable oscillator (oscillator) including an Oven Controlled Crystal Oscillator (OCXO), a GPS receiver in which one or more of temperature and menopausal characteristic data unique to each oscillator (oscillator) is stored in the storage unit; A frequency synthesizer that receives a reference frequency from the GPS receiver and generates and provides a clock signal, a frequency signal, or a time signal of a required specification. GPS clock device using a GPS receiver having a precise controllable local oscillator comprising a. delete Redundant GPS clock device consisting of two or more GPS clock units, One or more GPS signal receiving antennas; A down converter for converting the GPS signal received from the antenna into an intermediate frequency band signal; A local oscillator precisely controlled by a predetermined signal processor; A correlator unit which removes the carrier of the intermediate frequency band signal from the downconverter, extracts the PRN code included in the GPS signal, performs a correlation with the corresponding code generated by itself, and delivers the generated integrated data to the signal processor. (Correlation System); A reference time generator (1PPS Generator) for generating an internal reference time (1PPS) signal based on the data from the correlator; A phase detection unit detecting a phase difference between the output 1PPS signal generated by dividing the output of the local oscillator and the internal 1PPS signal from the reference time generator; A temperature sensor measuring a surface temperature of the local oscillator and calculating a temperature coefficient of the local oscillator using temperature characteristic data; An antenna check circuit for checking a connection state of the antenna; Receiving one or more of the phase difference data from the phase detection unit, the temperature coefficient data from the temperature sensor, and the antenna connection state data from the antenna check circuit to check whether there is an abnormality, and output a control value of the local oscillator; And a navigation solution calculation function for calculating a pseudo distance from the satellite using integrated data and measured data from the correlator and calculating a navigation solution including a current position and time using a least-squares navigation algorithm. A signal processor having a function of precisely correcting the frequency and visual error of the local oscillator using the navigation solution and the control value of the local oscillator; And It includes a storage unit for storing information about the control algorithm of the local oscillator, The local oscillator is a controllable oscillator (oscillator) including an Oven Controlled Crystal Oscillator (OCXO), a GPS receiver in which one or more of temperature and menopausal characteristic data unique to each oscillator (oscillator) is stored in the storage unit; A frequency synthesizer for receiving a reference frequency from the GPS receiver and generating a clock having a required specification; A redundancy interface for transmitting and receiving self-diagnostic data of the GPS clock units; It is for outputting clock or time information to an external device, and includes an output driver which is activated or deactivated. In case of a failure of the currently active clock unit, a redundant structure GPS using a GPS receiver having a precisely controllable local oscillator, which performs a duplication operation of deactivating the output driver of the corresponding clock unit and activating the output driver of the other clock unit. Clock device. The method of claim 15, The GPS clock device further includes a divider for outputting a 1PPS2S signal based on an input from the frequency synthesizer, wherein the GPS clock device has a redundant structure using a GPS receiver having a precisely controllable local oscillator. GPS clock device.