KR100521320B1 - Non volatile memory device and program method thereof - Google Patents

Abstract

A nonvolatile memory device according to the present invention comprises: at least one memory cell that is electrically erasable and programmable having a control gate and a floating gate; A high voltage generation circuit that receives information informing a start voltage and its stepping voltage to generate a high voltage at a relatively high level relative to a power supply voltage to be applied to the control gate during a program operation; A high voltage index register having an initialization terminal for receiving the high voltage generated in the high voltage generating circuit and providing information to the high voltage generating circuit for adjusting the start voltage and its stepping voltage; And a control circuit for providing an initialization signal to an initialization terminal of the high voltage index register.

Description

Nonvolatile memory device and its program method {NON VOLATILE MEMORY DEVICE AND PROGRAM METHOD THEREOF}

The present invention relates to a semiconductor memory device, and more particularly, to a nonvolatile memory device capable of storing multi-bit data in one memory cell and a program method for reducing a test time thereof.

The rapid development of semiconductor technology has resulted in very high integration of semiconductor integrated circuits, especially in the field of memory devices with electrically erasable and programmable read only memory (EEPROM) cell arrays. The growth was remarkable. As a result of the ultra-high integration of memory devices, more inspection time (hereinafter referred to as test time) is required to inspect defects of the memory cell array.

In general, the inspection of the EEPROM cell has been mainly to write or read the actual data directly to the memory cell to determine whether the failure. In addition, to expand the memory capacity, Flash EEPROM products have developed a multi-level flash EEPROM (hereinafter referred to as MLC) that can store multi-level data. Such MLC is a technology in which one memory cell stores at least two bits of data information so as to change the data of the memory cell by causing the cell's threshold voltage (hereinafter, Vth) to be equal to or greater than a predetermined voltage.

Figure 1 shows the threshold voltage distribution corresponding to each state for NAND-type MLC with four possible states. As shown in FIG. 1, since the MLC stores at least two bits of data information, verification must be made whether or not the cell threshold voltages for each cell state are correctly distributed. When MLC is tested by performing a write / read operation on each data state that a memory cell can have by using a single-level cell test method, the test time is much longer than that of a single-bit cell.

In general, in the case of a NAND flash EEPROM, erasing means that a high voltage is applied to the memory cell to have a negative threshold voltage. In FIG. 1, an "11" state is called an erased state. In addition, the program means that a high voltage is applied to the memory cell to have a positive threshold voltage. In FIG. 1, the states "10", "01", and "00" are referred to as programmed states. In order to put the desired data into a programmed state, the cell is always ready to be in an erased state with an "11" state, and the program is in the erased state with one of the "10", "01", and "00" states. Proceed.

FIG. 2 is a flowchart illustrating a test program method using a test method of a conventional single-level MLC in the case of sequentially testing "10"-> "01"-> "00" with respect to a NAND flash MLC. FIG. 3 is a diagram of a test result based on the threshold voltage distribution position of a memory cell according to the flowchart of FIG. 1. 4 is a diagram illustrating a relationship between a program voltage and a threshold voltage according to a test program method of the related art.

In FIG. 2, when programming the "01" state, it is understood that the memory cell in the "01" state is erased to the "11" state before programming the "01" state. It can be seen that the cells in the "00" state are erased to be erased in the "11" state. Even when programming the "00" state, it can be seen that the threshold voltage of the cell is always erased, that is, the "11" state, and then reprogrammed, such as programming "01".

As can be seen in Figure 3, when programming the "01" state or "00" state "11"-> "10"-> "01" or "11"-> "10"-> "01"-> " The final programming process through the sequential programming process such as 00 "can be seen that the increase of the program time during the test results in an increase of the total test time.

In particular, the program time of "11"-> "10" is about 1.2ms in the case of NAND flash MLC, and the program time of "10"-> "01" and "10"-> "00" is about 0.15ms. 11 "->" 10 "takes up 80% of the total program time. Eventually you will program the "00" state.

In addition, the relationship between the program voltage Vpgm necessary to shift the threshold voltage of the cell in each state is shown in FIG. 4. In FIG. 4, when programming each state, the program voltage is continuously increased from the start voltage until the program is completed, and then the program voltage level is lowered back to the initial start voltage when the program is completed.

When the MLC is tested by the conventional single level cell test method, the test time is inevitably increased due to repeated erase and sequential programs.

Accordingly, an object of the present invention is to provide a nonvolatile memory device and a test program method thereof for reducing test time in a multi-level cell which performs a program sequentially in a test mode.

(Configuration)

According to one aspect of the present invention for achieving the above object, a nonvolatile memory device comprising: at least one electrically erasable and programmable memory cell having a control gate and a floating gate; The memory cell stores at least one multi-level data and has one of the possible threshold voltages representing the multi-level data; A high voltage generation circuit that receives information informing a start voltage and its stepping voltage to generate a high voltage at a relatively high level relative to a power supply voltage to be applied to the control gate during a program operation; A high voltage index register having an initialization terminal for receiving the high voltage generated in the high voltage generating circuit and providing information to the high voltage generating circuit for adjusting the start voltage and its stepping voltage; A control circuit for providing an initialization signal to an initialization terminal of the high voltage index register; The control circuit causes the voltage information of the high voltage index register to be removed by a signal indicating an erase operation or an initialization signal for initializing the high voltage index circuit during an erase operation, and the voltage information generated in the previous step during a test mode operation. It is characterized by maintaining as it is.

In this embodiment, the control circuit comprises: a first inverter for inverting the initialization signal; A first NAND gate connected with one input terminal to an output terminal of the first inverter and the other input terminal provided with a signal indicating the test mode; A second NAND gate having one input terminal connected to an output terminal of the second NAND gate and another input terminal to which a signal for indicating an erase operation is applied; And a second inverter having an input terminal connected to the second NAND gate and an output terminal connected to an initialization terminal of the high voltage index register.

According to another aspect of the invention, at least one cell array having a plurality of memory cells arranged in rows and columns; Each memory cell stores multi-bit data and has one of the possible threshold voltages representing the multi-bit data; A high voltage generating circuit that receives information indicative of the start voltage and its stepping voltage and generates a high voltage at a relatively high level relative to the power supply voltage to be applied to the addressed memory cell during a program operation; A high voltage index register having an initialization terminal for receiving the high voltage generated in the high voltage generating circuit and providing information to the high voltage generating circuit for adjusting the start voltage and its stepping voltage; A program method of a nonvolatile memory device comprising a control circuit for providing an initialization signal to an initialization terminal of the high voltage index register, comprising: simultaneously erasing memory cells constituting the cell array; Determining whether memory cells associated with one of the rows have a threshold voltage corresponding to an erased state; Programming to have a threshold voltage of a next state corresponding to an erased state among the possible threshold voltages of the memory cells corresponding to the one row; The voltage information on the program voltage applied to the memory cells corresponding to the one row in the program step is determined in the high voltage index register while determining whether the memory cells corresponding to the one row have a desired threshold voltage. And storing the same.

In this embodiment, the program step corresponding to the possible threshold voltages and the program verifying step are sequentially performed according to the voltage information on the program voltage of the previous step stored in the high voltage index register.

(Action)

By such an apparatus and method, in the normal operation mode, the program voltage is normally supplied to the selected cell, and in the test operation mode, the previously programmed voltage information is stored and then used in the next program step to reduce the overall test time. have.

(Example)

Hereinafter, reference will be made in detail with reference to FIGS. 5 to 8 according to an embodiment of the present invention.

In the following description, specific details are set forth by way of example and in detail in order to provide a more thorough understanding of the present invention. However, for those skilled in the art, the present invention may be practiced only by the above description without these details.

The present invention is to reduce the test time by effectively testing a multi-level EEPROM cell, and to erase the cell array at the same time or to erase a specific block to the cells of one cell or page unit (word line unit) After verify-> program is executed, the verification-> program is repeatedly executed for the next cell or page.

5 is a flowchart illustrating a test program method according to an exemplary embodiment of the present invention, and FIG. 6 is a diagram illustrating a shift in the threshold voltage according to the test program method according to the present invention. 7 is a view showing a relationship between a program voltage and a threshold voltage according to the test program method of the present invention.

5 illustrates an example of erasing a specific memory block and programming a page unit. That is, program the "01" state and program the "10" state. When the "01" status completes the program, the "01" status is verified and the "00" is programmed again. When the program ends, the "00" is programmed. When the program ends, the "00" is verified. Again, test in the same way, based on the aforementioned method.

As can be seen in FIG. 5, it can be seen that after the erase operation is performed, the threshold voltage is continuously programmed to a higher voltage. Table 1 below compares the test items of the NAND flash MLC according to the conventional single bit test method and the test method performed in the present invention.

TABLE 1

In Table 1, we can see that the erase and "11"-> "10" programs are reduced from 3 times to 1 times. Table 2 below is a comparison between the conventional method and the test time of the present invention for NAND flash MLC (density: 64M bits / block number: 1K / page number: 16K / page size: 512 bytes).

TABLE 2

Table 2 shows that program time for the "10" state contributes the most to the total test time. Therefore, reducing the test time of "11"-> "10" is the biggest factor.

Referring to Figure 7, according to the test program method according to the present invention, it can be seen that the verification and the program is continuously performed in the middle of the program in progress. It can be seen from FIG. 7 that a circuit is required that maintains a level of program voltage that can program the next " 01 " state during read and program after completion of the program of the " 01 " state. In addition, it can be seen that when programming from the "01" state to the "00" state, a circuit for maintaining the program voltage level is required.

8 is a block diagram illustrating a configuration of a nonvolatile memory device for maintaining a program voltage level according to the present invention.

Referring to FIG. 8, a nonvolatile memory device according to the present invention includes an array 100 having at least one EEPROM cell M1 for storing multi-level data, a program voltage generator circuit 101, and a control circuit 102. ) And program index register 103. The program voltage generator circuit 101 is a high voltage generator that is well known to those skilled in the art. The program voltage index register 103 is a register which functions to adjust the start voltage and the stepping voltage of the program voltage generation circuit 101. The program voltage index register 103 is initialized after programming desired data in normal operation to indicate the level of the initial program start voltage.

In the present invention, the control circuit 102 supporting the test mode is adopted in the program voltage index register 103 so that the next data is not initialized when the test algorithm of the present invention is applied in the test mode. The program voltage level is maintained at the time of programming. When the erase operation is performed, the program voltage index register 103 is initialized irrespective of the test mode, so that the program can be started from the first " 10 " state after the erase operation.

As described above, employing a circuit for reducing test time for a multi-level cell that sequentially performs a program, and applying the test program method according to the present invention can reduce the test time compared to the conventional test method It can be seen that the larger the memory capacity, the greater the reduction in test time.

In the above, the configuration and operation of the circuit according to the present invention are shown in accordance with the above description and drawings, but this is merely an example, and various changes and modifications can be made without departing from the spirit and scope of the present invention. Of course.

As described above, test time for multi-level cells can be shortened.

1 is a view showing a distribution of possible threshold voltages of a memory cell storing multi-level (or multi-bit) data;

2 is a flowchart showing a test program method according to the prior art;

3 is a view illustrating a shift in a threshold voltage according to a test program method of the related art;

4 is a view showing a relationship between a program voltage and a threshold voltage according to a test program method of the related art;

5 is a flowchart showing a test program method according to a preferred embodiment of the present invention;

6 is a view showing a shift in the threshold voltage according to the test program method according to the present invention;

7 is a view showing a relationship between a program voltage and a threshold voltage according to the test program method of the present invention;

8 is a block diagram showing a configuration of a nonvolatile memory device according to the present invention.

* Explanation of symbols on the main parts of the drawings

100: memory cell array 101: program voltage generation circuit

102: control circuit 103: program voltage index register

Claims (4)

In a nonvolatile memory device: At least one electrically erasable and programmable memory cell having a control gate and a floating gate; The memory cell stores at least one multi-level data and has one of the possible threshold voltages representing the multi-level data; A high voltage index register for storing program voltage adjustment information for adjusting a start voltage of a program voltage and a stepping voltage of the program voltage; A high voltage generation circuit that receives the program voltage adjustment information stored in the high voltage index register and generates a high voltage at a relatively high level relative to a power supply voltage to be applied to the control gate during a program operation; A control circuit for initializing the program voltage regulation information stored in the high voltage index register; The control circuit causes the voltage information of the high voltage index register to be removed by a signal indicative of an erase operation or an initialization signal for initializing the high voltage index circuit during an erase operation, and a program voltage adjustment generated in a previous step during a test mode operation. Nonvolatile memory device, characterized in that to keep the information as it is. The method of claim 1, The control circuit includes a first inverter for inverting the initialization signal; A first NAND gate connected with one input terminal to an output terminal of the first inverter and the other input terminal provided with a signal indicating the test mode; A second NAND gate having one input terminal connected to an output terminal of the second NAND gate and another input terminal to which a signal for indicating an erase operation is applied; And a second inverter having an input terminal connected to the second NAND gate and an output terminal connected to an initialization terminal of the high voltage index register. At least one cell array having a plurality of memory cells arranged in rows and columns; Each memory cell stores multi-bit data and has one of the possible threshold voltages representing the multi-bit data; A high voltage index register for storing program voltage adjustment information for adjusting a start voltage of a program voltage and a stepping voltage of the program voltage; A high voltage generation circuit that receives the program voltage adjustment information stored in the high voltage register and generates a high voltage at a relatively high level relative to a power supply voltage to be applied to the control gate during a program operation; A program method of a nonvolatile memory device including a control circuit for initializing the program voltage regulation information stored in the high voltage index register. Simultaneously erasing memory cells constituting the cell array; Determining whether memory cells associated with one of the rows have a threshold voltage corresponding to an erased state; Programming to have a threshold voltage of a next state corresponding to an erased state among the possible threshold voltages of the memory cells corresponding to the one row; The voltage information on the program voltage applied to the memory cells corresponding to the one row in the program step is determined in the high voltage index register while determining whether the memory cells corresponding to the one row have a desired threshold voltage. And storing the program. The method of claim 3, wherein And a program step and a program verify step corresponding to the possible threshold voltages are sequentially performed according to the voltage information on the program voltage of the previous step stored in the high voltage index register.

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