CN113113072A

CN113113072A - Method for loading trim value in chip test

Info

Publication number: CN113113072A
Application number: CN202110346107.1A
Authority: CN
Inventors: 傅俊亮
Original assignee: Shanghai Huahong Grace Semiconductor Manufacturing Corp
Current assignee: Shanghai Huahong Grace Semiconductor Manufacturing Corp
Priority date: 2021-03-31
Filing date: 2021-03-31
Publication date: 2021-07-13
Anticipated expiration: 2041-03-31
Also published as: CN113113072B

Abstract

The invention discloses a method for loading trim values in chip test, which is characterized in that trim bit values are written into memory cells of a memory, and one trim bit value is written into 2 or more memory cells simultaneously when the trim bit values are written into the memory cells. When reading, all 2 or more memory cells written with the same trimming bit value are simultaneously selected, the SA is used for judging that the trimming bit value stored in all 2 or more selected memory cells is 1 or 0, and the data reading window is improved because more memory cells provide data for comparison. When the trim bit value is written into the memory cell, the inverse value of the trim bit value can be written into the memory cell at the same time, namely the inverse value of the trim bit value is written into the memory cell at the same time under the condition that the original trim bit value is 1; the mutual comparison verification after the reading can be performed when the data is read.

Description

Method for loading trim value in chip test

Technical Field

The invention relates to the field of semiconductor integrated circuit testing, in particular to a chip testing method, and specifically relates to a method for loading trim values in chip testing.

Background

When testing the SONOS EEPROM or Flash chip, the dac value of the analog quantity is always scanned until the appropriate dac value is found, namely Trimming test. The adopted method is that the dac value scanning mode of each test chip is uniformly scanned from 0 to the tail value. The chip IP evaluation usually needs to set the value of the personalized trim at a high temperature at normal temperature or low temperature, or set the value of the personalized trim at the normal temperature at the high temperature or low temperature, so as to evaluate the influence of changing the temperature on the product performance. However, since the individual IP is separated from the flash, there is no register for storing the personalized trim value, and it is long to manually set the number of dice (dies on a wafer) one by one, and for the dice on the wafer, it is necessary to debug the dice one by one and manually set the obtained dac value, then perform trimming for the next die, and then manually set the obtained dac value until the last die.

SONOS EEPROM or Flash, requires different analog quantities, such as VPOS (positive high voltage for erasure), VNEG (negative high voltage for erasure), ITIM (current for generating read timing), ISA (reference current when reading data), etc., for the erasure reading of NVM.

When a factory performs a wafer processing process, different dice (dies) on the same wafer and dice on different batches of wafers have different production processes, resulting in different analog values between the dice. If the VPOS and VNEG voltages are different, the erasing degrees of different die are increased; if the ITIMs are different, the read timing (reading time sequence) of different die is different; if there is a difference in ISAs, the difference between die increases. Too large a difference may also result in an erase-write read failure.

Therefore, the analog quantity of all die is adjustable, so that the analog quantity of different die is basically equivalent. All die have the same erase-write conditions, the memory performance will be more reliable.

One analog quantity corresponds to 3-5 bit trimming bits, and the analog quantity can be selected in 8-32 grades. Each trimming bits was determined after CP1 trim (CP, probe test) and then written to a special word line3 of SONOS NVM (SWL 3). After CP screening, SWL3 prohibits erasures and only allows reads. A one bit trim bit value is written in a SONOS cell, as shown in FIG. 1, using SA to distinguish whether a "1" cell (cell has no current) or a "0" cell (cell has current).

The SONOS IP allows entry into various modes of operation only after loading the trim value. Its mode of operation will meet the specification performance parameters (SPEC) specified in the chip manual.

The load trim value is a positive and negative trim value written in NVM SWL3, reliably read out without trim ITIM and ISA, loaded into a register of the BIST (built-in self-test technology).

Disclosure of Invention

The technical problem to be solved by the invention is to provide a method for loading trim values in a chip test, aiming at a storage unit of a memory, writing trim bit values into the storage unit of the memory:

when the trimming bit value is written, one trimming bit value is written into 2 or more storage units at the same time.

The further improvement is that the same trimming bit value is written in 2 or more memory units, when the trimming bit value is loaded and read, all 2 or more memory units written with the same trimming bit value are simultaneously selected, SA is used for judging that the trimming bit value stored in all 2 or more selected memory units is 1 or 0, and the data reading window is improved because more memory units provide data for comparison.

In a further improvement, the 2 or more memory cells are adjacent 2 or consecutive memory cells on the same column in the memory cell array.

In a further improvement, the SA is a sense amplifier for reading data from the memory.

The further improvement is that when the memory cell writes the trimming bit value, the inverse value of the trimming bit value is written, namely the inverse value of 0 is written under the condition that the original trimming bit value is 1; the mutual comparison verification after the reading can be performed when the data is read.

The further improvement is that the trimming bit value is written into the memory cell by a special word line SWL; namely, the trimming bit value is stored in the SONOS storage tube through the selection tube.

The further improvement is that when the trimming bit value in the memory cell is read out, the trimming bit value stored in the memory cell is read out by adopting a time sequence lower than the normal read-write time sequence of the memory, namely a slower time sequence, and the reading out of the original value and the inverse value is carried out simultaneously so as to carry out mutual check.

The further improvement is that the time sequence lower than the normal read-write of the memory is adopted, after the memory chip is powered on, the BIST internal register is set as a default value, all default dac values of the ITIM are set as the lowest value of 0, and the read time sequence is slowest at the moment.

The method for loading trim values in chip test changes the traditional single memory unit writing of one trim bit value into the writing of not less than 2 memory units simultaneously aiming at the writing of trim bit values in the memory chip during the test, realizes the expansion of a read window, and simultaneously can write the inverse value of the current trim bit value for mutual comparison and verification after reading, thereby improving the stability of data reading.

Drawings

FIG. 1 is a diagram illustrating a conventional method for writing a trimming bit value into a SONOS memory cell.

FIG. 2 is a schematic diagram of the present invention writing a trimming bit value into 2 adjacent SONOS memory cells simultaneously.

Detailed Description

The following detailed description of the present invention is provided with reference to the accompanying drawings, and the technical solutions in the present invention will be clearly and completely described, but the present invention is not limited to the following embodiments. It is to be understood that the embodiments described are only a few embodiments of the present invention, and not all embodiments. Advantages and features of the present invention will become apparent from the following description and from the claims. It is noted that the drawings are in greatly simplified form and that non-precision ratios are used for convenience and clarity only to aid in the description of the embodiments of the invention. All other embodiments obtained by a person skilled in the art without making any inventive step are within the scope of protection of the present invention.

It is to be understood that the present invention may be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art. In the drawings, the size and relative sizes of layers and regions may be exaggerated for clarity, and the same reference numerals denote the same elements throughout.

The method for loading trim values in the chip test is used for writing trim bit values into the memory cells of the memory. The present embodiment relates to a SONOS memory cell as shown in fig. 2, 2 memory cells are cut from a memory cell array, each memory cell includes two transistors, a select transistor and a SONOS memory tube, which are connected in series in sequence, a source-drain end of the transistor forms a bit line SL, a gate end of each transistor forms an SWL line, in the figure, the second and third memory cells are shown, and a second special word line SWL2 and a third special word line SWL3 are led out.

When the memory units are written with trimming bit values, one trimming bit value is written into 2 or more memory units at the same time. The 2 or more memory cells are adjacent 2 or continuous memory cells located on the same column in the memory cell array. This embodiment shows that 2 memory cells are written simultaneously, and the same trimming bit value is written simultaneously in the 2 memory cells, that is, in the two memory cells shown in fig. 2, the same trimming bit value is written simultaneously in SWL2 and SWL3, respectively, for example, both "1" are written. The data are written into the memory cells through special word lines SWL2 and SWL3, namely the trimming bit value is stored in the SONOS memory tube through the selection tube. Fnpass in fig. 2 is a select transistor, and the gate voltage of the select transistor is pulled high when reading data in the storage transistor. When the trimming bit value is loaded for reading, all 2 memory cells written with the same trimming bit value are simultaneously selected, the trimming bit value stored in all 2 selected memory cells is judged to be 1 or 0 by a sensing amplifier SA for data reading, and the window of data reading is improved because more memory cells provide data for comparison.

Meanwhile, a write-in value can be added, that is, when the memory cell writes a trimming bit value, the inverse value of the trimming bit value can be written in at the same time, that is, if the trimming bit value in the memory cell is "1", the inverse value of "0" is written in at the same time; thus, mutual comparison verification after reading can be performed when data is read, and whether the stored original value is correct or not can be verified through the inverse value.

When the trimming bit value in the memory cell is read out, the trimming bit value stored in the memory cell is read out by adopting a time sequence which is lower than the normal read-write time sequence of the memory, namely a slower time sequence, and the original value and the inverse value are simultaneously read out to carry out mutual verification. Generally, after the memory chip is powered on, the BIST internal register is set to a default value, and when all default dac values of the ITIM are set to the lowest level, i.e., all "0" states, the read sequence is slowest. And (3) writing trim bit values in 2 or more SONOS memory cells to have a larger current window, reading positive and negative trim bit values in the memory cells by using a relatively slow time sequence, and verifying the positive and negative values after reading.

The above are merely preferred embodiments of the present invention, and are not intended to limit the present invention. Various modifications and alterations to this invention will become apparent to those skilled in the art. Any modification, equivalent replacement, or improvement made within the spirit and principle of the present invention should be included in the protection scope of the present invention.

Claims

1. A method for loading trim value in chip test, which is to write trim bit value into the memory cell of the memory, is characterized in that:

2. The method of loading trim values in a chip test of claim 1, wherein: the same trimming bit value is written in 2 or more memory units, when the trimming bit value is loaded and read, all 2 or more memory units written with the same trimming bit value are simultaneously selected, SA is used for judging that the trimming bit value stored in all 2 or more selected memory units is 1 or 0, and the data reading window is improved because more memory units provide data for comparison.

3. The method of loading trim values in a chip test of claim 1, wherein: the 2 or more memory cells are adjacent 2 or continuous memory cells located on the same column in the memory cell array.

4. The method of loading trim values in a chip test of claim 1, wherein: the SA is a sensing amplifier for reading data in the memory.

5. The method of loading trim values in a chip test of claim 1, wherein: when the memory cell writes the trimming bit value, the memory cell also comprises the step of writing the inverse value of the trimming bit value, namely writing the inverse value of 0 under the condition that the original trimming bit value is 1; the mutual comparison verification after the reading can be performed when the data is read.

6. The method of loading trim values in a chip test of claim 1, wherein: the trimming bit value is written into the memory cell through a special word line SWL; namely, the trimming bit value is stored in the SONOS storage tube through the selection tube.

7. The method of loading trim values in a chip test of claim 5, wherein: when the trimming bit value in the memory cell is read out, the trimming bit value stored in the memory cell is read out by adopting a time sequence which is lower than the normal read-write time sequence of the memory, namely a slower time sequence, and the original value and the inverse value are simultaneously read out to carry out mutual verification.

8. The method of loading trim values in a chip test of claim 7, wherein: the adoption of the timing sequence lower than the normal reading and writing of the memory is that after the memory chip is electrified, the BIST internal register is set as a default value, all default dac values of the ITIM are set as the lowest value of 0, and the reading sequence at the moment is slowest.