KR100521121B1 - Method and apparatus for treating surface of specimen - Google Patents

Abstract

The present invention suppresses electrical damage of semiconductor elements in etching a fine pattern to a semiconductor using plasma.

For this purpose, in processing a fine pattern by plasma etching, before the charging voltage at the pattern portion reaches the dielectric breakdown voltage of the gate oxide film to which the pattern is connected, the high frequency power applied to the sample is turned off and the pattern is turned off. After the negative charging becomes sufficiently low, the high frequency power supply is turned on and these operations are repeated.

Description

Method of treatment of sample surface and treatment apparatus of sample surface {METHOD AND APPARATUS FOR TREATING SURFACE OF SPECIMEN}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a surface treatment method and apparatus, and more particularly, to a surface treatment method and apparatus suitable for etching a surface of a sample on which a semiconductor element or the like is formed using plasma.

As a conventional technique, an apparatus for etching a semiconductor element in plasma, for example, an apparatus called an ECR (electron cyclotron resonance) method will be described as an example. In this method, plasma is generated by microwaves in a vacuum vessel to which a magnetic field is applied from the outside. Due to the magnetic field, the electrons can be cyclotrond to resonate this frequency and the frequency of microwaves, thereby efficiently generating plasma. In order to accelerate the ions incident on the sample, a high frequency voltage is applied to the sample. Halogen gas, such as chlorine and fluorine, is used for the gas used as plasma.

The etching apparatus as described in Unexamined-Japanese-Patent No. 6-151360 for the purpose of aiming at high precision of such an apparatus is known. In other words, by controlling the high frequency voltage applied to the sample on / off intermittently, it is possible to increase the selectivity between Si, which is a substance to be etched, and the underlying oxide film, and to reduce the pattern dependency of the etching rate. Is disclosed.

Further, Japanese Patent Laid-Open No. 8-339989 discloses that the rest of the etch can be reduced by intermittently controlling the high frequency voltage on / off by etching the metal. In addition, Japanese Patent Laid-Open No. 62-154734 describes a method of processing an inclined portion by using an etching gas with high deposition ability and intermittently controlling high frequency voltage on / off. Japanese Laid-Open Patent Publication No. 60-50923 discloses a method of improving anisotropy by controlling high frequency voltage on / off in accordance with the introduction amount of etching gas. Further, US Pat. No. 4,5555,16 describes a method of improving in-plane uniformity of wafer speed by controlling on / off high frequency voltage applied to two of the electrodes in a three-electrode etching apparatus.

With the recent miniaturization of semiconductor devices, the problem of damage to semiconductor devices due to plasma used in the process has been increasing. Specifically, the thickness of the gate oxide film of the metal oxide semiconductor (MOS) transistor is 6 nm or less in a memory device of 256M or later. In addition to the thinning of the gate oxide film as described above, when the aspect ratio of the processing (dimension ratio in the vertical direction and the horizontal direction) increases, electrical damage caused by a phenomenon called electron shading becomes a problem. Next, the electronic shedding phenomenon will be described using the drawings. Fig. 24A is a cross sectional view of the semiconductor wafer exposed to the plasma in the etching apparatus. FIG. 24B is a view of the resist pattern of FIG. 24A seen from above.

In Fig. 24, the element isolation oxide film 204 and the gate oxide film 203 are formed on the Si substrate 205, and the po1y-Si layer 202 and the resist 201 are formed in the shape of a comb. During plasma etching, electrons 206 and ions 207 enter the sample. The ions 207 are accelerated by the high frequency voltage applied to the sample and incident perpendicularly to the surface of the sample. However, the electrons 206 are incident in a random direction due to the large random velocity component because the mass is small. For this reason, as shown in FIG. 24 (1), in the processing of a groove having a high aspect ratio, ions can reach the groove bottom 208, but electrons are mainly trapped on the sidewall of the resist 201. As a result, positive charges are accumulated in the gate oxide film 203 via the poly-Si layer 202. If the amount exceeds a predetermined value, the gate oxide film 203 causes dielectric breakdown, resulting in device defects. As described above, the phenomenon in which electrons are not supplied into the microgrooves due to the difference in directionality between ions and electrons is called electron shedding.

In addition, with the miniaturization of semiconductor devices, the processing dimensions of lines and spaces corresponding to wirings and electrodes are in a range of 0.3 m or less. As described above, in the processing of the fine pattern, the line becomes thicker gradually, and the problem that the pattern cannot be processed to the design dimension becomes remarkable. In addition to the difference in the etching speed in the microgrooves and the relatively wide portions, the difference in shape, so-called shape micro loading, becomes remarkable, which impairs processing. In addition, the thickness of the gate oxide layer of the metal oxide semiconductor (MOS) transistor is 6 nm or less in a memory device of 256M or later. In such a device, the anisotropy and the selectivity of the underlying oxide film are tradeoffs, which makes machining more difficult.

A first object of the present invention is to provide a surface treatment method and apparatus capable of preventing anisotropy improvement and a decrease in selectivity in etching fine patterns.

Another object of the present invention is to provide a surface treatment method and apparatus which can reduce damage to a semiconductor element due to this electronic shedding.

In order to achieve the first object of the present invention, in processing a fine pattern, the high frequency voltage applied to the sample is repeatedly turned on / off and the amplitude of the high frequency voltage is set sufficiently high. The gradually thickening of the line occurs because adhesion to sidewalls of the reaction product or the like becomes superior to etching. In general, when the energy of ions incident on the wafer at the time of etching is increased, etching becomes superior to adhesion to the sidewalls, so that the line thickness is improved. However, if the energy of ions is set high, the etching rate of the oxide film is increased, so that the underlying oxide film is not suitable for processing a thin gate electrode. Thus, the reduction of the selectivity was prevented by providing an off period at a high frequency voltage to reduce the number of high energy ions.

Another object of the present invention is to apply a high frequency voltage to a sample, and in etching processing of a fine pattern, the high frequency applied to the sample before the charging voltage of the pattern reaches the dielectric breakdown voltage of the gate oxide film to which the pattern is connected. This is achieved by repeatedly processing on and off of the high frequency power supply that turns off the power supply and then turns on the high frequency power supply after the charging of the pattern is sufficiently low.

EXAMPLE 1

Hereinafter, an embodiment of the present invention will be described with reference to FIGS. 1 to 12. 1 is an overall configuration diagram of a plasma etching apparatus to which the present invention is applied.

1 is an overall configuration diagram of a plasma etching apparatus to which the present invention is applied. Microwaves are introduced into the vacuum vessel 104 from the microwave power source 101 via the automatic matcher 110, the waveguide 102, and the introduction window 103.

On the other hand, an etching gas such as halogen is introduced into the vacuum vessel 104 through the gas introducing means 100, and plasma of this gas is generated by introduction of microwaves.

The material of the introduction window 103 is a material that transmits electromagnetic waves such as quartz and ceramics.

An electromagnet 105 is provided around the vacuum vessel 104. The magnetic field strength by the electromagnet 105 is set to cause resonance and frequency of microwaves. For example, if the frequency is 2.45 GHz, the magnetic field strength is 875 Gauss. Since the cyclotron motion of the electrons in the plasma is resonant with the frequency of the electromagnetic waves at this magnetic field intensity, the energy of the electromagnetic waves can be efficiently supplied to the plasma to achieve high density plasma.

The sample 107 is installed on the sample stage 108. An rf (radio frequency) bias power source 109 is connected to the sample stage 108 via a high pass filter 111 to accelerate ions incident on the sample. There is no restriction | limiting in particular in the frequency of the high frequency voltage power supply 109, Usually, the frequency is practical in the range of 20kHz to 20MHz. An insulating film 110 such as a ceramic or polymer film is provided on the surface of the sample table. Further, the DC power supply 112 is connected via the low pass filter 113 to apply a voltage to the sample stage 108 so that the sample is brought into close contact with the sample stage by electrostatic power.

FIG. 2 shows the gas pressure in the vacuum vessel 104 during the etching process by the apparatus of FIG. 1 and the operation of each of the power sources 101 and 109. As shown in (a), at the same time as the start of etching, the gas pressure is kept constant, and as shown in (b), microwave power is also supplied in stripes. On the other hand, as shown in (c), the rf bias applied to a sample is turned on / off periodically. By providing on and off periods for acceleration of ions by turning on / off the rf bias, a high energy ion section and a low energy ion section on the surface of the sample are generated. As shown in (d), etching does not proceed in the low-energy ion section, but rather, deposition of residual reaction products in gas or plasma occurs.

Next, the relationship between the frequency of the rf bias, the repetition frequency of the on / off and the etching characteristics will be described. When the rf bias is applied to the sample, a region of high electric field is generated in a thickness region of 1 mm or less from the sample surface (called a cis) where ions are accelerated. The energy distribution of the accelerated ions depends on the frequency of the rf bias. If the frequency of the rf bias is sufficiently low, the ion movement follows the change of the voltage represented by the sine wave, and therefore has the same energy as the instantaneous value Vx, and the energy distribution is very wide.

When the frequency of the rf bias increases, the ion energy cannot converge with the variation of the rf bias, so that the ion energy gradually converges to the value of the DC component Vdc of the voltage generated when the rf bias is applied. There is a transient state in between, and the frequency of about 100 KHz to several MHz has a saddle-shaped distribution having a high energy peak and a low energy peak corresponding to the amplitude (Vpp) of the rf bias. This low energy peak corresponds to the rf bias OW, i.e., the ions entering the sheath at a timing not even accelerated by the fluctuation of the rf bias. In the period where the rf bias is off, ions are not accelerated and all ions enter a region corresponding to low energy peak.

3 shows the etching progress state of the cross-sectional shape of the fine pattern by the plasma etching apparatus of FIG. Fig. 3 (1) is the initial state before etching. In FIG. 3 (2), the poly Si 301 between the lines still remains due to the phenomenon that the etching speed of the micro parts, called micro loading, is reduced when the etching of the poly Si of the wide part outside the line is finished.

At this point, the micropattern is electrically cut with other parts around it to start charging of the pattern. This transfer can be avoided by transferring the surrounding poly Si even when charged by electron shedding. Fig. 3 (3) shows the point of time when the etching is performed again and the oxide film 302 between the underlying lines is exposed. In this case, even though ions enter the groove bottom, since there is no poly Si, the oxide film is charged, but the oxide film does not flow to the gate oxide film 203, so that the deterioration of the gate oxide film after this is reduced. That is, the destruction of the gate oxide film usually occurs between FIGS. 3 (2) and 3 (3).

Fig. 4 shows the result of simulation by the calculator of the potential of the line and space pattern being cut off with the surroundings and then rising by electronic shedding. When the potential of the pattern rises and a current flows through the gate, and the total amount Q of charges passing through the oxide film exceeds the breakdown charge Qbd, the oxide film is destroyed.

5 shows the voltage-current characteristics of the gate oxide film. From the voltage Va of FIG. 5, a current called an FN tunnel current starts to flow through the oxide film, and a large current flows at the voltage Vb. Vb is referred to herein as the breakdown voltage. The increase in the pattern potential in Fig. 4 is because ions are accelerated by the application of a high frequency voltage to the sample to cause electron shedding. In order to prevent the destruction of the gate oxide film from the above, the high frequency voltage is turned off before the pattern potential Vp exceeds the breakdown voltage Vb to prevent the pattern voltage from rising. Turning off the high frequency voltage prevents ions from accelerating, so Vp decreases. If the high frequency power supply is turned on again when Vp is sufficiently lowered and then turned off before exceeding Vb, the amount of charge flowing to the gate oxide film is kept small, so that dielectric breakdown can be prevented.

6 shows the change of the pattern potential when the high frequency voltage applied to the sample is turned on / off. In addition, in order to increase the safety margin, the on / off may be performed so that Vp is 50% or less of Vb.

Since the pattern does not charge indefinitely even when a high frequency voltage is applied continuously, the pattern potential Vp is saturated at the saturation voltage Vsat where the incidence of ions and electrons is harmonized. When Vsat is smaller than the breakdown voltage Vb, the oxide film is not destroyed in a short time (several tens of ms), but is destroyed after a certain time because the current is somewhat large. In this case, the high frequency power supply is turned off before Vp becomes Vsat, and it is possible to suppress the destruction of the oxide film by repeatedly turning on after being sufficiently lowered. In addition, in order to increase the safety margin, the Vp may be turned on or off to be 50% or less of the Vsat.

The potential of the pattern is obtained by simulating or connecting the probe to the pattern, but these methods take time. Next, a method of simply finding the rising speed of the pattern voltage will be described. The potential of the outside of the pattern and the substrate silicon shown in Fig. 3 (2) is usually the same. Lines and space patterns correspond to wiring electrodes connecting gates or gates in semiconductor devices, and lines are disposed on the device isolation insulating film or the interlayer insulating film between the multi-layer wirings except for portions connected to the gate oxide film. The potential rising speed of the pattern on the insulating film corresponds to the speed of charging the capacitor formed of the insulating film with ion current from the plasma. Since the ion current flowing into the poly Si forming the line is neutralized with electrons at the groove side, 100% of the saturated ion current density Is of the plasma is not incident, but the upper limit is given as Is. In other words, the value calculated using Is is the worst case and can be used as a standard to prevent breakdown. When the capacitor C (F / cm 2) per unit area is charged with current I (A / cm 2), the rising speed of the voltage Vc (V / s) is given by Vc = I / C.

The rise dV (V) of the voltage between time Ton (s) becomes dV = Vc x Ton.

If Ton is set so that dV obtained in this way is equal to or less than the breakdown voltage Vb of the gate oxide film or the saturation voltage Vsat of the pattern, breakage of the oxide film can be suppressed. In addition, in order to increase the safety margin, Ton may be set so that the pattern potential Vp is 50% or less of Vb or Vsat.

The breakdown voltage Vb of the gate oxide film varies depending on the film. The saturation voltage Vsat of the pattern also depends on the shape of the pattern and the plasma state. Therefore, the conditions for suppressing gate oxide film breakdown, which are established by processing several nm of oxide film, will now be described. The breakdown field strength of the thermal oxide film of this thickness is 6 to 12 MV / cm. The current device gate oxide film thickness is about 5 nm, and when this value is aimed at, Vb becomes 3 to 6V. If the lines and space patterns to be etched are arranged on the insulating film having a thickness of 100 nm, the capacitance C per unit area of the insulating film is 4x10 ^-8 F / cm 2. If the saturation ion current density Isat of the plasma during etching is 2 mA / cm 2, the voltage rising rate Vc = I / C of the line and space pattern is 0.5 x 10 ⁵ V / s. In order to prevent this voltage from exceeding 3 to 6 V of the breakdown voltage Vb described above, the on time ton of the high frequency voltage applied to the sample may be set to 60 to 120 mV or less. The setting is based on the quality of the oxide film, but considering the margin of safety, 50% or less of these, that is, Ton may be 30 to 60 kPa or less. As described above, the on time of the high frequency voltage for preventing the destruction of the gate oxide film is obtained from the thickness of the underlying insulating film and the ion saturation current.

The on time of the high frequency voltage has been described above. The off time takes a sufficiently long time for the pattern potential to decrease, but since the time constants of the charge and discharge are usually about the same, the off time may be set to at least the on time. In other words, if the period of on / off repetition is T and the ratio of the on time in one cycle is the duty ratio D, D may be 50%. In addition, in order to increase the safety margin, it is sufficient to make the off time more than twice the on time.

Next, Fig. 7 shows the results of measuring the dielectric breakdown rate of the gate oxide film 203 by etching the damage evaluation device having the structure shown in Fig. 24 in this apparatus. The etching gas was a pressure of 1 Pa with a mixed gas of C12 (80 sccm) and BC13 (20 sccm). The output of the microwave power source 101 was 700W. The electrode temperature was 40 degreeC. The frequency of the high frequency voltage power supply 109 was 80 OKHz, and the power of continuous output was 70W. At on / off, the peak power was 350 W, the repetition frequency was 2 kHz, and the duty ratio was 20%. The net power is 70W by the product of the peak power and the duty ratio, and the on time is 100mW. Under these conditions, the etching rate of high frequency voltage continuous and on / off aluminum, poly Si, and resist becomes the same. The shape of the element shown in Fig. 24 is 4 nm in the thickness of the gate oxide film 203, 0.2 nm in the thickness of the poly Si layer 202, 1 mu m in the thickness of the resist 201, and 0.5 mu m in the width of the line and space, respectively. It was.

In Fig. 7, the number of lines and the antenna ratio ((space area) / (gate oxide film area)) are used as parameters. Under any condition, the breakdown rate of the device is 0% by turning the bias on and off, and the effect of the present embodiment can be seen.

Next, various parameter dependences of the line and space pattern potential in the state of FIG. 3 (2) are shown. When the high frequency voltage is turned on / off, the pattern potential oscillates as shown in Fig. 6, but the pattern potential shown below represents the peak value of the acid of the voltage when the voltage is stabilized. The following values are numerical calculation examples in which the thickness of the underlying insulating film is assumed to be 100 nm, but the etching conditions can be set for these targets.

Fig. 8 shows the relationship between the value of the saturated ion current from the plasma at the on / off repetition frequency of 2 kHz, the duty ratio of 20%, and the voltage amplitude of 1500V at on and the pattern potential. As the saturated ion current from the plasma increases, the pattern potential increases to easily damage the gate oxide film. From Fig. 8, it can be seen that when the saturated ion current is 5 mA / cm 2 or less, the pattern potential becomes 3 V or less and gate breakage can be suppressed. In order to reduce the saturated ion current density, the power of the electromagnetic wave generating the plasma may be reduced. In the apparatus of FIG. 1, when the microwave power is 1500 W or less, the saturated ion current density becomes 5 mA / cm 2 or less. Since the volume of the plasma generating portion (the space from the upper surface of the sample table 108 to the lower surface of the introduction window 103) of the etching apparatus shown in FIG. 1 is 15000 cc, the microwave power per cc should be 0.1 W / cc or less. Even if the volume of the plasma generating portion is changed or the method of the etching apparatus is changed, the ratio of the power of the plasma generating power source and the volume of the plasma generating portion may be 0.1 W / cc or less.

9 shows the pattern potential when the duty ratio is changed at a constant repetition frequency of 2 kHz, and the pattern potential can be 6 V or less at a duty ratio of 50% or less.

10 shows the pattern potential when the repetition frequency is changed at a duty ratio of 20%. If the repetition frequency is 250 Hz or more, the pattern potential can be 6 V or less. 11 shows the relationship between the leak resistance of the pattern and the pattern potential. The leak resistance of a pattern is expressed as the total of the phenomenon in which the static charge accumulated in the pattern is neutralized with electrons by the surface electrical conductivity of the resist, the leak resistance of the oxide film, or the injection of electrons from the plasma. The lower this value, the lower the potential because the pattern potential discharges quickly. When the device is designed so that this value is equal to or less than 4 ohm square m or the etching conditions are set, the pattern potential becomes 6V or less. In normal machining, no special setting is necessary, but for example, the machining of lines and spaces having a very high aspect ratio is necessary. In the design of the device, a part of the pattern is bonded to the silicon wafer of the substrate through a material having a low resistance, and the part is cut off after finishing the processing of the line and the space. As etching conditions, in order to lower the resist surface resistance, gases C02, C0, CF4, CH4 and the like containing carbon atoms are mixed so that carbon is deposited on the resist surface.

12 is an example of calculation of the arrival rate and the pattern potential of the former groove bottom. The arrival rate of ions to the groove bottom is a parameter. The arrival rate of ions or electrons to the groove bottom depends on the aspect ratio of the groove and the etching conditions.

Next, the gas used for etching is demonstrated. This embodiment is suitable for the machining of lines and spaces with high aspect. Such lines and spaces correspond mainly to metal wirings connected to the gate electrodes or gates of transistors. The gate electrode is made of an alloy of poly Si, poly Si and metal, a high melting point metal such as tungsten, or a multilayer film of these materials. For the etching of these materials, chlorine, HBr, a mixed gas of chlorine and oxygen, a mixed gas of HBr and oxygen, or a mixed gas of chlorine, HBr and oxygen is suitable. In addition, for etching the metal wiring, a mixed gas of chlorine, chlorine and BC13, a mixed gas of chlorine and HC1, or a mixed gas of chlorine, BC13 and HC1 is suitable. In other words, the present embodiment improves the effect in use in combination with these gases.

In this embodiment, the widths of the lines and the spaces are 0.5 µm, respectively, but the width and width of the lines and the spaces are 1 µm or less and the aspect ratio is 1 or more, and the effect of the present embodiment can be obtained.

EXAMPLE 2

13 is a structure of another plasma etching apparatus to which the present invention is applied. In this device, plasma is generated by inductive coupling at frequencies in the so-called radio frequency (hereinafter referred to as rf) of several hundred kHz to several tens of MHz. The vacuum container 1303 is made of a material that transmits electromagnetic waves such as alumina and quartz. An electromagnetic coil 1302 is wound around the plasma 1310 to generate the plasma 1310. The rf power supply 1304 is connected to the coil. In the vacuum container 1301, there is a sample stage 1308, and a sample 1307 is placed thereon, and a high frequency voltage power supply 1309 is connected thereto. The top cover 1305 is attached to the vacuum container 1301, but this may be an integral type.

Even in this type of device, if the high frequency voltage power supply 1309 is turned on / off to suppress the rise of the pattern potential, the destruction of the gate oxide film can be prevented.

In the plasma etching apparatus shown in FIG. 13, even if the electromagnetic coil 1302 is provided on the upper cover 1305, the effect is the same.

EXAMPLE 3

14 is a structure of another plasma etching apparatus to which the present invention is applied. In this device, plasma is generated by capacitive coupling of rf power. In the vacuum container 1401, two electrodes 1402 and 1405 are arranged in parallel. The rf power supply 1403 and the high frequency voltage power supply 1406 are connected to the electrodes, respectively. The sample 1404 is placed on the electrode 1405 serving as the sample stage. The gas is introduced into the container through the introduction tube 1408 from a hole open to the electrode 1402 facing the sample. The plasma 1407 is generated between two electrodes.

Even in this type of device, if the high frequency voltage power supply 1406 is turned on / off to suppress the rise of the pattern potential, the destruction of the gate oxide film can be prevented.

As mentioned above, according to this invention, the rise of a pattern potential can be suppressed and the breakdown of a gate oxide film can be prevented.

EXAMPLE 4

Hereinafter, another embodiment of the present invention will be described with reference to FIGS. 15 and 16. The results of etching the fine pattern consisting of lines and spaces in the apparatus of FIG. 1 are shown in FIGS. 15 and 16. A mixed gas of chlorine (72 sccm) and oxygen (8 sccm) was used as the etching gas, and the pressure inside the vacuum vessel 14 was set to 0.4 Pa. The output of the microwave power source 101 was 40 OW. The frequency of the bias power supply 109 is 80 OKHz. The structure of the etched element is 4 nm in thickness of the gate oxide film 202 on the silicon substrate 201, 300 nm in thickness of the poly Si 203, 1 μm in thickness of the resist 204, and the width of the line and space. Are 0.4 mu m each. FIG. 15 shows the bias power supply 109 at 60W as a continuous output (hereinafter referred to as continuous bias), and FIG. 16 shows the duty ratio at 300W peak output at on / off control (hereinafter referred to as on / off bias). The etching shape in the case of 20% of the ratio of the on-period in one cycle is shown. The repetition frequency of on / off was 1 kHz. The etching rate of poly Si under these conditions is about 250 nm / min, and the selectivity with respect to the oxide film is about 20. 15 and 16 show the middle shape of the etching of poly Si 203.

As shown in Fig. 15, in the continuous bias, the verticality of the sidewall of poly Si is poor, and in the sidewall 207 facing the narrow portion and the sidewall 208 facing the wide portion, the wider portion becomes worse (the shape is worse). Micro loading). Further, fine grooves called the sub trenches 209 are formed in the etching bottom surface. In the on / off bias, the verticality of the sidewalls is improved, which reduces the shape micro loading.

At the same time, the difference D is reduced in the depth of the poly Si 205 between the sub trench and the line and the depth of the poly Si 206 of the wide space portion.

The sub trenches occur because the verticality of the sidewalls deteriorates and ions are reflected from the sidewalls and enter the bottom surface. Therefore, the verticality of the side wall is improved, which is reduced. Normality is generally better with higher ion energy. The ion energy is approximately proportional to the amplitude of the bias voltage (hereinafter referred to as Vpp). Vpp at continuous bias 60W is 320V and Vpp at 300W on / off bias peak power is 1410V.

Therefore, as shown in FIG. 16, ion energy became higher in on / off bias, and the perpendicularity improved. Higher Vpp in a continuous bias improves verticality. However, since the etching rate of the oxide film is largely increased in proportion to Vpp, the selectivity of poly Si and the oxide film is lowered, which is not suitable when the underlying oxide film is thin such as the etching of the gate electrode of the transistor.

In the on / off bias, by providing an off period for accelerating ions, the number of high energy ions can be reduced, and the verticality can be improved without lowering the selectivity.

Suitable gases for etching poly Si include HBr and SF6. Typical conditions are HBr (100 cc) + oxygen (5 cc) at a pressure of 0.2 Pa and the output of the microwave power source 101 at 40 W. In addition, a mixed gas of chlorine, HBr and oxygen is also widely used, and a mixture of chlorine (20cc) + oxygen (3cc) + HBr (90cc) at a pressure of 0.4 Pa or the like is used.

[Example 5]

  Next, the result of applying to the etching of another material is demonstrated. As shown in FIGS. 17 and 18, the 4 nm oxide film 302 on the silicon substrate 301, the 300 nm poly Si film 303 and the 80 nm tungsten silicide (WSi) film 304 are formed on the silicon substrate 301. In the uppermost layer, there is a silicon nitride film 305 processed in a pattern shape as a mask. The etching gas was a mixed gas of chlorine (185 sccm) and oxygen (15 sccm), and the pressure was 0.8 Pa. The output of the microwave power source 101 was 400W. The frequency of the high frequency power supply 109 is 80 KHz.

17 and 18 show cross-sectional shapes during the etching of poly Si. FIG. 17 shows the etching pattern when the continuous bias is 60W (Vpp is about 370V) and the duty ratio is 20% at the peak output of 300W (Vpp is about 1450V) by on / off bias. The etching rate of poly Si under this condition is about 350 nm / min, and the selectivity with respect to the oxide film is about 25.

Also in this sample, when etching with a continuous bias, as shown in FIG. 17, the perpendicularity is bad and micro loading is also large. On the other hand, in the on / off bias, as shown in FIG. 18, the verticality of the sidewall is improved. In this sample, needle-like protrusions 306 are visible on the etching surface of poly Si. This is probably caused by a foreign material on the interface between poly Si 303 and WSi 304 as a mask, and is a cause of the rest of etch. In on / off bias, the density of the needle-like protrusions can also be reduced.

EXAMPLE 6

Next, the example which implemented this invention for the etching of the multilayer film of a metal and a semiconductor is demonstrated. In order to further increase the speed of semiconductor devices, development using a metal having a resistance lower than poly Si for the gate electrode of a transistor is underway. As shown in FIG. 19, the sample is a multilayer film of an oxide film 402, polysilicon 403, tungsten nitride 404, and tungsten 405 deposited on a silicon substrate 401, and a mask 406 of Si nitride on the top layer. ) Is formed. The gas used for etching was 38 sccm of chlorine, 12 sccm of oxygen and 0.2 Pa pressure. Microwave power is 500W and sample temperature is 70 ℃.

FIG. 19 (a) shows a case where a continuous bias 140W (Vpp is 890V) is applied to a sample, and FIG. 19 (b) shows an on / off bias when the peak power 700 (Vpp is 1720V) is 20% duty ratio. .

In this sample, since the vapor pressure of the chloride of tungsten is low and difficult to etch, as shown in Fig. 19A, the vertical bias and the shape micro loading become more problematic in the continuous bias. This difference is also reflected in the shape of the underlying poly Si. On the other hand, as etching in on / off bias, as shown in Fig. 19B, the verticality of the sidewall of tungsten etching is improved. In addition, the etching bottom surface is smoother than the continuous bias.

In the sample of FIG. 19, poly Si 403 and WN 404 are inserted as a buffer layer between the tungsten 405 and the oxide film 402. However, the structure of only the tungsten 405 is examined to further increase the speed. It is becoming. This invention is effective also in the element of this structure.

As described above, tungsten has been described as an example, but other metal materials include high melting point metals such as molybdenum, nickel, cobalt, and titanium that can withstand high temperature heat treatment. As the barrier film, there is a combination of nitrides of these metals. In the processing of these materials, a smooth etching surface can be obtained while improving the verticality by adding on / off-biasing and gas for promoting the etching of metals such as oxygen. The material of the mask may be an organic photoresist, but since the carbon contained in the resist promotes etching of the oxide film and the selectivity decreases, an inorganic film such as silicon oxide or silicon nitride can make the selectivity higher.

As the gas for etching tungsten or the like, there are other gases containing fluorine atoms such as SF6 and CF4. Even in this gas system, tungsten can be etched smoothly by turning the high frequency voltage on and off. In addition, when oxygen is added to these gases, the effect is further increased because oxygen promotes etching of tungsten. If a gas containing a fluorine atom is used, the etching rate is relatively high even if the sample temperature is low. However, since the etching of the sidewall of the etching groove of the polysilicon portion by fluorine proceeds, the temperature of the sample needs to be 20 ° C or lower.

EXAMPLE 7

In the following, an embodiment of a device having a structure of polysilicon electrodes having different conductivity on the same wafer for speeding up a device called dual gate will be described. 20 is a cross-sectional view of a sample, in which an oxide film 502, a p-type polycrystalline silicon 503, an n-type polycrystalline silicon 504, and a resist 505 are formed on a silicon substrate 501. The gas used for etching was 55 sccm of chlorine, 4 sccm of oxygen, 0.4 Pa in pressure, and the microwave power was 400W.

FIG. 20 (a) shows the power at 35W with continuous bias, and FIG. 20 (b) shows the shape at 20% peak power at 175W with on / off bias. The etching rate of the semiconductor is large in n type and small in p type depending on its conductivity. Therefore, in the machining of the dual gate, the difference E of the etch depth occurs even in a wide space due to the difference in the etching rates of the n type and the p type. There is also a difference in work shape, and the p-type has a worse verticality of the sidewall than the n-type. For this reason, processing becomes more difficult. As shown in Fig. 20B, in the on / off bias, the shape difference between the p type and the n type can also be improved. The difference between the n-type and the p-type is considered to be due to the difference in chemical reactivity between halogen radicals such as chlorine. The p-type has a lower reactivity with halogen, and the etching rate decreases, resulting in a larger line thickness. On the other hand, most of the physical spatters contributed by ion energy are not different between n-type and p-type. Therefore, in the on / off bias having a large ion energy, the difference between the n-type and p-type becomes small.

EXAMPLE 8

Next, the result of applying this invention to the etching of metals, such as aluminum, is demonstrated. As shown in FIG. 21, an oxide film 602 300 nm, TiN 603 10 Onm, Al 604 40 Onm, TiN 605 75 nm are deposited on the substrate Si 601, and a resist mask 606 is formed on the top layer. 1 micrometer is affixed. The line and space dimensions are 0.4 μm. The etching gas was a mixture of chlorine (80 sccm) and BCl 3 (20 sccm), and the pressure was 1 Pa. The output of the microwave power supply 101 was 700W, and the electrode temperature was 40 degreeC. The frequency of the high frequency voltage power supply 109 was 80 OKHz, and the repetition frequency of on / off was 2 kHz.

Fig. 21 (a) shows the etching shape when the power is 70W with the continuous bias, and the peak power is 350W at the on / off bias and the duty ratio is 20%. In this sample, the micro-loading is large, and the verticality of the side wall 607 facing the large space during continuous bias is particularly bad, but is suppressed by the on / off bias.

EXAMPLE 9

Next, the relationship between the ion energy and its high frequency voltage necessary to improve the perpendicularity will be described. Since the absolute value of ion energy which obtains a vertical side wall varies with a sample or etching conditions, it cannot be prescribed | regulated. However, experiments show that the effect starts from about 1.2 times the ion energy of continuous bias, and becomes remarkable at 1.5 times or more. Therefore, in order to improve the perpendicularity without changing the etching rate and selectivity, the ion energy is increased by 1.2 times and the number of ions of the energy is reduced to about 80%. In other words, the duty ratio is set to 80% as on / off bias. If the ion energy is 1.5 times, the duty ratio is 67%.

Since the intrinsic physical quantity which affects the shape of etching is ion energy, in order to improve perpendicularity, ion ion may be made high. However, since the measurement of energy takes time, the amplitude of the bias (Vpp) can be targeted. When a high frequency voltage is applied to the sample stage via the plasma, a direct current potential is generated to introduce ions into the sample stage due to the action of flowing a current between the earth (usually the conductor wall becomes the earth) and the electrode (after Vdc). Ions are accelerated by an electric field superimposed with this Vdc and a high frequency voltage that changes in time. The maximum energy gained by the ions begins to change whether or not it follows the temporal change of the high frequency voltage.

In general, the density of plasma used for etching is more than 10 multipliers of 10 per cubic cm. At this density, Emax is approximately equal to the voltage amplitude, because at high frequencies below 15 MHz, ions reach the sample across the plasma sheath during periods during which the high frequency voltage is in contact with the negative, ie, between half of the sine wave. It is equal to 1/2 (Vpp / 2) plus Vdc. In fact, there is a voltage drop in an electric circuit and the like, and it is known from the measurement that Emax is 70 to 80% of Vpp. When the frequency of the high frequency rises so that the movement of ions does not follow the change in voltage, Emax gradually approaches Vdc. The transition is between 15 MHz and several tens of MHz, but Emax is above Vpp / 2.

The on / off repetition frequency is appropriately between 100 Hz and 10 kHz. If the frequency is lower than this, the effect of the on / off control is gradually lowered. If the repetition frequency is high, it is technically difficult to prepare the high frequency power supply 109.

Next, the goal of ion energy required to achieve high anisotropy is described. This value is not determined as a single value because it depends on the material to be etched and the etching conditions. However, this value is a guideline for the on / off control of the bias. Here, the degree of anisotropy of the etching is expressed by the inclination (taper angle) of the sidewall of the line pattern to calculate the ion energy E necessary to obtain a taper angle close to 90 °. The calculation of the taper angle is based on a theoretical formula published on page 45 of the 1997 dry process symposium published by the Institute of Electrical Engineers. In this theory, the taper angle q is represented by q = arccos (R / dAF). Where R is the deposition rate of the reaction product, d is the depth that affects when the ions are incident, called the ion range is given by d = 0.1O (nm). A is given by A = 0.025E ^2/3 as the area of influence range (hot spot) caused by the incident ions. F is the collision frequency of ions per unit area and can be calculated from the ion current density incident on the sample.

The relationship between the ion energy E and the taper angle q calculated by the formula explained above in FIG. 22 is shown. Providing the off period in the bias here reduces the number of accelerated ions, i.e., lowers the actual ion current density by the duty ratio. Fig. 22 is a calculation in which the ion current density is 1.4 mA / cm 2 and the duty ratio is 20%. The deposition rate R (nm / s) is used as a parameter. This value varies depending on the etching material and pressure, but is estimated to be approximately 10 to 40 nm / minute shown in FIG. The smaller R corresponds to the case where the reaction product is less (fast exhaust rate) or the reaction product is difficult to attach. The larger R corresponds to the case where the reaction product is large or easy to attach. In order to obtain a taper angle of 80 ° or more, which is an allowable range in FIG. 22, it can be seen that the goal is to set E = 300 eV or more at R = 10 nm / s and E = 600 eV or more at R = 40 nm / s.

EXAMPLE 10

Next, the conditions of etching are demonstrated. The conditions described in the above embodiments are typical values, and the present invention is effective even if the gas pressure, type, power value for plasma generation, etc. change. However, in consideration of the etching rate and the selectivity, it is preferable to use it within the range described below. First, as a mixed gas of chlorine and oxygen mainly used for etching poly Si and its multilayer film, the mixing ratio of oxygen is suitably 0% to 50% at a chlorine flow rate of 20 sccm to 1000 sccm. As the amount of oxygen is no longer mixed, the etching rate of poly Si becomes very slow. Moreover, the pressure is suitably from 0.1 Pa to 10 Pa. In the case where the etching gas is a mixed gas of chlorine, HBr, and oxygen, the flow rate of chlorine and HBr is appropriately in the range of 20% to 100% scsc.

In addition, for the etching of metal wirings such as A1, a mixed gas of chlorine, chlorine and BC13, a mixed gas of chlorine and HCl, or a mixed gas of chlorine and BC13 and HC1 is suitable. In this case, 0% to 50% of the mixing ratio of BC13 is appropriate at 20 sccm to 1000 sccm, respectively, for the flow rates of chlorine and HC1. Moreover, you may mix diluent gases, such as CH4 or argon, with these gases.

The density of the plasma is determined by the power of the plasma generating power source, and is closely related to the etching rate. In order to obtain a practical speed, the power of the plasma generating space, that is, the volume between the sample stage and the electrode, may be set to 0.01 W / cc or more. In addition, if the plasma density is too high, electrical damage or the like of the device becomes a problem. Therefore, the plasma density is preferably 0.2 W / cc or less.

Moreover, the frequency of the high frequency power supply applied to a sample is good between 1OOKHz and 100MHz. If the repetition frequency of the on / off bias is 10 OHz or less, the on / off time is too long and the etching side walls are not smooth. A high repetition frequency makes it difficult to produce a power supply, so 10KHz or less is suitable. If the duty ratio of on / off is too small, it is difficult to maintain the etching rate, so 5% or more is preferable. If it is too big, it is equal to continuous bias, so 80% or less is good. The high frequency power applied to the sample varies greatly depending on the frequency, but is 20 W to 500 W at 100 KHz to 800 KHz, 40 W to 1 KW at 800 KHz to 5 MHz, and 80 W to 2 KW at 5 MHz to 100 MHz. Is good. On / off bias power is also the product of peak power and duty ratio.

In addition, the present invention is particularly effective in processing a fine pattern having a line and space spacing of 0.5 µm or less. In the gate electrode, the underlying oxide film has a thickness of 5 nm or less.

You may use this invention for the step etch which changes conditions during an etching. In this case, for example, using a mixed gas of HBr and oxygen, which has a high selectivity for overetching, to take an etch after the underlying oxide film is exposed by using an on / off bias on the main etching etching poly Si. There is a combination. In addition, since the present invention also has an effect of reducing the density dependency of the etching rate, the so-called electron shedding damage caused by the difference in the directionality of ions and electrons in the plasma during etching can be reduced. In this case, the damage can be reduced without reducing the selectivity by reducing the amplitude of the high frequency voltage immediately before the end of etching of the material to be etched as on / off bias in the first step.

In addition, although the embodiment of the present invention has been described in the embodiment of on / off of the high frequency power source, the output from the high frequency power source may be zero completely during the off time, but it is not necessarily zero. In other words, the output from the high frequency power supply can be made small so that the energy acting on the ions does not affect the processing during off time. Thus, off also includes a small output.

In addition, in the embodiment of the present invention, the control for turning on / off the output of the high frequency power source, that is, the time modulation of the bias voltage, has been described. However, as shown in FIG. 23, it can be used in combination with the generation of periodic plasma. The control device 112 is connected to the microwave power source 101, and the output of the microwave is controlled by the pulse-shaped output 113. Moreover, the pulse voltage 111 of both electric potentials at the time of off in ON / OFF control of the output of a high frequency power supply can also be output. In addition, in FIG. 23, the same code | symbol as FIG. 1 shows the same member, and abbreviate | omits description. The plasma generating means is not limited to microwaves as in this case. When the pulse voltage is superimposed by an output or another power supply device at the time of OFF, electrons can be drawn to the etching target surface when the pulse voltage is applied, and the effect of the charge-up delay is improved. However, in the etching target portion having a smaller pattern width and a higher aspect ratio, electrons are repelled at the inlet of the upper portion of the pattern by electrons charged in the side wall, and electrons cannot reach the bottom surface, so that the effect of delaying the filling up is lost. In this case, by lowering the electron temperature of the plasma, the free movement of the electrons is slowed down, the movement of the horizontal components of the electrons when the electrons are attracted by both voltages is reduced, and the charge of the electrons on the sidewalls is reduced to reduce the pattern bottom surface. The incidence of electrons on can be made easy to produce the effect of delaying charging up.

  At this time, this can be achieved by periodically generating the plasma as a means for lowering the electron temperature of the plasma. Therefore, in order to prevent the charging of the fine pattern, it is effective to combine the periodic generation of the plasma, the on / off of the high frequency power supply, and the application of the pulse voltage at the electrostatic potential at the off time.

According to the present invention, there is an effect that the anisotropy can be improved and the selection ratio can be prevented in etching the fine pattern.

According to the present invention, the verticality of the etching can be increased and the shape micro loading can be reduced.

According to the present invention, the thickness of the line pattern can be reduced and the shape micro loading can be reduced.

1 is an overall configuration diagram of an etching apparatus for performing a surface processing method of an embodiment of the present invention,

FIG. 2 is a view showing the gas pressure in the vacuum vessel 104 and the operation of each of the power sources 101 and 109 during the etching process by the apparatus of FIG.

3 is a cross-sectional view of a sample surface processed by the apparatus of FIG. 1 according to Example 1;

4 is a diagram showing a relationship between processing time and pattern potential;

5 is a diagram showing a relationship between a voltage and a current of a gate oxide film;

6 is a diagram showing a relationship between processing time and pattern potential;

7 is a diagram showing a relationship between a breakdown rate of a gate oxide film;

8 is a diagram showing a relationship between a saturated ion current and a pattern potential.

9 is a diagram showing a relationship between a duty ratio and a pattern potential;

10 is a diagram showing a relationship between a repetition frequency and a pattern potential;

11 is a diagram showing a relationship between a leak resistance and a pattern potential;

Fig. 12 is a diagram showing the relationship between the electron bottom groove arrival rate and the pattern potential;

13 is an overall configuration diagram showing another embodiment of an etching apparatus for performing the surface processing method of the present invention;

14 is an overall configuration diagram showing still another embodiment of the etching apparatus for implementing the surface processing method of the present invention;

15 is a cross-sectional view of a sample for describing example 4 of the present invention;

16 is a cross-sectional view of a sample for describing example 4 of the present invention;

17 is a cross-sectional view of a sample for describing example 5 of the present invention;

18 is a cross-sectional view of a sample illustrating a fifth embodiment of the present invention;

Fig. 19 is a sectional view of a sample illustrating Example 6 of the present invention;

20 is a cross-sectional view of a sample illustrating a seventh embodiment of the present invention;

Fig. 21 is a sectional view of a sample illustrating Example 8 of the present invention;

Fig. 22 shows the relationship between ion energy and taper angle in the method of the present invention;

23 is a block diagram showing a plasma etching apparatus as another embodiment of the surface treatment apparatus of the present invention;

Fig. 24 is a view showing a cross section of a sample for explaining the electron shedding phenomenon when the surface is processed by a conventional method.

Claims (29)

On the surface of the sample using a device comprising a vacuum vessel, a means for generating a plasma therein, a sample stage for installing a sample surface-treated by the plasma, and a high frequency power source for applying a high frequency voltage to the sample. In the surface treatment method for forming a fine pattern, By repeatedly turning on / off the high frequency power supply during the processing of the sample and controlling the off time of the high frequency power supply to be longer than the on time, the charging voltage of the pattern reaches the dielectric breakdown voltage of the gate oxide film to which the pattern is connected. And turning off the high frequency power before turning on the high frequency power after sufficiently charging of the pattern is sufficiently low. delete The method of claim 1, The relationship between the on time (Ton) of the high frequency power supply, the capacitance (C) of the underlying insulating film of the fine pattern, and the ion current density (I) from the plasma is set so that Ton x I / C is equal to or less than the dielectric breakdown voltage of the gate oxide film. Surface treatment method characterized in that. The method of claim 1, The relationship between the on time (Ton) of the high frequency power supply, the capacitance (C) of the underlying insulating film of the fine pattern, and the ion current density (I) from the plasma is that Ton x I / C is 50% or less of the dielectric breakdown voltage of the gate oxide film. Surface treatment method characterized in that set so as to. delete The method of claim 1, Surface treatment method characterized in that the off time (Toff) of the high frequency power supply is more than twice the on time (Ton). The method according to claim 3 or 4, The relationship between the on time Ton of the high frequency power supply, the capacitance C of the underlying insulating film of the fine pattern, and the ion current density I from the plasma is set such that Ton x I / C is 6 V or less. Treatment method. The method according to claim 3 or 4, The relationship between the on time Ton of the high frequency power supply, the capacitance C of the underlying insulating film of the fine pattern, and the ion current density I from the plasma is set such that Ton x I / C is 3 V or less. Treatment method. The method according to claim 3 or 4, The ion current density (I) from plasma was 5 mA / square cm or less, The surface treatment method characterized by the above-mentioned. The method of claim 1, Surface treatment method characterized in that the ratio of the power (W) of the means for generating plasma and the volume (cc) of the plasma generating space is 0.1 W / cc or less The method of claim 1, The gas used to generate the plasma includes at least one of chlorine, BCl 3 and HCl. The method of claim 1, The gas used for generating the plasma is chlorine and oxygen or HBr and oxygen, or a mixed gas of chlorine and HBr and oxygen. The method of claim 1, A surface treatment method comprising adding a gas containing carbon to a gas used for generating a plasma. The method of claim 1, The sample is a sample in which the fine pattern is designed so that the resistance between the fine pattern on the substrate and the silicon substrate is 4 ohm square meter or less, and the sample is processed. In the apparatus comprising a vacuum vessel, a means for generating a plasma therein, a sample stage for installing a sample surface-treated by the plasma, and a high frequency power source for applying a high frequency voltage to the sample, By repeatedly turning the high frequency power on and off, the off time of the high frequency power is controlled to be longer than the on time so that the charging voltage of the fine pattern formed on the sample reaches the dielectric breakdown voltage of the gate oxide film to which the pattern is connected. And a control means for turning off the high frequency power before and turning on the high frequency power after the charging of the pattern is sufficiently low. delete The method of claim 15, The relationship between the on time (Ton) of the high frequency power supply, the capacitance (C) of the underlying insulating film of the fine pattern, and the ion current density (I) from the plasma is set so that Ton x I / C is equal to or less than the dielectric breakdown voltage of the gate oxide film. Surface treatment apparatus characterized in that. The method of claim 15, The relationship between the on time (Ton) of the high frequency power supply, the capacitance (C) of the underlying insulating film of the fine pattern, and the ion current density (I) from the plasma is that Ton x I / C is 50% or less of the dielectric breakdown voltage of the gate oxide film. Surface treatment apparatus characterized in that set so as to. delete The method of claim 15, A surface treatment apparatus characterized in that the off time (Toff) of a high frequency power supply is made more than twice the on time (Ton). The method of claim 17 or 18, The relationship between the on time Ton of the high frequency power supply, the capacitance C of the underlying insulating film of the fine pattern, and the ion current density I from the plasma is set such that Ton x I / C is 6 V or less. Processing unit. The method of claim 17 or 18, The relationship between the on time Ton of the high frequency power supply, the capacitance C of the underlying insulating film of the fine pattern, and the ion current density I from the plasma is set such that Ton x I / C is 3 V or less. Processing unit. The method of claim 17 or 18, A surface treatment apparatus characterized in that the ion current density (I) from the plasma is set to 5 mA / square cm or less. The method of claim 15, And a ratio of the power (W) of the means for generating the plasma to the volume (cc) of the plasma generating space is 0.1 W / cc or less. The method of claim 15, The gas used to generate the plasma comprises at least one of chlorine, BCl 3, HCl. The method of claim 15, The gas used for generating the plasma is chlorine and oxygen or HBr and oxygen, or a mixed gas of chlorine and HBr and oxygen. The method of claim 15, A surface treatment apparatus characterized by adding a gas containing carbon to a gas used for generating plasma. The method of claim 1, The fine pattern has a width of a line and a space of 1 μm or less, and an aspect ratio of 1 or more. The method of claim 15, The fine pattern has a width of a line and a space of 1 μm or less, and an aspect ratio of 1 or more.