JP2000091325A - Method and device for surface treatment - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce damages to a gate oxide film connected to a pattern from electron shading by turning off a high-frequency power source which impresses a high-frequency voltage upon a sample prior to the electrified voltage of the pattern reaches the dielectric breakdown voltage of the gate oxide film, and turning on the voltage after the electrified voltage of the pattern becomes sufficiently lower. SOLUTION: A sample 107 is set up on a sample stage 108. In order to accelerate ions incident on the sample 107, a high-frequency power source 109, which impresses a high-frequency voltage upon the sample 107, is connected to the sample stage 108. The breakdown of a gate oxide film is prevented by preventing the rising of a pattern voltage Vp, by turning off the power source 109 before the voltage Vp exceeds the dielectric breakdown voltage Vb of the gate oxide film. When the power source 109 is turned off, the pattern voltage Vp drops, because the ions are no longer accelerated. When the power source 109 is repeatedly turned on and off in such a way that the source 109 is turned on, when the pattern voltage Vp becomes sufficiently low and turned off before the pattern voltage Vp exceeds the breakdown voltage Vb, the charge amount flowing into the gate oxide film can be maintained at a small amount. Therefore, the dielectric breakdown of the gate oxide film can be prevented.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a surface treatment method and apparatus, and more particularly to a surface treatment method and apparatus suitable for etching the surface of a sample on which a semiconductor element or the like is formed using plasma. .

[0002]

2. Description of the Related Art The prior art will be described with reference to an apparatus utilizing plasma used for etching a semiconductor element, for example, an apparatus called an ECR (Electron Cyclotron Resonance) system. In this method, plasma is generated by microwaves in a vacuum vessel to which a magnetic field is externally applied. Electrons move in a cyclotron due to the magnetic field, and plasma can be efficiently generated by resonating the frequency of the cyclotron motion with the frequency of the microwave. In addition, a high frequency voltage is applied to the sample to accelerate ions incident on the sample. When an Si-based material is used as an object to be etched, a halogen gas such as chlorine or fluorine is used as a plasma gas.

In order to improve the accuracy of such a device,
The technique described in JP-A-6-151360 is known. This technology is a substance to be etched by intermittently controlling on-off of a high-frequency voltage applied to a sample.
The selectivity between Si and the underlying oxide film is increased.

[0004]

With the recent miniaturization of semiconductor devices, the problem of damage to semiconductor devices due to plasma used in processes has become apparent. Specifically, the thickness of the gate oxide film of a MOS (metal oxide semiconductor) transistor is 6 nm or less in a memory element of 256M or more. If the aspect ratio of processing (the ratio of dimensions in the vertical direction to the horizontal direction) increases in addition to the reduction in the thickness of the gate oxide film, electrical damage caused by a phenomenon called electron shading becomes a problem. Next, the electronic shading phenomenon will be described with reference to the drawings. FIG. 2A is a cross-sectional view of a semiconductor wafer exposed to plasma in an etching apparatus. FIG. 2B is a view of the resist pattern of FIG. An element isolation oxide film 204 and a gate oxide film 203 are formed on a Si substrate 205, and a poly-Si layer 202 and a resist 201 are formed thereon in a comb shape. During the plasma etching, electrons 206 and ions 207 are incident on the sample. The ions 207 are accelerated by the high-frequency voltage applied to the sample and are incident perpendicularly to the surface of the sample, but the electrons 206 are incident in irregular directions in which the random velocity component is large because the mass is small. For this reason, as shown in FIG. 2A, in processing a groove having a high aspect ratio, ions can reach the groove bottom 208, but electrons are mainly captured on the side walls of the resist 201. Then, positive charges are accumulated in the gate oxide film 203 via the poly-Si layer 202. If this amount exceeds a certain value, the gate oxide film 203 undergoes dielectric breakdown, resulting in element failure. As described above, a phenomenon in which electrons are not supplied into the fine groove due to a difference in directionality between ions and electrons is referred to as electron shading.

An object of the present invention is to provide a surface treatment method and apparatus capable of reducing damage to a semiconductor element due to the electron shading.

[0006]

According to the present invention, in etching a fine pattern by applying a high-frequency voltage to a sample, the charging voltage of the pattern is reduced by the breakdown voltage of the gate oxide film to which the pattern is connected. Before reaching, turn off the high-frequency power supply to be applied to the sample, and turn on the high-frequency power supply after the pattern is sufficiently charged.
This is achieved by repeatedly processing off.

[0007]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiment 1 An embodiment of the present invention will be described below with reference to FIGS. FIG. 1A is an overall configuration diagram of a plasma etching apparatus to which the present invention is applied. Microwaves are introduced from a microwave power supply 101 into a vacuum vessel 104 through a waveguide 102 and an introduction window 103. The material of the introduction window 103 is a material that transmits electromagnetic waves, such as quartz or ceramic. An electromagnet 105 is provided around the vacuum vessel 104, and the magnetic field strength is set to cause resonance with the microwave frequency. For example, if the frequency is 2.45 GHz, the magnetic field strength is 875 Gauss. Since the cyclotron motion of the electrons in the plasma 106 resonates with the frequency of the electromagnetic wave at this magnetic field intensity, the energy of the electromagnetic wave is efficiently supplied to the plasma, and a high-density plasma is generated. The sample 107 is set on a sample stage 108.
A high frequency voltage power supply 109 is connected to the sample stage 108 to accelerate ions incident on the sample. There is no particular limitation on the frequency of the high-frequency voltage power supply.
A range from 00 kHz to 20 MHz is practical. Fig. 1 (2)
Shows a voltage waveform 110 of the high-frequency voltage power supply 109. According to the present invention, the high frequency voltage can be turned on and off.

FIG. 3 shows the progress of the etching of the cross-sectional shape of the fine pattern. FIG. 3A shows a starting state before etching. In FIG. 3 (2), when the etching of the poly Si in a wide portion outside the line is completed, poly Si 301 between the lines still remains due to a phenomenon called microloading, in which the etching rate of the fine portion decreases. At this point, the fine pattern is electrically disconnected from other surrounding parts, and charging of the pattern starts. Before this, even if charged by electron shading, the charges can escape through the surrounding poly Si. FIG. 3C shows a point in time when the etching proceeds further and the oxide film 302 between the underlying lines is exposed. Here, even if ions enter the groove bottom,
The oxide film is charged due to the absence of poly Si, but does not flow to the gate oxide film 203, so that the deterioration of the gate oxide film thereafter is reduced. That is, the destruction of the gate oxide film almost occurs between FIGS. 3 (2) and 3 (3).

FIG. 4 shows the result of a computer simulation of how the potential of the line and space patterns rises due to electronic shading after being cut off from the surroundings. When the potential of the pattern rises, a current flows through the gate, and when the total amount Q of charges passing through the oxide film exceeds the breakdown charge amount Qbd, the oxide film is destroyed. FIG. 5 shows the voltage-current characteristics of the gate oxide film. From the voltage Va in FIG.
A current called a tunnel current starts to flow, and a large current flows at the voltage Vb. Here, Vb is called a breakdown voltage. The increase in the pattern potential in FIG. 4 is because the application of a high-frequency voltage to the sample accelerates ions and causes electron shading. As described above, in order to prevent the gate oxide film from being broken, the high-frequency voltage may be turned off before the pattern potential Vp exceeds the breakdown voltage Vb to prevent the pattern voltage from rising. When the high-frequency voltage is turned off, ions are not accelerated, so that Vp decreases. If the high-frequency power supply is turned on again at the time when Vp is sufficiently lowered and then turned off before exceeding Vb, the amount of charge flowing through the gate oxide film is kept small, so that dielectric breakdown can be prevented. FIG. 6 shows a change in the pattern potential when the high frequency voltage applied to the sample is turned on and off. In order to further increase the safety margin, it is preferable to turn on / off so that Vp becomes 50% or less of Vb.

Further, since the pattern is not charged indefinitely even when the high-frequency voltage is applied continuously, the pattern potential Vp becomes the saturation voltage Vs when the incidence of ions and electrons is balanced.
Saturates at. If Vsat is smaller than the breakdown voltage Vb,
Although the oxide film does not break down in a short time (several tens of ms), it breaks down after a certain period of time because of a large current.
In this case, destruction of the oxide film can be suppressed by repeatedly turning off the high-frequency power supply before Vp becomes Vsat and turning it on after it is sufficiently lowered. To further increase safety margins
It is preferable to turn on and off such that Vp becomes 50% or less of Vsat.

The potential of a pattern is determined by simulation or by connecting a probe to the pattern, but these methods are time-consuming. Next, a method for easily obtaining the rising speed of the pattern voltage will be described. The potential of the pattern outside and the substrate silicon shown in FIG. In a semiconductor device, the line and space pattern correspond to the gate electrode and the wiring connecting the gate, and the line is formed on the element isolation insulating film or the interlayer insulating film between the multilayer wirings except for the portion connected to the gate oxide film. Have been placed. The rate at which the potential of the pattern on the insulating film rises corresponds to the rate at which a capacitor formed of the insulating film is charged with ion current from plasma. Since the ion current flowing into the poly Si forming the line has a portion neutralized with the electrons on the groove side surface, 100% of the saturated ion current density Is of the plasma is not necessarily incident, but the upper limit is given by Is. That is, the value calculated using Is is the worst case, and this value can be used as a reference for preventing dielectric breakdown. When a capacitor having a capacitance per unit area C (F / cm2) is charged with a current per unit area I (A / cm2), a voltage rising rate Vc (V / s) is given by Vc = I / C. Time Ton
The voltage rise dV (V) during (s) is dV = Vc × Ton. If Ton is set so that dV obtained by this equation is equal to or lower than the breakdown voltage Vb of the gate oxide film or the saturation voltage Vsat of the pattern, the breakdown of the oxide film can be suppressed. To further increase the safety margin, Ton should be set to a pattern potential Vp of 50 Vb or Vsat.
%.

The breakdown voltage Vb of the gate oxide film differs depending on the film. Further, the saturation voltage Vsat of the pattern also depends on the shape of the pattern and the plasma state. Therefore, next, conditions for suppressing gate oxide film destruction that are satisfied by processing an oxide film of several nm will be described. The breakdown electric field strength of the thermal oxide film having this thickness is 6 to 12 MV / cm. The gate oxide film thickness of the current device is about 5 nm, and using this value as a guide, Vb is 3 to 6 V. Here, assuming that the line to be etched and the space pattern are arranged on the insulating film having a thickness of 100 nm, the capacitance C per unit area of the insulating film is 4 × 10 ⁻⁸ F / cm 2. When the saturation ion current density Isat of the plasma at the time of etching is 2 mA / cm2, the voltage rise rate Vc = I / C of the line and space pattern is 0.
5 x 10 ⁵ V / s. This voltage is the breakdown voltage Vb described above.
In order not to exceed 3 to 6 V, the on-time ton of the high-frequency voltage applied to the sample may be set to 60 to 120 μs or less. The setting depends on the quality of the oxide film, but considering the safety margin, it is sufficient to set these to 50% or less, that is, Ton to 30 to 60 μs or less. As described above, the on-time of the high-frequency voltage for preventing the gate oxide film from being broken is determined from the thickness of the base insulating film and the ion saturation current.

The on-time of the high-frequency voltage has been described above. The off time is taken during the time when the pattern potential is sufficiently lowered, but since the time constants of normal charge and discharge are almost the same, the off time may be set to at least the on time. That is, if the cycle of the on / off repetition is T and the duty ratio D is the ratio of the on time in one cycle, D may be set to 50%. In order to further increase the safety margin, it is sufficient to set the off time to twice or more the on time.

Next, FIG. 7 shows the result of measuring the dielectric breakdown rate of the gate oxide film 203 by etching the damage evaluation element having the structure shown in FIG. 2 with this apparatus. The etching gas was a mixture gas of Cl2 (80 sccm) and BCl3 (20 sccm) at a pressure of 1 Pa. The output of the microwave power supply 101 was 700 W. The electrode temperature was 40 ° C. High frequency voltage power supply 109
Was 800 KHz and the continuous output power was 70 W. At the time of on / off, the peak power was 350 W, the repetition frequency was 2 kHz, and the duty ratio was 20%. The net power is 70 W as the product of the peak power and the duty ratio, and the ON time is 100 μs. Under these conditions, the high-frequency voltage continuity and the etching rate of aluminum, poly Si, resist, etc. at the time of on / off are the same. The device shown in FIG. 2 has a gate oxide film 203 having a thickness of 4 nm, a poly Si layer 202 having a thickness of 0.2 nm, a resist 201 having a thickness of 1 μm, and a line and space width of 0.5 μm. In FIG. 7, the number of lines and the antenna ratio ((space area) / (gate oxide film area)) are used as parameters. Under any conditions,
The destruction rate of the element is 0% by turning on and off the bias.
Thus, the effect of this embodiment can be understood.

Next, the dependence of the line and space pattern potentials in the state of FIG. 3 (2) on various parameters will be described. When the high-frequency voltage is turned on and off, the pattern potential oscillates as shown in FIG. 6, but the following pattern potential indicates the peak value of the voltage peak when the voltage is stabilized. The following values are numerical examples in which the thickness of the base insulating film is assumed to be 100 nm, and the etching conditions can be set using these as a guide.
FIG. 8 shows the relationship between the value of the saturated ion current from the plasma and the pattern potential when the on / off repetition frequency is 2 kHz, the duty ratio is 20%, and the voltage amplitude at the time of on is 1500 V. When the saturated ion current from the plasma increases, the pattern potential increases, and the gate oxide film is easily damaged. FIG.
From this, it is found that when the saturated ion current is set to 5 mA / cm 2 or less, the pattern potential becomes 3 V or less, and gate breakdown can be suppressed. In order to reduce the saturation ion current density, the power of the electromagnetic wave for generating plasma may be reduced. In the apparatus of FIG. 1, when the microwave power is set to 1500 W or less, the saturation ion current density becomes 5 mA / cm 2 or less. The plasma generating portion of the etching apparatus shown in FIG.
Since the volume of the space up to the lower surface of 03 is 15000 cc, the microwave power per cc may be set to 0.1 W / cc or less.
Even if the volume of the plasma generating portion changes or the method of the etching apparatus changes, the ratio of the power of the power source for plasma generation to the volume of the plasma generating portion is preferably set to 0.1 W / cc or less. FIG. 9 shows a pattern potential when the duty ratio is changed at a constant repetition frequency of 2 kHz. The pattern potential can be reduced to 6 V or less at a duty ratio of 50% or less. FIG. 10 shows a pattern potential when the repetition frequency is changed while the duty ratio is constant at 20%. When the repetition frequency is set to 250 Hz or more, the pattern potential can be set to 6 V or less. FIG. 11 shows the relationship between the pattern leak resistance and the pattern potential. The leak resistance of a pattern is the resistance expressed as the sum of the phenomenon in which positive charges accumulated in a pattern are neutralized with electrons by surface electric conduction of a resist, leak resistance of an oxide film, or injection of electrons from plasma. The lower this value is, the faster the pattern potential is discharged, and the lower the potential is. If the element is designed so that this value is equivalent to 4 ohm square m or less, or if the etching conditions are set, the pattern potential becomes 6 V or less. No special setting is necessary for normal processing, but it is necessary for processing lines and spaces with a very high aspect ratio, for example. In designing the element, a part of the pattern is bonded to the silicon wafer of the substrate through a substance having a low resistance, and the part is cut off after the line and the space are processed. Further, under the etching conditions, gases containing carbon atoms such as CO2, CO, CF4, and CH4 are mixed to lower the resistance of the resist surface so that carbon is deposited on the resist surface. FIG. 12 is a calculation example of the electron arrival rate at the groove bottom and the pattern potential. The arrival rate of ions to the groove bottom is a parameter. The rate at which ions or electrons reach the bottom of the groove depends on the aspect ratio of the groove and the etching conditions.

Next, the gas used for etching will be described. This embodiment is suitable for processing lines and spaces having a high aspect ratio. Such lines and spaces mainly correspond to a gate electrode of a transistor or a metal wiring portion connected to a gate. Gate electrode is poly Si, pol
y It is made of an alloy of Si and a metal, a high melting point metal such as tungsten, or a multilayer film of these materials. For etching these materials, chlorine, HBr, a mixed gas of chlorine and oxygen, a mixed gas of HBr and oxygen, or a mixed gas of chlorine, HBr, and oxygen are suitable. For etching of metal wiring, chlorine, a mixed gas of chlorine and BCl3, a mixed gas of chlorine and HCl, or a mixed gas of chlorine, BCl3 and HCl is suitable. That is, the present embodiment is more effective when used in combination with these gases.

In this embodiment, the line width and the space width are each 0.5 μm. However, in the case of a fine pattern having a line width and a space width of 1 μm or less and an aspect ratio of 1 or more, respectively. Can obtain the effect of the present embodiment.

Embodiment 2 FIG. 13 shows another apparatus structure to which the present invention is applied. In this apparatus, plasma is generated by inductive coupling at a frequency of a so-called radio wave band (hereinafter referred to as rf) of several hundred kHz to several tens MHz. Generate. The vacuum vessel 1303 is made of a material that transmits electromagnetic waves, such as alumina and quartz. An electromagnetic coil 1302 for generating the plasma 1310 is wound therearound. Rf power supply 1 for coil
304 is connected. A sample table 1308 is provided in the vacuum vessel 1301, on which a sample 1307 is placed, and a high-frequency voltage power supply 1309 is connected. Vacuum container 130
1 has an upper lid 1305, which may be an integral type. In this type of apparatus, the high-frequency voltage power supply 130
By turning on / off 9 to suppress the increase in the pattern potential, it is possible to prevent the gate oxide film from being broken. In the device shown in FIG. 13, the effect is the same even if the electromagnetic coil 1302 is installed on the upper lid 1305.

Embodiment 3 FIG. 14 shows another apparatus structure to which the present invention is applied. In this apparatus, plasma is generated by capacitive coupling of rf power. Two electrodes 1402 and 1405 are arranged in parallel in a vacuum vessel 1401. An rf power supply 1403 and a high-frequency voltage power supply 1406 are connected to the electrodes, respectively. The sample 1404 is an electrode 140 serving as a sample stage.
Put it on 5. The gas is the electrode 1402 facing the sample.
The container is put into the container through the introduction tube 1408 from the hole opened at the end. Plasma 1407 is generated between two electrodes.
Also in this type of device, when the high-frequency voltage power supply 1406 is turned on and off to suppress the increase in the pattern potential, the gate oxide film can be prevented from being broken.

[0020]

As described above, according to the present invention, an increase in the pattern potential can be suppressed and the dielectric breakdown of the gate oxide film can be prevented.

[Brief description of the drawings]

FIG. 1 is an overall configuration diagram showing one embodiment of an apparatus for performing a surface processing method of the present invention.

FIG. 2 is a view showing a cross section of a sample for explaining an electron shading phenomenon when a surface is processed by a conventional method.

FIG. 3 is a cross-sectional view of a sample whose surface has been processed by the apparatus of FIG. 1;

FIG. 4 is a diagram showing the relationship between processing time and pattern potential.

FIG. 5 is a diagram showing a relationship between a voltage of a gate oxide film and a current.

FIG. 6 is a diagram showing the relationship between processing time and pattern potential.

FIG. 7: Breakdown rate of gate oxide film

FIG. 8: Relationship between saturated ion current and pattern potential

FIG. 9 is a relationship between duty ratio and pattern potential.

FIG. 10: Relationship between repetition frequency and pattern potential

FIG. 11 shows the relationship between leak resistance and pattern potential.

FIG. 12 shows the relationship between the rate at which electrons reach the groove bottom and the pattern potential.

FIG. 13 is an overall configuration diagram showing another embodiment of an apparatus for performing the surface processing method of the present invention.

FIG. 14 is an overall configuration diagram showing still another embodiment of the apparatus for performing the surface processing method of the present invention.

[Explanation of symbols]

101 ... microwave power supply, 102 ... waveguide, 103 ... introduction window, 10
4,1303,1401… Vacuum container, 105… Magnet, 106,1310,1407…
Plasma, 107, 1307, 1404 ... sample, 108, 1308 ... sample stage, 1
09,1309,1406… High frequency voltage power supply, 1408… Gas inlet tube, 11
0: voltage waveform, 201: resist, 202: poly Si layer, 203: gate oxide film, 204: element isolation oxide film, 205: substrate Si, 206
… Electrons, 207… ions, 208… groove bottoms, 301… poly between lines
Si, 302: oxide film between lines, 1302: electromagnetic coil, 1304, 14
03 rf power supply, 1305 top cover, 1402, 1405 electrodes.

Continuing from the front page (72) Inventor Yasuhiro Nishimori 794, Higashi-Toyoi, Oji, Kudamatsu, Yamaguchi Prefecture Inside the Kasado Plant, Hitachi, Ltd. (72) Inventor Naoyuki Koto 1-280 Higashi Koigakubo, Kokubunji-shi, Tokyo Inside the Central Research Laboratory of Hitachi, Ltd. (72) Inventor Masaru Izawa 1-280 Higashi Koigakubo, Kokubunji-shi, Tokyo Hitachi Central, Ltd. In the laboratory (72) Inventor Yasushi Goto 1-280 Higashi Koigakubo, Kokubunji-shi, Tokyo Inside the Hitachi, Ltd.Central Research Laboratories (72) Inventor Hideyuki Kazumi 7-1-1, Omika-cho, Hitachi City, Ibaraki Prefecture F-term in Hitachi Research Laboratory, Hitachi Ltd. 4G075 AA30 AA61 BC06 CA26 CA47 CA51 CA65 EC21 FB04 FB06 5F004 AA16 BA14 BA20 BB 11 CA03 CA06 DA00 DA01 DA26 DA29 DB02 DB15 DB17 5F045 AA08 AA10 EH03 EH11 EH12 EH17 EH20

Claims (29)

[Claims] A fine pattern is formed on the surface of a sample by an apparatus comprising a vacuum vessel, means for generating plasma therein, a sample stage on which a sample to be surface-treated by plasma is installed, and a high-frequency power supply for applying a high-frequency voltage to the sample. In the processing method for forming, the high-frequency power supply is turned off before the charging voltage of the pattern reaches the dielectric breakdown voltage of the gate oxide film to which the pattern is connected, and after the charging of the pattern becomes sufficiently low, A surface treatment method comprising: turning on a high-frequency power supply; and repeating the on-off of the high-frequency power supply to process the sample. 2. The method according to claim 1, wherein the high-frequency power supply is turned off before the fine pattern is charged in a steady state, and the high-frequency power supply is turned on after the potential of the pattern is sufficiently lowered. Surface treatment method. 3. The relationship between the on-time Ton of the high-frequency power source, the capacitance C of the underlying insulating film of the fine pattern, and the ion current density I from the plasma, wherein Ton x I / C is the gate oxide film. A surface treatment method characterized by being set so as to be equal to or lower than a dielectric breakdown voltage. 4. The relationship between the on-time Ton of the high-frequency power supply, the capacitance C of the underlying insulating film of the fine pattern, and the ion current density I from the plasma, wherein Ton x I / C is A surface treatment method characterized by being set to be 50% or less of a dielectric breakdown voltage. 5. The surface treatment method according to claim 1, wherein the off-time Toff of the high-frequency power supply is set to be longer than the on-time Ton. 6. The surface treatment method according to claim 1, wherein the off time Toff of the high-frequency power supply is set to be at least twice the on time Ton. 7. The relationship between the on-time Ton of the high-frequency power supply, the capacitance C of the underlying insulating film of the fine pattern, and the ion current density I from the plasma, wherein Ton x I / C is 6 V or less. A surface treatment method characterized by setting as described above. 8. The relationship between the on-time Ton of the high-frequency power supply, the capacitance C of the underlying insulating film of the fine pattern, and the ion current density I from the plasma, wherein Ton x I / C is 3 V or less. A surface treatment method characterized by setting as described above. 9. The surface treatment method according to claim 1, wherein the ion current density I from the plasma is set to 5 mA / cm 2 or less. 10. A surface treatment method according to claim 1, wherein the ratio of the power (W) of the means for generating plasma to the volume (cc) of the plasma generation space is set to 0.1 W / cc or less. 11. A surface treatment method according to claim 1, wherein the gas generating plasma contains at least one of chlorine, BCl3, and HCl. 12. The surface treatment method according to claim 1, wherein the gas generating plasma is chlorine and oxygen, HBr and oxygen, or a mixed gas of chlorine, HBr and oxygen. 13. A surface treatment method according to claim 1, wherein a gas containing carbon is added to the gas for generating plasma. 14. A surface treatment method according to claim 1, wherein the fine pattern is designed so that the resistance between the fine pattern on the substrate and the silicon substrate is 4 ohm square meter or less. 15. An apparatus comprising a vacuum vessel, a means for generating plasma therein, a sample table on which a sample to be surface-treated by plasma is installed, and a high-frequency power supply for applying a high-frequency voltage to the sample. The high frequency power supply is turned off before the charging voltage of the fine pattern formed on the sample reaches the dielectric breakdown voltage of the gate oxide film to which the pattern is connected, and the high frequency power supply is turned on after the charging of the pattern is sufficiently low. A surface treatment apparatus, comprising: 16. A high frequency power supply according to claim 15, wherein the high frequency power supply is turned off before the fine pattern is charged to a steady state, and the high frequency power supply is turned on after the potential of the pattern becomes sufficiently low. Surface treatment equipment. 17. The relationship between the on-time Ton of the high-frequency power supply, the capacitance C of the underlying insulating film of the fine pattern, and the ion current density I from the plasma according to claim 15 or 16, wherein Ton x I / C is the gate oxide film thickness. A surface treatment apparatus characterized in that it is set so as to have a dielectric breakdown voltage or less. 18. The relationship between the on-time Ton of the high-frequency power supply, the capacitance C of the underlying insulating film of the fine pattern, and the ion current density I from the plasma according to claim 15 or 16, wherein Ton x I / C is equal to that of the gate oxide film. A surface treatment apparatus characterized in that it is set so as to be 50% or less of a dielectric breakdown voltage. 19. The surface treatment apparatus according to claim 15, wherein the off-time Toff of the high-frequency power supply is set to be longer than the on-time Ton. 20. The surface treatment apparatus according to claim 15, wherein the off-time Toff of the high-frequency power source is twice or more the on-time Ton. 21. The relationship between the on-time Ton of the high-frequency power supply, the capacitance C of the underlying insulating film of the fine pattern, and the ion current density I from the plasma, wherein Ton x I / C is 6
V. The surface treatment apparatus is set to be V or less. 22. The relationship between the on-time Ton of the high-frequency power supply, the capacitance C of the underlying insulating film of the fine pattern, and the ion current density I from the plasma, wherein Ton x I / C is 3
V. The surface treatment apparatus is set to be V or less. 23. The surface treatment apparatus according to claim 15, wherein the ion current density I from the plasma is 5 mA / cm 2 or less. 24. A surface treatment apparatus according to claim 15, wherein the ratio of the power (W) of the means for generating plasma to the volume (cc) of the plasma generation space is 0.1 W / cc or less. 25. A surface treatment apparatus according to claim 15, wherein the gas generating plasma contains at least one of chlorine, BCl3, and HCl. 26. A surface treatment apparatus according to claim 15, wherein the gas generating plasma is chlorine and oxygen, HBr and oxygen, or a mixed gas of chlorine, HBr and oxygen. 27. A surface treatment apparatus according to claim 15, wherein a gas containing carbon is added to the gas for generating plasma. 28. The surface treatment method according to claim 1,
The fine pattern has a line and space width of 1μ each.
m or less and an aspect ratio of 1 or more. 29. The surface treatment method according to claim 15, wherein the fine pattern has a line and space width of 1 μm or less and an aspect ratio of 1 or more.