KR100519532B1 - Test circuit - Google Patents

Abstract

The present invention relates to a test circuit, a control unit for generating a first control signal and a second control signal for a multi-DUT test according to a probe test enable signal and a probe test clock signal, and a plurality of clock enable signals. A plurality of input / output buffers for inputting and outputting data through input / output pads, a plurality of control signals according to a plurality of operations, and data between the plurality of input / output buffers and a plurality of input / output buses according to the first and second control signals Test circuits are presented that reduce the cost of test by reducing probe test time without upgrading test equipment, including multiplexers for delivery.

Description

Test circuit

TECHNICAL FIELD The present invention relates to test circuits, and more particularly, to test circuits for multi device under test (DUT).

1 is a configuration diagram schematically illustrating a test circuit of a general NAND flash memory device, and FIGS. 2 to 5 are waveform diagrams in respective operations.

Referring to FIG. 1, a plurality of input / output buffers 10 input / output data IO <0: 7> through a plurality of input / output pads IOPAD <0: 7> according to a clock enable signal CE #. . The plurality of input / output multiplexers 20 control signals according to a plurality of operations, for example, a write enable signal WE #, a read enable signal RE #, an address latch enable signal ALE, and an instruction latch enable. The input / output data IO <0: 7> is transferred between the plurality of input / output buffers 10 and the plurality of input / output buses IOBUS <0: 7> according to the signal CLE.

The general test circuit configured as described above is operated with a waveform as shown in FIGS. 2 to 5, wherein FIG. 2 is a waveform diagram of an address latch operation, FIG. 3 is a waveform diagram of an instruction latch operation, and FIG. 4 is a data latch. 5 is a waveform diagram of a data read operation.

As shown in FIG. 2, when the address latch enable signal ALE is at a high level and the write enable signal WE # transitions from a low level to a high level, the input latch pads IOPAD <0: 7> are connected to each other. A plurality of input addresses are loaded on the input / output bus IOBUS <0: 7>. As shown in FIG. 3, when the command latch enable signal CLE is at a high level and the write enable signal WE # transitions from a low level to a high level, the input / output pads IOPAD <0: 7> A plurality of commands inputted through are loaded on the input / output bus (IOBUS <0: 7>). In addition, as shown in FIG. 4, when the write enable signal WE # transitions from the low level to the high level, a plurality of data is transferred through the I / O pads IOPAD <0: 7>. >). Meanwhile, as shown in FIG. 5, when the read enable signal RE # transitions from the high level to the low level, a plurality of data output through the input / output bus IOBUS <0: 7> is output to the input / output pad IOPAD < 0: 7>).

The conventional test circuit constructed and operated as described above can test 10 dies because the device has 8 input / output pins to perform the test in a device having 80 input / output pins.

Thus, the conventional test circuit simply tested several dies using all existing pins when performing a wafer test. This wafer test method requires a lot of test time and test cost because the number of pins increases, the number of dies must be reduced.

SUMMARY OF THE INVENTION An object of the present invention is to provide a test circuit that can reduce the cost of test by allowing the number of dies to be tested simultaneously by allowing the test to be performed using fewer pins in circuit.

Another object of the present invention is to test a device having a × 8, × 16 structure using only four pins instead of eight or sixteen pins, thereby simultaneously testing two or four times the die during wafer testing. It is to provide a test circuit that enables it.

The test circuit according to the present invention includes a control unit for generating a first control signal and a second control signal for the multi-DUT test according to the probe test enable signal and the probe test clock signal, and a plurality of input / output pads according to the clock enable signal. A plurality of input / output buffers for inputting / outputting data through the plurality of inputs, a plurality of control signals according to a plurality of operations, and data between the plurality of input / output buffers and the plurality of input / output buses according to the first and second control signals. It includes a number of multiplexers for the purpose.

The control unit generates a probe test clock toggle signal when the probe test enable signal is applied at a high level and the probe test clock signal is toggled to perform a multi-DUT test, and the probe test clock toggle signal is at a low level. When the probe test clock signal becomes the first control signal, the probe test clock signal becomes the second control signal when the probe test clock toggle signal is at a high level.

The plurality of control signals include an address latch enable signal for an address latch operation, an instruction latch enable signal for an instruction latch operation, a write enable signal for a data latch operation, and a read enable signal for a data read operation. .

Hereinafter, with reference to the accompanying drawings will be described an embodiment of the present invention;

6 is a schematic diagram of a test circuit for multi-DUT testing of a NAND flash memory device in accordance with the present invention.

Referring to FIG. 6, the controller 100 receives a probe test enable signal PTEN and a probe test clock signal PTCK to input a first control signal PTCKL and a second control signal PTCKH for a multi-DUT test. Outputs The plurality of input / output buffers 200 input / output data IO <0: 3> through the plurality of input / output pads IOPAD <0: 3> according to the clock enable signal CE #. The multiplexer 300 includes control signals according to a plurality of operations, for example, a write enable signal WE #, a read enable signal RE #, an address latch enable signal ALE, and a command latch enable signal. Between the plurality of input / output buffers 200 and the plurality of input / output buses IOBUS <0: 7> according to the CLE and the first control signal PTCKL or the second control signal PTCKH output from the controller 100. The data (IO <0: 3>) is divided and transmitted.

A driving method of the controller 100 in the test circuit for the multi-DUT test according to the present invention configured as described above will be described with reference to FIG. 7.

In order to perform the multi-DUT test, the probe test enable signal PTEN is applied at a high level, and when the probe test clock signal PTCK is toggled, the probe test clock toggle signal PTCK_TOGGLE is generated. The probe test clock signal PTCK becomes the first control signal PTCKL when the probe test clock toggle signal PTCK_TOGGLE is at the low level, and the probe test clock signal PTCK when the probe test clock toggle signal PTCK_TOGGLE is at the high level. ) Becomes the second control signal PTCKH. That is, when the probe test clock toggle signal PTCK_TOGGLE is at the low level, the second control signal PTCKH is at a low level and the first control signal PTCKL is output with a signal having the same phase as the probe test clock signal PTCK. On the other hand, when the probe test clock toggle signal PTCK_TOGGLE is at the high level, the first control signal PTCKL is at a low level and the second control signal PTCKH is output with a signal having the same phase as the probe test clock signal PTCK.

The test circuit for the multi-DUT test according to the present invention configured as described above is performed with a waveform as shown in Figures 8 to 11, Figure 8 is a waveform diagram of the address latch operation, Figure 9 is a waveform of the command latch operation 10 is a waveform diagram of a data latch operation, and FIG. 11 is a data read operation.

Referring to FIG. 8, when the probe test enable signal PTEN is applied at a high level and the probe test clock signal PTCK is toggled, as shown in FIG. 11, the probe test clock toggle signal PTCK_TOGGLE is generated in the first cycle. Low level, high level in the second cycle. Therefore, when the address latch enable signal ALE is applied at the high level and the write enable signal WE # is applied at the low level, and the probe test clock signal PTCK is toggled, the probe test clock toggle signal PTCK_TOGGLE is performed in the first cycle. Becomes a low level, and a 4-bit low address input through the I / O pads IOPAD <0: 3> is placed on the I / O bus IOBUS <0: 3> through the I / O buffer 200 and the I / O multiplexer 300. In the second cycle, the probe test clock toggle signal PTCK_TOGGLE is at a high level so that a 4-bit high address input through the I / O pads IOPAD <0: 3> is inputted to the I / O buffer 200 and the I / O multiplexer 300. Will be loaded on the I / O bus (IOBUS <4: 7>). Therefore, all 8 bits of address are carried.

Referring to FIG. 9, when the probe test enable signal PTEN is high level and the probe test clock signal PTCK is toggled, as shown in FIG. 7, the probe test clock toggle signal PTCK_TOGGLE is low level in the first cycle. In the second cycle, it goes high. Therefore, if the command latch enable signal CLE is at a high level, the write enable signal WE # is at a low level, and the probe test clock signal PTCK is toggled, the probe test clock toggle signal PTCK_TOGGLE is low at the first cycle. At the level, a 4-bit low command input through the I / O pads IOPAD <0: 3> is loaded on the I / O bus IOBUS <0: 3> through the I / O buffer 200 and the I / O multiplexer 300. In the second cycle, the probe test clock toggle signal PTCK_TOGGLE is at a high level, and a 4-bit high command input through the I / O pads IOPAD <0: 3> is inputted through the I / O buffer 200 and the I / O multiplexer 300. It is loaded on the I / O bus (IOBUS <4: 7>). Therefore, all 8-bit instructions are carried.

Referring to FIG. 10, when the probe test enable signal PTEN is at a high level and the probe test clock signal PTCK is toggled, as shown in FIG. 7, the probe test clock toggle signal PTCK_TOGGLE is at a low level in the first cycle. In the second cycle, it goes high. Therefore, when the write enable signal WE # is at the low level and the probe test clock signal PTCK is toggled, the probe test clock toggle signal PTCK_TOGGLE is at the low level in the first cycle, and thus the input / output pad IOPAD <0: 3> 4 bit data inputted through the I / O buffer 200 and the I / O multiplexer 300 are loaded on the I / O bus IOBUS <0: 3>, and the probe test clock toggle signal PTCK_TOGGLE is high in the second cycle. At the level, 4-bit data input through the input / output pads IOPAD <0: 3> are loaded on the input / output bus IOBUS <4: 7> through the input / output buffer 200 and the input / output multiplexer 300. Therefore, all 8 bits of data are carried.

Referring to FIG. 11, when the probe test enable signal PTEN is high level and the probe test clock signal PTCK is toggled, the probe test clock toggle signal PTCK_TOGGLE is low level in the first cycle as shown in FIG. 7. In the second cycle, it goes high. If the read enable signal RE # is at a low level and the probe test clock signal PTCK is toggled, the probe test clock toggle signal PTCK_TOGGLE is at a low level in the first cycle, so that the input / output bus IOBUS <0: 3> 4-bit low data is read through the I / O multiplexer 300, I / O buffer 200, and I / O pads (IOPAD <0: 3>), and in the second cycle, the probe test clock toggle signal (PTCK_TOGGLE) is at high level, 4-bit high data of (IOBUS <4: 7>) is read through the input / output multiplexer 300, the input / output buffer 200, and the input / output pads IOPAD <0: 3>.

In this way, all input / output signals can be input / output using only four input / output pins.

As described above, according to the present invention, by configuring the test circuit to perform the multi-DUT test using the limited input / output channels of the test equipment as it is, the test cost can be reduced by reducing the probe test time without upgrading the test equipment.

1 is a schematic configuration diagram of a conventional test circuit.

2 to 5 are operational waveform diagrams of a conventional test circuit.

6 is a schematic diagram of a test circuit according to the present invention;

7 is an operational waveform diagram of a controller constituting a test circuit according to the present invention;

8 to 11 are operational waveform diagrams of the test circuit according to the present invention.

<Explanation of symbols for the main parts of the drawings>

10 and 200: I / O buffer 20 and 300: I / O multiplexer

100: control unit

Claims (3)

A control unit for generating a first control signal and a second control signal for the multi-DUT test according to the probe test enable signal and the probe test clock signal; A plurality of input / output buffers for inputting / outputting data through the plurality of input / output pads according to the clock enable signal; And a plurality of multiplexers for dividing and transferring data between the plurality of input / output buffers and the plurality of input / output buses according to the plurality of control signals and the first and second control signals. 2. The probe test clock signal of claim 1, wherein the control unit generates a probe test clock toggle signal when the probe test enable signal is applied at a high level and the probe test clock signal is toggled to perform a multi-DUT test. The probe test clock signal becomes the first control signal when the toggle signal is at a low level, and the probe test clock signal becomes the second control signal when the probe test clock toggle signal is at a high level. The method of claim 1, wherein the plurality of control signals include an address latch enable signal for an address latch operation, an instruction latch enable signal for an instruction latch operation, a write enable signal for a data latch operation, and a read for a data read operation. A test circuit comprising an enable signal.