CN117706129A - System and method for using CXL test devices to increase parallelism - Google Patents

Abstract

Systems and methods for using CXL test devices to increase parallelism are disclosed. Embodiments of the present invention may selectively enable testing of devices during testing using a multiplexer circuit disposed between CXL1.1CPU and the DUT, either 16-channel (x 16) or 8-channel (x 8). In this way, parallelism and test efficiency are significantly improved over existing methods that can only test devices using 8 channels of the CXL1.1 CPU.

Description

System and method for using CXL test devices to increase parallelism

Cross Reference to Related Applications

This patent application claims priority and benefit from U.S. provisional patent application No. 63/407,058 entitled "improvement of CXL bus protocol to increase parallelism (also known as CXL 1.1x8 support)" filed on day 9, 2022 and U.S. provisional patent application No. 63/439,489 entitled "system and method for using CXL test devices to increase parallelism" filed on day 17, 2023, the entire contents of which are incorporated herein by reference.

Technical Field

Embodiments of the present invention generally relate to the field of device testing. More particularly, embodiments of the invention relate to methods and systems for testing a device under test (device under test, DUT) using a computational fast link (Compute Express Link, CXL).

Background

The device under test (or device under test) is typically tested to determine the performance and consistency of the device before the device is sold. For example, a variety of test cases may be used to test the DUT and the results of the test cases may be compared to expected output results. When the result of the test case does not match a satisfactory value or range of values, the device may be considered a failed device or have an abnormal value, and the device may be classified based on performance or the like.

DUTs are typically tested by automated or Automated Test Equipment (ATE) that may be used to perform complex tests using software and automation to improve test efficiency. A DUT may be any type of semiconductor device, wafer, or component intended to be integrated into an end product, such as a computer, network interface, or Solid State Drive (SSD). By using ATE to remove defective or unsatisfactory chips at the time of manufacture, the quality of the yield can be significantly improved.

Computing quick links (Compute Express Link) are open standards for high speed CPU to device and CPU to memory connections designed for high performance data center computers. CXLs build on the physical and electrical interfaces of speed PCI (PCI Express) and include PCIe-based block input/output protocols and new cache coherency protocols for accessing system memory and device memory. Recently, improvements have been made to the CXL bus protocol in CXL 2.0, allowing devices of different widths to be tested using 16 bus lanes (PCIe bus lanes) in parallel. However, existing processors that support CXL1.1 at most cannot take advantage of this improvement in multiport testing using existing methods, and are typically limited to testing devices using 16 channels in parallel, which limits the parallelism and efficiency of the test.

Disclosure of Invention

Thus, there is a need for a method of testing devices using CXL1.1 that can utilize all 16 channels available under the modified CXL bus protocol for parallel testing. Embodiments of the present invention may selectively enable configurations that allow 16-channel testing (x 16) of one DUT in parallel, or 8-channel testing (x 8) of two DUTs in parallel, using multiplexers of an expansion board located between the CPU and the DUTs during testing. In this way, parallelism and test efficiency are significantly improved over existing methods that can only test devices using 16 channels of the CXL1.1 CPU.

According to one embodiment, a circuit for forking a processor bus is disclosed. The circuit comprises: a plurality of input ports for coupling to four n-bit buses from the processor, wherein each of the four buses includes n bits and includes a lower half and an upper half, respectively; a plurality of output ports for providing four buses, wherein each of the four buses from the plurality of output ports comprises n/2 bits; and a multiplexing circuit coupled to the plurality of input ports and to the plurality of output ports, the multiplexing circuit being responsive to a common select line for selectively implementing one of two configurations, the two configurations comprising: a first configuration coupling the plurality of output ports to only a lower half of the four buses from the processor; and a second configuration coupling the plurality of output ports to a lower half and an upper half of at least two of the four buses from the processor.

According to some embodiments, the multiplexing circuit comprises a plurality of high-speed multiplexers, each high-speed multiplexer coupled to a common select line.

According to some embodiments, the plurality of high-speed multiplexers includes two multiplexers.

According to some embodiments, n is 16.

According to some embodiments, the first configuration is operable to couple the processor to four Devices Under Test (DUTs), each of the four DUTs comprising an n/2 bit wide bus. In this example, n=16.

According to some embodiments, the second configuration is operable to couple the processor to two DUTs, each of which comprises an n-bit wide bus. In this example, n=16.

According to some embodiments, the first configuration and the second configuration are operable to dynamically configure based on a value of the select line.

According to various embodiments, a tester circuit for testing a Device Under Test (DUT) is disclosed. The tester circuit includes: a processor having four n-bit buses; a plurality of input ports coupled to four n-bit buses of the processor, wherein each of the four n-bit buses includes a lower half and an upper half; a plurality of output ports for providing four n/2 bit buses; and a high-speed multiplexing circuit coupled to the plurality of input ports and to the plurality of output ports, the high-speed multiplexing circuit being responsive to a common select line for selectively implementing one of two configurations, the two configurations comprising: a first configuration coupling the plurality of output ports to only a lower half of the four n-bit buses from the processor; and a second configuration coupling the plurality of output ports to a lower half and an upper half of at least two of the four n-bit buses from the processor.

According to some embodiments, the high-speed multiplexing circuit includes a plurality of high-speed multiplexers, each high-speed multiplexer coupled to a common select line.

According to some embodiments, n is 16.

According to some embodiments, the first configuration is operable to couple the processor to four DUTs to test them, each of the four DUTs comprising an n/2 bit wide bus.

According to some embodiments, the second configuration is operable to couple the processor to two device DUTs to test them, each of the two DUTs comprising an n-bit wide bus.

According to some embodiments, the first configuration and the second configuration are operable to be dynamically configured.

In accordance with another embodiment, a method of forking a bus of a processor for testing is disclosed. The method comprises the following steps: the processor generates signals through at least four n-bit buses; in a first mode of operation, the multiplexer circuit is coupled to at least four n-bit buses of the processor and is disposed external to the processor, generating signals through four n/2-bit output buses. In a first mode of operation, the processor simultaneously tests four Devices Under Test (DUTs) with four n/2 bit output buses. In a second mode of operation, the multiplexer circuit generates signals over two n-bit output buses and the processor simultaneously tests two DUTs with the two n-bit output buses. The method further comprises the steps of: the first mode of operation and the second mode of operation are switched by switching the value of a select line coupled to the multiplexing circuit.

According to some embodiments, the multiplexer circuit includes a high-speed multiplexer commonly coupled to the select lines.

According to some embodiments, the high-speed multiplexer includes two multiplexers.

According to some embodiments, n=16.

According to some embodiments, the first mode of operation provides the lower half of the 4 n-bit buses from the processor through only four n/2-bit output buses.

According to some embodiments, the second mode of operation provides two of the 4 n-bit buses from the processor through two n-bit output buses.

According to some embodiments, the second mode of operation provides two of the 4 n-bit buses from the processor through two n-bit output buses.

Drawings

The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments of the invention and together with the description, serve to explain the principles of the invention:

FIG. 1 is a block diagram of a tester system and circuitry for selectively enabling configurations supporting 8x or 16x device testing using a multiplexer circuit in a first configuration, according to an embodiment of the present invention.

FIG. 2 is a block diagram of a tester system and circuitry for selectively enabling configurations that support 8x or 16x device testing using a multiplexer circuit in a second configuration, according to an embodiment of the invention.

FIG. 3 is a flowchart depicting an exemplary sequence of computer-implemented steps of a computer-controlled process for automatically testing multiple DUTs in parallel using a multiplexer circuit to selectively enable 8x or 16x device testing.

FIG. 4 depicts an exemplary tester computer system platform (e.g., a tester system) on which embodiments of the invention may be implemented.

Detailed Description

Reference will now be made in detail to several embodiments. While the subject matter will be described in conjunction with alternative embodiments, it will be understood that they are not intended to limit the claimed subject matter to these embodiments. On the contrary, the claimed subject matter is intended to cover alternatives, modifications and equivalents, which may be included within the spirit and scope of the claimed subject matter as defined by the appended claims.

Furthermore, in the following detailed description, numerous specific details are set forth in order to provide a thorough understanding of the claimed subject matter. However, it will be recognized by one skilled in the art that the embodiments may be practiced without these specific details or with equivalents thereof. In other instances, well-known methods, procedures, components, and circuits have not been described in detail so as not to unnecessarily obscure aspects and features of the subject matter.

Portions of the detailed description that follows are presented and discussed in terms of a method. Although the steps and sequence of steps thereof are disclosed in a diagram describing the operation of the method (e.g., fig. 3), these steps and sequence are exemplary. Embodiments are well suited to performing various other steps or variations of the steps recited in the flowcharts of the figures herein, and in a different order than depicted and described herein.

Some portions of the detailed descriptions are presented in terms of procedures, steps, logic blocks, processing, and other symbolic representations of operations on data bits that can be performed on computer memory. These descriptions and representations are the means used by those skilled in the data processing arts to most effectively convey the substance of their work to others skilled in the art. A procedure, computer-executed step, logic block, process, etc., is here, and generally, conceived to be a self-consistent sequence of steps or instructions leading to a desired result. The steps are those requiring physical manipulations of physical quantities. Usually, though not necessarily, these quantities take the form of electrical or magnetic signals capable of being stored, transferred, combined, compared, and otherwise manipulated in a computer system. It has proven convenient at times, principally for reasons of common usage, to refer to these signals as bits, values, elements, symbols, characters, terms, numbers, parameters, or the like.

It should be borne in mind, however, that all of these and similar terms are to be associated with the appropriate physical quantities and are merely convenient labels applied to these quantities. Unless specifically stated otherwise as apparent from the following discussions, it is appreciated that throughout the discussion, discussions utilizing terms such as "accessing," "writing," "including," "storing," "transmitting," "associating," "identifying," "encoding," "marking," or the like, refer to the action and processes of a computer system, or similar electronic computing device, that manipulates and transforms data represented as physical (electronic) quantities within the computer system's registers and memories into other data similarly represented as physical quantities within the computer system memories or registers or other such information storage, transmission or display devices.

Some embodiments may be described in the general context of computer-executable instructions, such as program modules, executed by one or more computers or other devices. Generally, program modules include routines, algorithms, programs, objects, components, data structures, etc. that perform particular tasks or implement particular abstract data types. Typically, the functionality of the program modules may be combined or distributed as desired in various embodiments.

DUT parallel testing using CXL1.1 processor

Embodiments of the present invention may use a multiplexer circuit disposed between the CXL1.1CPU and the DUT to selectively enable 16-channel (x 16) or 8-channel (x 8) device testing during testing. In this way, parallelism and test efficiency are significantly improved compared to existing methods of 8-channel testing devices that can only use CXL1.1 CPU. In one embodiment, the multiplexer is a high-speed multiplexer.

FIG. 1 depicts an exemplary tester system 100 coupled to multiplexers 135 and 140 for parallel testing of DUTs 115 and 120 using 16 channels for each DUT. The tester system 100 includes a CXL1.1cpu 105 that is capable of communicating with peripheral devices using the enhanced CXL protocol. In the example of fig. 1, CPU 105 uses 16-bit output ports PE1, PE2, PE3, and PE4 to test devices. Output ports PE1, PE2, PE3, and PE4 each provide 16 PCIe lanes for testing the DUT by sending data or commands to be executed by the DUT. Compared with the 8 channels used in the existing method, the 16 channels are used, and the parallelism and the testing efficiency are remarkably improved. CPU 105 may also test four DUTs in parallel using 8 channels for each DUT to test more devices simultaneously (see fig. 2). The DUT is typically placed in a socket of a device interface board that is mounted on the site module. Each DUT may be independently tested by a separate test program executed by CPU 105.

The outputs PE1, PE2, PE3, and PE4 of the CPU 105 are sent to a multiplexer circuit 130, the multiplexer circuit 130 including multiplexers 135 and 140 coupled to a common select line 145. Each output port may be divided into high order bits (high) and low order bits (low). Typically, the output port is 16 bits, divided into two 8 bit lanes. Importantly, for x16 testing, all inputs received by the device must come from the same CPU port.

In the example of FIG. 1, multiplexer 135 outputs PE3-HIGH to DUT 115 in the x16 mode of operation and multiplexer 140 outputs PE4-HIGH to DUT 120. Output port PE3 is used to test DUT 115 where PE3-HIGH transmits 8 HIGH order bits and PE3-LOW transmits 8 LOW order bits. Similarly, output port PE4 is used to test DUT 120, where PE4-HIGH sends 8 HIGH order bits and PE4-LOW sends 8 LOW order bits. During the x16 test, output ports PE1 and PE2 are typically not used. As discussed in more detail below, to test four DUTs in parallel using x8 (FIG. 2), multiplexer 135 outputs PE2-LOW to one DUT and PE3-LOW to a second DUT. Similarly, multiplexer 140 outputs PE1-LOW to the third DUT and PE4-LOW to the other DUT.

The multiplexer circuit 130 may also include a current buffer at each output to prevent the signal transmitted through the multiplexer circuit 130 from being affected by differences in the amount of current drawn by the output load.

Multiplexers 135 and 140 are operated using common select line 145 for selecting the output based on either a high value or a low value. Select logic 150 generates signals for switching between the inputs of multiplexers 135 and 104. Selection logic 150 may be performed by a test program executing on CPU 105 or by a separate component (e.g., a switch or module), or it may originate from a processor.

According to some embodiments, if select line 145 is LOW (e.g., 0), then 8 LOW order bits are selected for output (e.g., PE2-LOW and PE 1-LOW), and each of the four DUTs receives input from eight channels; if the select line 145 is HIGH (e.g., 1), then 8 HIGH order bits are selected for output (e.g., PE3-HIGH and PE 4-HIGH) so that when combined with PE3-LOW and PE4-LOW, each of the two DUTs receives input from 16 channels.

FIG. 2 depicts an exemplary tester system 200 coupled to multiplexers 235 and 240 for parallel testing of DUTs 215, 220, 225, and 230 using 8 channels for each DUT. Tester system 200 includes a CXL1.1cpu 205 that is capable of communicating with peripheral devices using the enhanced CXL protocol. In the example of fig. 2, CPU 205 uses output ports PE1, PE2, PE3, and PE4 to test devices. Output ports PE1, PE2, PE3, and PE4 each provide 16 PCIe lanes for testing the DUT by sending data or commands to be executed by the DUT. CPU 205 may also test four DUTs in parallel using 8 channels for each DUT to test more devices simultaneously. The DUT is typically placed in a socket of a device interface board that is mounted on the site module. Each DUT may be independently tested by a separate test program executed by CPU 205.

According to some embodiments, when two DUTs are available for x16 testing and 4 DUTs are available for x8 testing, all 6 DUTs may be coupled to the output of multiplexer circuit 235 and the output may be provided to the DUTs according to the value of select line 245 generated by select logic 250. In this manner, tester system 200 may switch between x16 and x8 modes of operation without shutdown.

In the example of FIG. 2, to test four DUTs in parallel, multiplexers 235 and 240 receive a LOW value on select line 245 and bits PE2-LOW and PE1-LOW are passed as outputs. In this way, DUT 215 receives input from PE2-LOW, DUT 220 receives input from PE3-LOW, DUT 220 receives input from PE1-LOW, and DUT 225 receives input from PE4-LOW, each using 8 channels. In this way, each of the four DUTs may be tested in parallel to increase speed and efficiency.

FIG. 3 is a flow chart depicting an exemplary automated parallel DUT testing procedure 300 performed by a CXL1.1 processor for testing multiple DUTs in either a x8 or x16 configuration using an enhanced CXL bus protocol in accordance with an embodiment of the invention.

At step 305, a signal is generated over a plurality of n-bit buses using a (CXL 1.1) processor.

At step 310, signals are generated over four n/2 bit output buses using a multiplexer circuit coupled to the processor.

In step 315, four DUTs are simultaneously tested with four n/2 bit output buses using the processor in a first mode of operation (x 8).

At step 320, a signal is generated at the multiplexer circuit over two n-bit output buses.

At step 325, two DUTs are tested simultaneously with two n-bit output buses using the processor.

In step 330, the value of the select line coupled to the multiplexing circuit is changed to switch between the first mode of operation and the second mode of operation.

Exemplary test System

Embodiments of the present invention relate to an electronic system having a CLX 1.1 processor and enabling the processor to test multiple DUTs in parallel using an enhanced CXL bus protocol and multiplexer circuitry to selectively enable x8 or x16 device testing, thereby improving parallelism and efficiency over existing approaches. In the example of fig. 4, exemplary computer system 412 may be a test system that includes a Central Processing Unit (CPU) 401 and an operating system for running software applications. The CPU 401 may test multiple DUTs 411 in parallel by executing a test program that sends commands and/or data to the DUTs 411, e.g., the DUTs 411 may be placed in sockets of a device interface board that is installed on a site module. According to some embodiments, the CPU may selectively enable x8 and x16 testing of DUT 411 by configuring multiplexer circuit 410 with select lines. An output port of the CPU 401 may be coupled to a multiplexer circuit 410 and an output of the multiplexer circuit 410 is passed to the DUT 411 (or device interface board, site module, etc.), for example, to test the functionality and performance of the DUT 411. The 4 output ports of the CPU 401 connected to the output circuit 410 typically each include 16 channels (64 channels in total). Furthermore, according to some embodiments, computer system 412 may include 2 CPUs for a total of 8 output ports and 128 channels.

Random access memory 402 and read only memory 403 store applications and data for use by CPU 401. The data storage device 404 provides non-volatile storage for applications and data and may include fixed disk drives, removable disk drives, flash memory devices, and CD-ROM, DVD-ROM, or other optical storage devices. The data storage 404 or memory 402/403 may store historical and real-time test data (e.g., test results, limits, calculations, etc.). Optional user inputs 406 and 407 include devices (e.g., a mouse, joystick, camera, touch screen, keyboard, and/or microphone) that communicate input from one or more users to computer system 412. Communication or network interface 408 allows computer system 412 to communicate with other computer systems, networks, or devices via an electronic communication network, including wired and/or wireless communications, and including an intranet or the internet.

Optional display device 409 may be any device capable of displaying visual information (e.g., a final scan report) in response to a signal from computer system 412 and may include, for example, a flat panel touch sensitive display. Components of computer system 412, including CPU 401, memory 402/403, data storage 404, user input devices 406, and graphics subsystem 405, may be coupled via one or more data buses 400.

Embodiments of the invention are thus described. While the present invention has been described in particular embodiments, it should be appreciated that the present invention should not be construed as limited by such embodiments, but rather construed according to the below claims.

Claims (20)

1. A circuit for forking a bus channel of a processor, the circuit comprising:

a plurality of input ports for coupling to four n-bit buses from the processor, wherein each of the four n-bit buses includes a lower half and an upper half;

a plurality of output ports for providing four n/2 bit buses;

a multiplexing circuit coupled to the plurality of input ports and to the plurality of output ports, the multiplexing circuit being responsive to a common select line for selectively implementing one of two configurations, the two configurations comprising:

a first configuration coupling the plurality of output ports to only a lower half of the four n-bit buses from the processor; and

a second configuration coupling the plurality of output ports to a lower half and an upper half of at least two of the four n-bit buses from the processor.

2. The circuit of claim 1, wherein the multiplexing circuit comprises a plurality of high-speed multiplexers, each high-speed multiplexer coupled to the common select line.

3. The circuit of claim 2, wherein the plurality of high-speed multiplexers comprises two multiplexers.

4. The circuit of claim 1, wherein n is 16.

5. The circuit of claim 1, wherein the first configuration is operable to couple the processor to four Devices Under Test (DUTs), each of the four DUTs comprising an n/2 bit wide bus.

6. The circuit of claim 5, wherein the second configuration is operable to couple the processor to two DUTs, each of the two DUTs comprising an n-bit wide bus.

7. The circuit of claim 6, wherein the first configuration and the second configuration are operable to be dynamically configured based on a value of the select line.

8. A tester circuit for testing a Device Under Test (DUT), the tester circuit comprising:

the processor, the processor having four n-bit buses;

a plurality of input ports coupled to the four n-bit buses of the processor, wherein each of the four n-bit buses includes a lower half and an upper half;

a plurality of output ports for providing four n/2 bit buses; and

a high speed multiplexing circuit coupled to the plurality of input ports and to the plurality of output ports, the high speed multiplexing circuit being responsive to a common select line for selectively implementing one of two configurations, the two configurations comprising:

a first configuration coupling the plurality of output ports to only a lower half of the four n-bit buses from the processor; and

a second configuration coupling the plurality of output ports to a lower half and an upper half of at least two of the four n-bit buses from the processor.

9. The tester circuit of claim 8 wherein the multiplexing circuit comprises a plurality of high speed multiplexers, each high speed multiplexer coupled to the common select line.

10. The tester circuit of claim 8 wherein n is 16.

11. The tester circuit of claim 8 wherein the first configuration is operable to couple the processor to four DUTs to test them, each of the four DUTs comprising an n/2 bit wide bus.

12. The tester circuit of claim 11 wherein the second configuration is operable to couple the processor to two device DUTs to test them, each of the two DUTs comprising an n-bit wide bus.

13. The circuit of claim 8, wherein the first configuration and the second configuration are operable to be dynamically configured.

14. A method of forking a bus of a processor for testing, the method comprising:

the processor generates signals through at least four n-bit buses;

in a first mode of operation, a multiplexer circuit is coupled to the at least four n-bit buses of the processor and disposed external to the processor, generating signals through four n/2-bit output buses;

in the first mode of operation, simultaneously testing four Devices Under Test (DUTs) with the four n/2 bit output buses using the processor;

in a second mode of operation, the multiplexer circuit generates signals over two n-bit output buses;

in the second mode of operation, simultaneously testing two DUTs with the two n-bit output buses using the processor; and

switching between the first mode of operation and the second mode of operation is performed by switching a value of a select line coupled to the multiplexing circuit.

15. The method of claim 14, wherein the multiplexer circuit comprises a high-speed multiplexer commonly coupled to the select line.

16. The method of claim 15, wherein the high-speed multiplexer comprises two multiplexers.

17. The method of claim 14, wherein n = 16.

18. The method of claim 14, wherein the first mode of operation provides a lower half of the 4 n-bit buses from the processor only through the four n/2-bit output buses.

19. The method of claim 14, wherein the second mode of operation provides two of the 4 n-bit buses from the processor through the two n-bit output buses.

20. The method of claim 18, wherein the second mode of operation provides two of the 4 n-bit buses from the processor through the two n-bit output buses.