KR100517126B1 - Single electron transistor with controllable quantum dot size, an integration of single electron transistor and double-gate MOSFET, and fabrication method thereof, respectively - Google Patents

Abstract

According to the present invention, a single-electron transistor and a double-gate MOSFET capable of simultaneously adjusting the size of a quantum dot and a double-gate MOSFET for complementing the functions of the single-electron transistor on the same SOI substrate through the same process are provided. It relates to the respective manufacturing method.

According to the present invention, a single-electron transistor includes an insulator stacked on top of a substrate support; Source and drain regions formed on the insulator spaced apart from each other by single crystal silicon; A thin channel connecting the source and the drain to each other and formed of single crystal silicon; A first insulating film for forming the channel; A first gate insulating film electrically separating the source and drain regions while making most of both sidewalls of the channel a transmission barrier; A first gate stacked on the first gate insulating film; A second gate insulating layer forming a quantum dot with remaining portions of the sidewalls of the channel where the first gate is not formed; A single-electron transistor comprising a second gate stacked between the second gate insulating layer and the source and drain regions over the first insulating layer, and compared to the prior art, the weakening of the tunneling barrier caused by the first gate in the lower portion of the silicon channel is reduced. While blocking, the size of the quantum dot may be adjusted according to the thickness of the first gate material and the degree of transient etching. In addition, a structure of a single-electron transistor and a double-gate MOSFET capable of simultaneously integrating a FinFET-type double gate MOSFET for increasing signal amplification of a single-electron transistor on the same SOI substrate through the same process and a manufacturing method thereof are provided.

Description

Single electron transistor with controllable quantum dot size, an integration of single electron transistor and double- gate MOSFET, and fabrication method approximately, respectively}

According to the present invention, a single-electron transistor and a double-gate MOSFET capable of simultaneously adjusting the size of a quantum dot and a double-gate MOSFET for complementing the functions of the single-electron transistor on the same SOI substrate through the same process are provided. It relates to the respective manufacturing method.

The single-electron transistor is a new concept transistor using nanometer-sized microquantum dots, and much research has been conducted because it is advantageous for low power consumption and high integration as a next-generation device after the MOSFET. Since the size of quantum dots has the greatest influence on the operating temperature, it is necessary to reduce the size of the quantum dots in order to increase the operating temperature. Since reducing the size of the quantum dots exceeds the limitations of current lithography technology, It was difficult to fabricate silicon-based single-electron transistors reproducibly because devices using ultra-fine quantum dots were manufactured by accidental effects, and two gates using two gates to electrically form quantum dots were overcome to overcome these problems. An electron transistor structure (FIG. 1) has been reported. However, conventionally disclosed single-electron transistors have a buried oxide film 12 on the substrate support 11 and a long thin silicon channel 15 between the source 13 and the drain 14 and the silicon oxide film 17 thereon. And the silicon nitride film 16 are stacked and the silicon nitride film is patterned and etched to form a first gate 18. The silicon nitride film 16 is present only on the upper surface of the channel to form an electrical barrier on the upper part of the channel. The second gate insulating film 17 and the second gate 19 of the silicon oxide film are formed thereon to serve to induce electrical quantum dots, so that the tunneling barrier by the first gate is formed only on the upper portion of the channel, There was a problem that the tunneling barrier could be weakened.

In addition, even in the case of a single-electron transistor using two gates, the gain is very small, and it is difficult to apply to a system because it is sensitive to the drain voltage. In order to overcome this problem, there is a need for an integrated technology of single-electron transistors and MOSFETs to amplify signals of single-electron transistors using a conventional MOSFET as a buffer. However, in case of MOSFET fabricated on existing Si substrate or SOI substrate, it is difficult to adequately suppress short channel effect at 20-30 nm size, and advantage of single electron transistor when using long channel length MOSFET for stable MOSFET operation There was a problem that can negatively affect the high density. Therefore, a double gate MOSFET structure that is resistant to short channel effects has been proposed even in a channel of several tens of nm in size. Among them, a dual gate MOSFET having a FinFET structure has been reported that can form two gates across a thin channel perpendicular to a substrate in a self-aligned form using conventional semiconductor processing techniques such as lithography and etching (Figs. 2A to 2C where 21 is a source, 22 is a drain, 23 is an insulating film for channel formation, 24 is a gate, 25 is a channel, 26 is a buried oxide film, and 27 is a gate insulating film). However, they are manufactured in a separate process from the single-electron transistor and then integrated into a single chip, which causes a lot of manufacturing difficulties.

The present invention solves the problem of the weakening of the tunneling barrier caused by the first gate of the conventional single-electron transistor (FIG. 1) and can reduce the size of the quantum dot in the semiconductor process, and a FinFET for complementing the functions of the single-electron transistor. It is an object of the present invention to provide a single-electron transistor and a double-gate MOSFET capable of simultaneously integrating a double gate MOSFET of the same type into the same SOI substrate through the same process, and a manufacturing method of each.

The single-electron transistor for achieving the above object includes an insulator stacked on the substrate support; Source and drain regions formed on the insulator spaced apart from each other by single crystal silicon; A thin channel connecting the source and the drain to each other and formed of single crystal silicon; A first insulating film for forming the channel; A first gate insulating film electrically separating the source and drain regions while making most of both sidewalls of the channel a transmission barrier; A first gate stacked on the first gate insulating film; A second gate insulating layer forming a quantum dot with remaining portions of the sidewalls of the channel where the first gate is not formed; And a second gate stacked between the source and drain regions over the second gate insulating layer and the first insulating layer, and the double gate MOSFET simultaneously manufactured with the single-electron transistor includes an insulator stacked on the substrate support. ; Source and drain regions formed on the insulator spaced apart from each other by single crystal silicon; A thin channel connecting the source and the drain to each other and formed of single crystal silicon; A first insulating film for forming the channel; A first gate insulating layer formed on both sidewalls of the channel and self-aligned; The first gate insulating layer and the first insulating layer surrounding the channel is characterized in that it has a FinFET form consisting of a first gate formed by being stacked between the source and drain regions.

In addition, the method of manufacturing a single electron transistor of the present invention includes a first step of defining single crystal silicon to be used as an active layer in an SOI substrate and forming a fine pattern of a first insulating film in a portion to be a channel; Forming a spacer with a second insulating film on the fine patterns of the single crystal silicon and the first insulating film, and injecting impurities into the single crystal silicon to do source and drain doping; A third step of depositing and patterning a third insulating film on the single crystal silicon on which the first insulating film fine pattern and the second insulating film spacer are formed; A fourth step of forming a channel by removing single crystal silicon of a portion where the first gate is to be formed using the fine patterns of the third insulating film and the first insulating film as a mask; A fifth step of growing a first gate insulating film on sidewalls of the channel, the source, and the drain; Forming a first gate by depositing and etching a material to be used as a first gate on the first gate insulating layer; A seventh step of forming a second gate insulating film on the first gate and on a portion of the remaining channel where the first gate is not covered; And an eighth step of forming a second gate electrode on the second gate insulating film, wherein a method of simultaneously fabricating a single-electron transistor and a double-gate MOSFET includes single crystal silicon to be used as an active layer on the same SOI substrate, respectively. Defining a first pattern of the first insulating film in a portion to be a channel; Forming a spacer with a second insulating film on the fine patterns of the single crystal silicon and the first insulating film, and injecting impurities into each single crystal silicon to do source and drain doping; A third step of depositing a third insulating film on the single crystal silicon on which the first insulating film fine pattern and the second insulating film spacer are formed and patterning the third insulating film so that the channel length of each device is formed differently; A fourth step of forming a channel by removing each single crystal silicon in a portion where the first gate is to be formed using the fine patterns of the third insulating film and the first insulating film as a mask; A fifth step of growing a first gate insulating film on sidewalls of the single crystal silicon sidewalls of the channel, the source, and the drain; Forming a first gate by depositing and etching a material to be used as a first gate on the first gate insulating layer; A seventh step of forming a second gate insulating film on the first gate and on a portion of the remaining channel where the first gate is not covered; And an eighth step of forming a second gate electrode on the second gate insulating film.

Hereinafter, exemplary embodiments of the present invention will be described with reference to the accompanying drawings.

[First Embodiment]

The single-electron transistor proposed in the present invention is formed on an SOI (Silicon On Insulator) substrate composed of an insulator stacked on top of a substrate support (not shown in the drawings. The same applies below) and single crystal silicon grown on the insulator. In addition, the single crystal silicon existing on the buried oxide film 30 of the SOI substrate is left in the portion where the device is to be formed by the photolithography process and the etching process, and the remaining portion is removed (FIG. 3A). At this time, the substrate support may use silicon, and the buried oxide film, which is an insulator of the SOI substrate, may use a silicon oxide film (the same applies hereinafter).

Then, a first insulating film to be used as an etch stop film in a later step is deposited, and a fine pattern 32 of the first insulating film is formed using an ultrafine patterning process (FIG. 3B). In this case, a silicon nitride film, a silicon oxide film, or a stacked structure of each of these films and an amorphous silicon film may be used as the first insulating film. For the fine pattern of the first insulating film, electron beam lithography or a fine patterning technique using sidewalls may be used.

A second insulating film is deposited around the first insulating film having a fine pattern, the spacer 33 is formed by anisotropic etching, and then source and drain doping is performed using an ion implantation process (FIG. 3C). At this time, only the fine pattern of the first insulating layer to be a channel remains in the SOI of the entire active layer without being doped. When the doping process of the source and the drain is performed in the initial process of FIG. 3C, a high dielectric constant material may be used in the first gate insulating layer 36 and a metal may be used in the first gate 37.

In the state of FIG. 3C, the third insulating film 34 is deposited and patterned (FIG. 3D). In this case, the third insulating film must be a material having an excellent etching selectivity with the silicon and the first insulating film, and the material must have little or the same selectivity as the second insulating film. For example, a silicon oxide film can be deposited by chemical vapor deposition using the second insulating film and the third insulating film. In the patterning of the third insulating layer, electron beam lithography or a fine patterning method using sidewalls may be used so that the channel length is larger than twice the thickness of the first gate material.

After patterning the third insulating film in FIG. 3D, when the second and third insulating films are etched by the portion 35 corresponding to the gate size of the device to be manufactured, the first insulating film 32 and the single crystal silicon 31 are exposed ( 3e).

Subsequently, when the single crystal silicon of the portion 35 on which the gate is to be formed is etched using the third insulating film and the first insulating film as a mask, the single crystal silicon 31 is removed except for pad portions and channels of the source and drain (FIG. 3f).

In the state shown in FIG. 3F, the first gate insulating film 36 is grown (FIG. 3G). If a thermal oxidation process is used to grow the first gate insulating film at this time, the thickness of the first gate oxide film (insulating film) growing on the sidewalls of the source and drain in FIG. Since the thickness of the oxide film is approximately three times the thickness of the oxide film, the leakage current due to tunneling between the source or drain and the first gate can be sufficiently suppressed.

After growing the first gate insulating layer 36, a material to be the first gate is deposited and etched to form a first gate 37 (FIG. 3H). In this case, the first gate material may be etched back to leave the first gate in the form of a spacer only on the sidewall portions and the channel sidewall portions of the source and drain. In particular, since the channel sidewall portion has a lower step compared to the sidewalls of the source and drain, when the first gate material is excessively etched, the portion 37 ′ covered by the first gate at the center portion of the channel sidewall according to the degree of etching And portions 32 'that are not. Accordingly, the height of the first gate remaining on the sidewall of the channel may be adjusted according to the degree of excessive etching of the first gate material, thereby controlling the size of the quantum dot.

Finally, a second gate insulating film 38 is formed on and over the first gate 37 and over the remaining channel portion 32 ′ where the first gate is not covered to make a second gate forming a quantum dot. Deposition of the material of the second gate 39 results in the final formation of a single-electron transistor divided into a portion where the potential is controlled by the first gate 37 and a portion where the potential is controlled by the second gate 39 (FIG. 3i). 4A to 4C are cross-sectional views showing the structure of the single-electron transistor, respectively.

Second Embodiment

In order to simultaneously manufacture a single-electron transistor and a double-gate MOSFET proposed in the present invention, a single silicon on insulator (SOI) substrate is first prepared, and the single crystal silicon present on the buried oxide film 50 of the SOI substrate is photographed and etched. In the process, the single crystal silicon 51, 511 is left only in the portion where each element is to be formed, and the remaining portions are removed (Fig. 5A).

Thereafter, a first insulating film to be used as an etch stop layer is deposited in a subsequent step, and fine patterns 52 and 512 of the first insulating film are formed using an ultrafine patterning process (FIG. 5B). In this case, a silicon nitride film, a silicon oxide film, or a stacked structure of each of these films and an amorphous silicon film may be used as the first insulating film. For the fine pattern of the first insulating film, electron beam lithography or a fine patterning technique using sidewalls may be used.

A second insulating film is deposited around the first insulating film having a fine pattern, the spacers 53 and 513 are formed by anisotropic etching, and then source and drain doping is performed using an ion implantation process (FIG. 5C). At this time, only the fine pattern of the first insulating layer to be a channel remains in the SOI of the entire active layer without being doped. When the doping process of the source and drain is performed in the initial process of FIG. 5C, a high dielectric constant material and a first gate metal may be used in the first gate insulating layer.

In the state of FIG. 5C, the third insulating films 54 and 514 are deposited and the third insulating film is patterned so that the channel lengths of the elements are different from each other (FIG. 5D). In this case, the third insulating film must be a material having an excellent etching selectivity with the silicon and the first insulating film, and the material must have little or the same selectivity as the second insulating film. For example, a silicon oxide film can be deposited by chemical vapor deposition using the second insulating film and the third insulating film. In the patterning of the third insulating layer, the channel length is greater than twice the thickness of the first gate material at the position where the single-electron transistor is to be manufactured. Electron beam lithography or a fine patterning method using sidewalls can be used to be smaller than twice.

After patterning the third insulating film in FIG. 5D, when the second and third insulating films are etched by the portions 55 and 515 corresponding to the gate size of each device to be manufactured, the first insulating films 52 and 512 and the single crystal silicon 51 may be etched. , 511 is exposed (FIG. 5E).

Subsequently, when single crystal silicon is etched using the third insulating film and the first insulating film as a mask, the single crystal silicon 51 and 511 are removed from all portions except the pads and the channels of the source and drain (FIG. 5F).

In the state shown in Fig. 5F, the first gate insulating films 56 and 516 are grown (Fig. 5G). If a thermal oxidation process is used to grow the first gate insulating film at this time, the thickness of the first gate oxide film (insulating film) growing on the sidewalls of the source and drain in FIG. Since the thickness of the oxide film is approximately three times the thickness of the oxide film, the leakage current due to tunneling between the source or drain and the first gate can be sufficiently suppressed.

After growing the first gate insulating layer, a material to be the first gate is deposited and etched to form first gates 57 and 517 (FIG. 5H). At this time, the etching of the first gate material is etch-back, leaving only the first gate at the sidewall portion and the channel sidewall portion of the source and drain at the position where the single-electron transistor is to be manufactured, and the position at which the double gate MOSFET is to be manufactured. The first gate may be left between the source and the drain while surrounding the channel. This results in a double gate MOSFET. In addition, in the case of the channel sidewall portion of the single-electron transistor, since it has a lower step compared to the sidewalls of the source and drain, excessive etching of the first gate material may cover the first gate at the center portion of the channel sidewall depending on the degree of etching. There will be a portion 57 'and a portion 52' that is not. Therefore, according to the degree of transient etching of the first gate material, the formation of the double gate MOSFET can be maintained, and the height of the first gate remaining on the channel sidewall of the single-electron transistor can be adjusted to adjust the size of the quantum dot of the single-electron transistor. .

Finally, in order to make the second gate forming the quantum dot of the single electron transistor, a mask defining the second gate is applied only to the single electron transistor (left of FIG. 5H), so that the first gate 57 and the first gate are By forming the second gate insulating film 58 only on the remaining uncovered channel portion 52 'and depositing the second gate 59 material thereon to form the second gate, the first gate 57 A single-electron transistor divided into a portion where the potential is controlled and a portion where the potential is controlled by the second gate 59 is also finally formed (FIG. 5I). Thus, a single-electron transistor and a FinFET type are processed in one process. Double gate MOSFETs will be made simultaneously. 6A to 6D are cross-sectional views showing the configuration of the co-manufactured single-electron transistor and the double gate MOSFET, respectively.

Third Embodiment

3E and 5E, in the process of forming the third insulating film fine pattern of FIGS. 3E and 5E, when the etching selectivity with the first insulating film is bad, the first insulating film is excessively etched to form the silicon channel of FIGS. 3F and 5F. Problems can occur that do not serve as a sufficient mask in the process. That is, in the semiconductor process, when the silicon nitride film is used as the first insulating films 32, 52, and 512, and the silicon oxide film is used as the third insulating films 34, 54, and 514, as shown in FIGS. 3B and 5B, the selectivity between the two is high. Too bad can cause this problem.

In order to solve this problem, instead of using the first insulating layers 32, 52, and 512 serving as channel masks as one material, the materials 52 and 512 having good etching selectivity with respect to silicon may be used as shown in FIG. 7. In addition, a double stack structure is used in which materials 52 " and 512 " having good etching selectivity are placed on the third insulating film. For example, since the silicon oxide film or the silicon nitride film has excellent etching selectivity with respect to single crystal, polycrystal, and amorphous silicon, silicon serves as a mask when etching the third insulating film as shown in FIGS. 3E and 5E, and as shown in FIGS. 3F and 5F. In the silicon etching process, the silicon oxide film or the silicon nitride film may be used as a stacked structure of the polycrystalline / amorphous silicon 52 "and 512" and the silicon oxide film or the silicon nitride film 52 and 512.

[Example 4]

Of the first, second, and third embodiments, the third insulating layer 34, 34 ′, 54, 54 ′, 514, 514 ′ in FIGS. 3I and 5I without performing source / drain doping in FIGS. 3C and 5C. ) And the first insulating films 32, 52, and 512 under the third insulating film are selectively removed, and source / drain doping is performed. In this case, the impurity doping of the source / drain may selectively select the third insulating layers 34, 34 ′, 54, 54 ′, 514 and 514 ′ and the first insulating layers 32, 52, and 512 below after forming the second gate. And doping can be made easier by forming a spacer using a fourth insulating film on the gate sidewall.

[Example 5]

In the first, second, and third embodiments, in forming the fine pattern on the third insulating film in FIG. 3D or 5D, first, the bends 34 ′, 54 ′, and 514 ′ formed in the third insulating film are first changed into CMP (Chemical Mechanical). After the planarization as shown in FIG. 8 using a polishing process, a lithography process is performed.

The single-electron transistor according to the present invention solves the problem of weakening the tunneling barrier caused by the first gate by forming the first gate on the sidewall of the channel, and remaining on the sidewall of the channel according to the degree of excessive etching during the first gate material etching. By controlling the height of one gate, the size of the quantum dot of the single-electron transistor can be adjusted, thereby increasing the operating temperature of the single-electron transistor.

In addition, in order to implement a low-power, high-density single-electron transistor system, MOSFETs must be integrated at the same time. The gate MOSFET structure and its manufacturing method are presented.

1 is a perspective view of a conventional single electron transistor structure.

2A is a layout of a conventional double gate MOSFET.

FIG. 2B is a cross-sectional view taken along the line AA ′ of FIG. 2A.

FIG. 2C is a cross-sectional view taken along the line BB ′ of FIG. 2A.

3A to 3I are perspective views illustrating a manufacturing process of a single electron transistor according to a first embodiment of the present invention.

FIG. 4A is a cross-sectional view taken along the line AA ′ of FIG. 3I showing a state in which the single-electron transistor according to the first embodiment of the present invention is finally completed.

4B is a cross-sectional view taken along line B-B 'of FIG. 3I showing a state in which the single-electron transistor according to the first embodiment of the present invention is finally completed.

4C is a cross-sectional view taken along line C-C 'of FIG. 3I showing a state in which the single-electron transistor according to the first embodiment of the present invention is finally completed.

5A to 5I are perspective views illustrating a process for simultaneously manufacturing a single-electron transistor and a double gate MOSFET according to a second embodiment of the present invention.

FIG. 6A is a cross-sectional view taken along line AA ′ of FIG. 5I showing a state in which a single-electron transistor and a double gate MOSFET are finally completed according to the second embodiment of the present invention.

FIG. 6B is a cross-sectional view taken along line B-B 'of FIG. 5I showing a state in which the single-electron transistor and the double gate MOSFET are finally completed according to the second embodiment of the present invention.

FIG. 6C is a cross-sectional view taken along line C-C 'of FIG. 5I showing a state in which the single-electron transistor and the double gate MOSFET are finally completed according to the second embodiment of the present invention.

FIG. 6D is a cross-sectional view taken along line D-D ′ of FIG. 5I showing a state in which the single-electron transistor and the double gate MOSFET are finally completed according to the second embodiment of the present invention.

FIG. 7 is a perspective view of a case in which the first insulating film fine pattern according to the third exemplary embodiment of the present invention is a laminated material. FIG.

8 is a perspective view after planarizing the bends 54 'and 514' formed in the third insulating film according to the fifth embodiment of the present invention using a chemical mechanical polishing (CMP) process.

<Description of the symbols for the main parts of the drawings>

30, 50: investment oxide film

31, 51, 511: single crystal silicon

32, 52, 512: fine pattern of the first insulating film

33, 53, 513: second insulating film

34, 54, 514: third insulating film

34 ', 54', 514 ': bent portion of the third insulating film

35, 55, 515: portion where the gate will be formed

35 ', 55', 515 ': recessed portion where gate will be formed

36, 56, 516: first gate insulating film

57, 517: First gate

38, 58: second gate insulating film

59: second gate

32 ', 52': portion of the channel not covered by the first gate

37 ', 57': portion of the channel covered by the first gate

52 ", 512": An upper layer of the first insulating film having a laminated structure and having a good etching selectivity with respect to the third insulating film

524: third insulating film planarized by CMP process

Claims (27)

An insulator laminated on the substrate support; Source and drain regions formed on the insulator spaced apart from each other by single crystal silicon; A thin channel connecting the source and the drain to each other and formed of single crystal silicon; A first insulating film for forming the channel; A first gate insulating layer 36 electrically separating the source and drain regions while making most of both sidewalls of the channel a transmission barrier; A first gate 37 stacked on the first gate insulating layer and formed in a spacer shape only on sidewall portions of the source and drain portions and a portion of the channel sidewalls; A second gate insulating film 38 for forming a quantum dot from the remaining portions of both sidewalls of the channel where the first gate is not formed; And a second gate (39) stacked between the source and drain regions over the second gate insulating film and the first insulating film. The single-electron transistor of claim 1, wherein the second gate formed in the channel has a size that can be adjusted according to a thickness of the first gate material and a degree of excessive etching. The single-electron transistor according to claim 1 or 2, wherein the first gate insulating film is any one selected from a silicon oxide film, a silicon nitride film, and a high dielectric constant insulating film. The single-electron transistor according to claim 1 or 2, wherein the first gate material is any one selected from polycrystalline silicon, amorphous silicon and a metal. The single-electron transistor according to claim 1 or 2, wherein the insulator is a silicon oxide film. An insulator laminated on the substrate support; The single-electron transistor of claim 1 formed on the insulator spaced apart from each other; Source and drain regions formed of single crystal silicon spaced apart from each other on top of the insulator; A thin channel connecting the source and drain regions and formed of single crystal silicon on the insulator; A first insulating film integrally deposited on top of the channel and on a portion of the top of the source and drain in line with the channel; A first gate insulating film deposited on both sidewalls of the channel and sidewall portions of the source and the drain; And a double gate MOSFET including a first gate formed on the first gate insulating layer and the first insulating layer overlying the channel and stacked between the source and drain regions. delete 7. The method of claim 6, wherein the single-electron transistor is characterized in that the length of the channel is greater than twice the thickness of the first gate material, and wherein the double gate MOSFET is less than twice the thickness of the first gate material. Single electron transistor and double gate MOSFET. 7. The single-electron transistor and the double gate MOSFET of claim 6, wherein the first gate insulating film is any one selected from a silicon oxide film, a silicon nitride film, and a high dielectric constant insulating film. 7. The single-electron transistor and double gate MOSFET of claim 6, wherein the first gate is one selected from polycrystalline silicon, amorphous silicon, and a metal. 7. The single-electron transistor and double gate MOSFET of claim 6, wherein the insulator is a silicon oxide film. Defining a single crystal silicon to be used as an active layer in an SOI substrate and forming a fine pattern of a first insulating film in a portion to be a channel; Forming a spacer with a second insulating film on the fine patterns of the single crystal silicon and the first insulating film, and injecting impurities into the single crystal silicon to do source and drain doping; Depositing and patterning a third insulating film on single crystal silicon on which the first insulating film fine pattern and the second insulating film spacer are formed; A fourth step of forming a channel by removing single crystal silicon of a portion where the first gate is to be formed using the fine patterns of the third insulating film and the first insulating film as a mask; A fifth step of growing a first gate insulating film on sidewalls of the channel, the source, and the drain; Forming a first gate by depositing and etching a material to be used as a first gate on the first gate insulating layer; Forming a second gate insulating film on the first gate and on the remaining channel portion not covered with the first gate; And a eighth step of forming a second gate electrode on the second gate insulating film. The method of claim 12, wherein the first insulating layer has a stacked structure composed of two or more materials. The method of manufacturing a single electron transistor according to claim 13, wherein the stacked structure of the first insulating film has a lower layer as a silicon oxide film or a silicon nitride film and an upper layer as polycrystalline silicon or amorphous silicon. 13. The method of claim 12, wherein the source and drain doping removes the third insulating film and the first insulating film after forming the second gate, and is doped with impurities. 16. The method of claim 15, wherein the impurity doping is performed after removing the third insulating film and the first insulating film and forming a spacer using a fourth insulating film on the sidewall of the gate. 13. The method of claim 12, wherein the third insulating film patterning causes the channel length to be greater than twice the thickness of the first gate material. 18. The method of claim 12 or 17, wherein the patterning of the third insulating film is performed after depositing the third insulating film and performing a CMP process. 18. The method of claim 12 or 17, wherein the first gate material is etched to leave the first gate only on portions of the sidewalls and the channel sidewalls of the source and the drain.  Defining a single crystal silicon to be used as an active layer in the SOI substrate, and forming a fine pattern of the first insulating film in a portion to be a channel; Forming a spacer with a second insulating film on the fine patterns of the single crystal silicon and the first insulating film, and injecting impurities into each single crystal silicon to do source and drain doping; A third step of depositing a third insulating film on the single crystal silicon on which the first insulating film fine pattern and the second insulating film spacer are formed and patterning the third insulating film so that the channel length of each device is formed differently; A fourth step of forming a channel by removing each single crystal silicon in a portion where the first gate is to be formed using the fine patterns of the third insulating film and the first insulating film as a mask; A fifth step of growing a first gate insulating film on sidewalls of the channel, the source, and the drain; Forming a first gate by depositing and etching a material to be used as a first gate on the first gate insulating layer; Forming a second gate insulating film on the first gate and on the portion of the channel not covered with the first gate; And an eighth step of forming a second gate electrode on the second gate insulating film. 21. The method of claim 20, wherein the first insulating film is a stacked structure composed of two or more materials. 22. The method of claim 21, wherein the stacked structure of the first insulating film is a silicon oxide film or silicon nitride film with a lower layer and polycrystalline silicon or amorphous silicon with an upper layer. 21. The method of claim 20, wherein the source and drain doping removes the third insulating film and the first insulating film after forming the second gate and doped with impurities, respectively. How to. 24. The single-electron transistor and the double-gate MOSFET of claim 23, wherein the impurity doping is performed after removing the third insulating film and the first insulating film, respectively, and forming a spacer using a fourth insulating film on each sidewall of the gate. How to manufacture at the same time. 21. The method of claim 20, wherein the third insulating film patterning is such that the channel length is greater than twice the thickness of the first gate material at the location where the single-electron transistor is to be fabricated and the channel length is first at the location where the double gate MOSFET is to be fabricated. A method of simultaneously fabricating a single-electron transistor and a double gate MOSFET, characterized in that it is less than twice the thickness of the gate material. 26. The method of claim 20 or 25, wherein the third insulating film patterning is performed after the CMP process after depositing the third insulating film. 26. The gate of claim 20 or 25, wherein the first gate material is etched, leaving the first gate at only a portion of the sidewalls of the source and drain and a portion of the sidewalls of the channel at the position where the single-electron transistor is to be fabricated. A method for manufacturing a single-electron transistor and a double-gate MOSFET simultaneously, wherein a first gate is left between the source and the drain while surrounding the channel at a position where the MOSFET is to be manufactured.