KR100515382B1 - Inter-Metal Dielectric layer structure in semiconductor device and method for fabricating the same - Google Patents
Inter-Metal Dielectric layer structure in semiconductor device and method for fabricating the same Download PDFInfo
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- KR100515382B1 KR100515382B1 KR10-2003-0101862A KR20030101862A KR100515382B1 KR 100515382 B1 KR100515382 B1 KR 100515382B1 KR 20030101862 A KR20030101862 A KR 20030101862A KR 100515382 B1 KR100515382 B1 KR 100515382B1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
- H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
- H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
- H01L21/02126—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC
- H01L21/02129—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC the material being boron or phosphorus doped silicon oxides, e.g. BPSG, BSG or PSG
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
- H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
- H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
- H01L21/02126—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC
- H01L21/02131—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC the material being halogen doped silicon oxides, e.g. FSG
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
- H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
- H01L21/02263—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
- H01L21/02271—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition
- H01L21/02274—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition in the presence of a plasma [PECVD]
Abstract
본 발명의 반도체 소자의 금속간 절연막 구조는, 하부 금속 배선막과 상부 금속 배선막을 전기적으로 분리시키기 위한 것이다, 이 금속간 절연막 구조는, 하부 금속 배선막과 상부 금속 배선막 사이에서 라이너, PSG(Phosphorous Silica Glass) 하부 라이너, FSG(Fluorine-doped Silica Glass)막, PSG(Phosphorous Silica Glass) 상부 라이너 및 캡핑층이 순차적으로 적층되는 구조로 이루어진다.The intermetallic insulating film structure of the semiconductor element of the present invention is for electrically separating the lower metal wiring film and the upper metal wiring film. The intermetallic insulating film structure includes a liner and a PSG between the lower metal wiring film and the upper metal wiring film. Phosphorous Silica Glass lower liner, Fluorine-doped Silica Glass (FSG) film, Phosphorous Silica Glass (PSG) upper liner and capping layer are sequentially stacked.
Description
본 발명은 반도체 소자 및 그 제조 방법에 관한 것으로서, 보다 상세하게는 반도체 소자의 금속간 절연막 구조 및 그 제조 방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a method for manufacturing the same, and more particularly, to an intermetallic insulating film structure of a semiconductor device and a method for manufacturing the same.
최근 금속 배선막과 금속 배선막 사이를 절연시키는 금속간 절연(IMD; Inter-Metal Dielectric)막으로서 저유전율을 갖는(low-k) 물질을 사용하는 구조가 각광받고 있다. 저유전율을 갖는 물질로 금속간 절연막을 형성하는 경우 RC 지연이 감소되고, 크로스토크(cross talk) 잡음이 억제되는 등의 많은 장점들을 제공한다.Recently, a structure using a low-k material as an inter-metal dielectric (IMD) film that insulates between the metal wiring film and the metal wiring film has been in the spotlight. Forming an intermetallic insulating film with a material having a low dielectric constant provides many advantages, such as reducing RC delay and suppressing cross talk noise.
도 1은 종래의 반도체 소자의 금속간 절연막 구조이 일 예를 개략적으로 나타내 보인 단면도이다.1 is a cross-sectional view schematically showing an example of an intermetallic insulating film structure of a conventional semiconductor device.
도 1을 참조하면, 금속간 절연막(120)은, 하부 금속 배선막(110)과 상부 금속 배선막(130) 사이를 절연하기 위하여 그 사이에 배치된다. 이 금속간 절연막(120)은, 하부 금속 배선막(110) 위에 배치되는 라이너(121)와, 라이너(121) 위에 배치되는 FSG(Fluorine-doped Silica Glass)막(122)과, 그리고 FSG막(122)과 상부 금속 배선막(130) 사이의 캡핑층(123)을 포함하여 구성된다.Referring to FIG. 1, an intermetallic insulating film 120 is disposed therebetween to insulate between the lower metal wiring film 110 and the upper metal wiring film 130. The intermetallic insulating film 120 includes a liner 121 disposed on the lower metal wiring film 110, a Fluorine-doped Silica Glass (FSG) film 122 disposed on the liner 121, and an FSG film ( And a capping layer 123 between the 122 and the upper metal wiring layer 130.
도 2는 도 1의 금속간 절연막 구조의 제조 방법을 설명하기 위하여 나타내 보인 플로우챠트이다.FIG. 2 is a flowchart showing a method for manufacturing the intermetallic insulating film structure of FIG. 1.
도 2를 참조하면, 먼저 하부 금속 배선막(110) 위에 라이너(121)를 증착시킨다(단계 210). 라이너(121)는 PECVD(Plasma Enhanced Chemical Vapor Deposition)법을 사용하여 형성할 수 있다. 다음에 라이너(121) 위에 FSG막(122)을 이용하여 캡 필(gap fill)을 수행한다(단계 220). 다음에 FSG막(122) 위에 PECVD법을 이용한 캡핑층(123)을 형성한다(단계 230).Referring to FIG. 2, first, a liner 121 is deposited on the lower metal wiring layer 110 (step 210). The liner 121 may be formed using a Plasma Enhanced Chemical Vapor Deposition (PECVD) method. Next, a cap fill is performed on the liner 121 using the FSG film 122 (step 220). Next, a capping layer 123 is formed on the FSG film 122 using PECVD (step 230).
그런데 상기 FSG막(122)은 저유전율을 유지하기 위해 불소(F)를 포함하고 있는데, 이 불소는 인접하는 하부 금속 배선막(110) 및 상부 금속 배선막(130)으로 쉽게 확산된다는 문제가 있다. 특히 이 불소는 후속의 열공정시에 불순물로 존재하는 수소(H)와 결합하여 HF 형태로서 하부 금속 배선막(110) 및 상부 금속 배선막(130)에 리프팅(lifting)과 같은 결함이 발생되도록 하고, 비아 홀에도 결함을 발생시키는 등 소자의 신뢰성 및 수율에 큰 악 영향을 끼친다.However, the FSG film 122 includes fluorine (F) to maintain a low dielectric constant, which has a problem in that the fluorine is easily diffused into the adjacent lower metal wiring film 110 and the upper metal wiring film 130. . In particular, the fluorine is combined with hydrogen (H) which is present as an impurity in a subsequent thermal process so that defects such as lifting are generated in the lower metal wiring layer 110 and the upper metal wiring layer 130 in the form of HF. In addition, defects are also generated in the via holes, which greatly affect the reliability and yield of the device.
본 발명이 이루고자 하는 기술적 과제는 FSG막 내에 포함되는 불소 성분이 하부 금속 배선막 및 상부 금속 배선막으로 확산되지 않는 반도체 소자의 금속간 절연막 구조를 제공하는 것이다.An object of the present invention is to provide an intermetallic insulating film structure of a semiconductor device in which the fluorine component contained in the FSG film is not diffused into the lower metal wiring film and the upper metal wiring film.
본 발명이 이루고자 하는 다른 기술적 과제는 상기 반도체 소자의 금속간 절연막 구조를 제조하는 방법을 제공하는 것이다.Another object of the present invention is to provide a method of manufacturing an intermetallic insulating film structure of the semiconductor device.
상기 기술적 과제를 달성하기 위하여, 본 발명에 따른 반도체 소자의 금속간 절연막 구조는, 하부 금속 배선막과 상부 금속 배선막을 전기적으로 분리시키기 위한 반도체 소자의 금속간 절연막 구조에 있어서, 상기 하부 금속 배선막과 상기 상부 금속 배선막 사이에서 라이너, PSG(Phosphorous Silica Glass) 하부 라이너, FSG(Fluorine-doped Silica Glass)막, PSG(Phosphorous Silica Glass) 상부 라이너 및 캡핑층이 순차적으로 적층되는 구조로 이루어지는 것을 특징으로 한다.In order to achieve the above technical problem, the intermetallic insulating film structure of the semiconductor device according to the present invention, in the intermetallic insulating film structure of the semiconductor device for electrically separating the lower metal wiring film and the upper metal wiring film, the lower metal wiring film And a liner, a phosphorous silica glass (PSG) lower liner, a fluorine-doped silica glass (FSG) film, a phosphorous silica glass (PSG) upper liner, and a capping layer are sequentially stacked between the upper metal wiring layer and the upper metal wiring layer. It is done.
상기 PSG 하부 라이너 및 PSG 상부 라이너는 20-5000Å의 두께를 갖는 것이 바람직하다.The PSG lower liner and PSG upper liner preferably have a thickness of 20-5000 mm 3.
상기 다른 기술적 과제를 달성하기 위하여, 본 발명에 따른 반도체 소자의 금속간 절연막 구조의 제조 방법은, 하부 금속 배선막과 상부 금속 배선막을 전기적으로 분리시키기 위한 반도체 소자의 금속간 절연막 구조의 제조 방법에 있어서, 상기 하부 금속 배선막 위에 라이너를 형성하는 단계; 상기 라이너 위에 PSG(Phosphorous Silica Glass) 하부 라이너를 형성하는 단계; 상기 PSG 하부 라이너 위에 FSG(Fluorine-doped Silica Glass)막을 형성하는 단계; 상기 FSG막 위에 PSG(Phosphorous Silica Glass) 상부 라이너를 형성하는 단계; 및 상기 PSG 상부 라이너 위에 캡핑층을 형성하는 단계를 포함하는 것을 특징으로 한다.In order to achieve the above another technical problem, a method of manufacturing an intermetallic insulating film structure of a semiconductor device according to the present invention is directed to a method of manufacturing an intermetallic insulating film structure of a semiconductor device for electrically separating the lower metal wiring film and the upper metal wiring film. Forming a liner on the lower metal wiring layer; Forming a PSG (Phosphorous Silica Glass) bottom liner over the liner; Forming a Fluorine-doped Silica Glass (FSG) film on the PSG lower liner; Forming a phosphorous silica glass (PSG) upper liner on the FSG film; And forming a capping layer on the PSG upper liner.
상기 PSG 하부 라이너 및 PSG 상부 라이너는 20-5000Å의 두께를 갖도록 하는 것이 바람직하다.Preferably, the PSG bottom liner and PSG top liner have a thickness of 20-5000 mm 3.
상기 라이너 및 캡핑층은 PECVD(Plasma Enhanced Chemical Vapor Deposition)법을 사용하여 형성하는 것이 바람직하다.The liner and the capping layer are preferably formed using a Plasma Enhanced Chemical Vapor Deposition (PECVD) method.
이하 첨부 도면을 참조하여 본 발명의 바람직한 실시예를 상세히 설명하기로 한다. 그러나, 본 발명의 실시예들은 여러 가지 다른 형태로 변형될 수 있으며, 본 발명의 범위가 아래에서 상술하는 실시예들로 인해 한정되어지는 것으로 해석되어져서는 안된다.Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. However, embodiments of the present invention may be modified in many different forms, and the scope of the present invention should not be construed as being limited by the embodiments described below.
도 3은 본 발명에 따른 반도체 소자의 금속간 절연막 구조를 개략적으로 나타내 보인 단면도이다.3 is a cross-sectional view schematically showing the intermetallic insulating film structure of the semiconductor device according to the present invention.
도 3을 참조하면, 본 발명에 따른 반도체 소자의 금속간 절연막(320)은, 하부 금속 배선막(310)과 상부 금속 배선막(330) 사이를 절연하기 위하여 그 사이에 배치된다. 이 금속간 절연막(320)은, 하부 금속 배선막(310) 위에 배치되는 라이너(321)와, 라이너(321) 위에 배치되는 PSG(Phosphorous Silica Glass) 하부 라이너(322)와, PSG 하부 라이너(322) 위에 배치되는 FSG(Fluorine-doped Silica Glass)막(323)과, FSG막(323) 위에 배치되는 PSG 상부 라이너(324)와, 그리고 PSG 상부 라이너(324) 위에 배치되는 캡핑층(325)을 포함하여 구성된다.Referring to FIG. 3, an intermetallic insulating film 320 of a semiconductor device according to the present invention is disposed therebetween to insulate between the lower metal wiring film 310 and the upper metal wiring film 330. The intermetallic insulating film 320 includes a liner 321 disposed on the lower metal wiring film 310, a phosphorous silica glass (PSG) lower liner 322 disposed on the liner 321, and a PSG lower liner 322. Fluorine-doped Silica Glass (FSG) film 323 disposed on the top surface), the PSG upper liner 324 disposed on the FSG film 323, and the capping layer 325 disposed on the PSG upper liner 324. It is configured to include.
이와 같은 금속간 절연막(320)에 있어서, 상기 FSG막(323)은 PSG 하부 라이너(322)와 PSG 상부 라이너(324) 사이에서 샌드위치(sandwich) 구조로 배치되며, 이에 따라 FSG막(323) 내의 불소는 PSG 하부 라이너(322)와 PSG 하부 라이너(324)의 그물망 구조에 걸려서 하부 금속 배선막(310)이나 또는 상부 금속 배선막(330)으로 확산되지 못한다. 상기 PSG 하부 라이너(322) 및 PSG 하부 라이너(324)는 각각 20-5000Å의 두께를 갖는다.In the intermetallic insulating layer 320, the FSG film 323 is disposed in a sandwich structure between the PSG lower liner 322 and the PSG upper liner 324, and thus, in the FSG film 323. Fluorine is caught in the network structure of the PSG lower liner 322 and the PSG lower liner 324 and thus cannot be diffused into the lower metal interconnect layer 310 or the upper metal interconnect layer 330. The PSG lower liner 322 and PSG lower liner 324 each have a thickness of 20-5000 mm 3.
도 4는 도 3의 금속간 절연막 구조의 제조 방법을 설명하기 위하여 나타내 보인 플로우챠트이다.FIG. 4 is a flowchart illustrating a method of manufacturing the intermetallic insulating film structure of FIG. 3.
도 4를 참조하면, 먼저 하부 금속 배선막(310) 위에 라이너(321)를 증착시킨다(단계 410). 라이너(321)는 PECVD법을 사용하여 형성할 수 있다. 다음에 라이너(321) 위에 PSG 하부 라이너(321)를 형성한다(단계 420). PSG 하부 라이너(321)의 두께는 대략 20-5000Å이 되도록 한다. 다음에 PSG 하부 라이너(321) 위에 FSG막(322)을 형성한다(단계 430). 다음에 FSG막(323) 위에 PSG 상부 라이너(324)를 형성한다(단계 440). PSG 상부 라이너(324)의 두께도 대략 20-5000Å이 되도록 한다. 다음에 PSG 상부 라이너(324) 위에 PECVD법을 이용한 캡핑층(325)을 형성한다(단계 450).Referring to FIG. 4, first, a liner 321 is deposited on the lower metal wiring layer 310 (step 410). The liner 321 may be formed using PECVD. Next, a PSG lower liner 321 is formed over the liner 321 (step 420). The thickness of the PSG lower liner 321 is approximately 20-5000 mm 3. Next, an FSG film 322 is formed on the PSG lower liner 321 (step 430). Next, a PSG upper liner 324 is formed over the FSG film 323 (step 440). The thickness of the PSG upper liner 324 is also approximately 20-5000 mm 3. Next, a capping layer 325 using PECVD is formed on the PSG upper liner 324 (step 450).
이상의 설명에서와 같이, 본 발명에 따른 반도체 소자의 금속간 절연막 구조 및 그 제조 방법에 의하면, FSG막의 상부 및 하부에 각각 PSG 라이너를 형성함으로써 FSG막의 불소가 PSG 라이너의 그물망 구조에 가둘 수 있으며, 이에 따라 FSG막으로부터의 불소가 하부 금속 배선막 또는 상부 금속 배선막으로 확산되는 현상을 억제시킬 수 있다.As described above, according to the intermetallic insulating film structure and the manufacturing method of the semiconductor device according to the present invention, by forming a PSG liner on the upper and lower portions of the FSG film, the fluorine of the FSG film can be trapped in the mesh structure of the PSG liner, Thereby, the phenomenon which the fluorine from an FSG film spreads to a lower metal wiring film or an upper metal wiring film can be suppressed.
이상 본 발명을 바람직한 실시예를 들어 상세하게 설명하였으나, 본 발명은 상기 실시예에 한정되지 않으며, 본 발명의 기술적 사상 내에서 당 분야에서 통상의 지식을 가진 자에 의하여 여러 가지 변형이 가능함은 당연하다.Although the present invention has been described in detail with reference to preferred embodiments, the present invention is not limited to the above embodiments, and various modifications may be made by those skilled in the art within the technical spirit of the present invention. Do.
도 1은 종래의 반도체 소자의 금속간 절연막 구조의 일 예를 개략적으로 나타내 보인 단면도이다.1 is a cross-sectional view schematically showing an example of an intermetallic insulating film structure of a conventional semiconductor device.
도 2는 도 1의 금속간 절연막 구조의 제조 방법을 설명하기 위하여 나타내 보인 플로우챠트이다.FIG. 2 is a flowchart showing a method for manufacturing the intermetallic insulating film structure of FIG. 1.
도 3은 본 발명에 따른 반도체 소자의 금속간 절연막 구조를 개략적으로 나타내 보인 단면도이다.3 is a cross-sectional view schematically showing the intermetallic insulating film structure of the semiconductor device according to the present invention.
도 4는 도 3의 금속간 절연막 구조의 제조 방법을 설명하기 위하여 나타내 보인 플로우챠트이다.FIG. 4 is a flowchart illustrating a method of manufacturing the intermetallic insulating film structure of FIG. 3.
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