KR100505394B1 - Wafer-level chip size semiconductor package and its manufacturing method - Google Patents
Wafer-level chip size semiconductor package and its manufacturing method Download PDFInfo
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- KR100505394B1 KR100505394B1 KR10-1998-0043481A KR19980043481A KR100505394B1 KR 100505394 B1 KR100505394 B1 KR 100505394B1 KR 19980043481 A KR19980043481 A KR 19980043481A KR 100505394 B1 KR100505394 B1 KR 100505394B1
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 77
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 29
- 230000001681 protective effect Effects 0.000 claims abstract description 7
- 238000000034 method Methods 0.000 claims description 35
- 229920002120 photoresistant polymer Polymers 0.000 claims description 24
- 239000002184 metal Substances 0.000 claims description 13
- 238000004544 sputter deposition Methods 0.000 claims description 6
- 239000000463 material Substances 0.000 claims description 5
- 238000005530 etching Methods 0.000 claims description 3
- 238000000576 coating method Methods 0.000 claims description 2
- 229920001971 elastomer Polymers 0.000 claims description 2
- 239000000806 elastomer Substances 0.000 claims description 2
- 229910000679 solder Inorganic materials 0.000 claims description 2
- 239000011343 solid material Substances 0.000 claims description 2
- 239000013536 elastomeric material Substances 0.000 claims 2
- 239000011248 coating agent Substances 0.000 claims 1
- 239000007769 metal material Substances 0.000 claims 1
- 238000000465 moulding Methods 0.000 description 9
- 239000010408 film Substances 0.000 description 4
- 238000005520 cutting process Methods 0.000 description 2
- 238000009826 distribution Methods 0.000 description 2
- 230000010354 integration Effects 0.000 description 2
- 230000008707 rearrangement Effects 0.000 description 2
- 238000005476 soldering Methods 0.000 description 2
- 239000010409 thin film Substances 0.000 description 2
- 239000003822 epoxy resin Substances 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- WABPQHHGFIMREM-UHFFFAOYSA-N lead(0) Chemical compound [Pb] WABPQHHGFIMREM-UHFFFAOYSA-N 0.000 description 1
- 238000012858 packaging process Methods 0.000 description 1
- 238000007747 plating Methods 0.000 description 1
- 229920000647 polyepoxide Polymers 0.000 description 1
- 239000007787 solid Substances 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
- H01L21/4814—Conductive parts
- H01L21/4821—Flat leads, e.g. lead frames with or without insulating supports
- H01L21/4828—Etching
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3157—Partial encapsulation or coating
- H01L23/3171—Partial encapsulation or coating the coating being directly applied to the semiconductor body, e.g. passivation layer
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
- H01L23/49579—Lead-frames or other flat leads characterised by the materials of the lead frames or layers thereon
- H01L23/49582—Metallic layers on lead frames
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/4826—Connecting between the body and an opposite side of the item with respect to the body
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73215—Layer and wire connectors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Wire Bonding (AREA)
- Lead Frames For Integrated Circuits (AREA)
Abstract
본 발명은 웨이퍼 수준 칩크기 반도체 패키지에 관한 것으로서, 특히 패키지를 웨이퍼 상에서 직접 형성하여 표면실장에 용이하고 접속상태의 신뢰도를 높이기 위함이다. 본 발명에 의한 웨이퍼 수준 칩크기 반도체 패키지는 반도체 칩(11) 표면상에 통상적인 수개의 본딩패드(12)로 이루어지는 본딩패드 어레이를 재배치한 전극(13)들로 이루어지는 전극패턴, 이 전극패턴의 각 전극(13)의 먼 쪽 끝 부분에 전기접속된 내부접속부(14a)와 외부회로측의 외부접속부(14b)을 가지는 수개의 리드(14), 그리고 표면에 도포되는 보호막(17)을 가지는 리드돌출된 실 칩크기의 반도체 패키지로 제공된다. 이러한 패키지 구조는 웨이퍼상에서 직접 제조되므로 그 제조시 외부회로의 접속환경에 따라 리드의 높이와 접속면적을 적절하게 조절할 수 있어 생산성이 높고 높은 신뢰도를 보유할 수 있다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a wafer-level chip size semiconductor package, and in particular, to form the package directly on the wafer to facilitate surface mounting and to increase the reliability of the connection state. The wafer-level chip size semiconductor package according to the present invention comprises an electrode pattern consisting of electrodes 13 having rearranged a bonding pad array consisting of several conventional bonding pads 12 on the surface of the semiconductor chip 11, A lead having several leads 14 having an internal connection portion 14a electrically connected to the far end of each electrode 13 and an external connection portion 14b on the external circuit side, and a protective film 17 applied to the surface thereof. It is provided in a semiconductor package of protruding seal chip size. Since the package structure is manufactured directly on the wafer, the height and the connection area of the lead can be appropriately adjusted according to the connection environment of the external circuit during the manufacturing process, thereby achieving high productivity and high reliability.
Description
본 발명은 웨이퍼(wafer) 상에서 형성된 돌출 리드를 가지는 웨이퍼 수준 칩크기 반도체 패키지에 관한 것으로서, 특히 패키지 제조시에 외부회로에의 장착환경에 따라 리드 패턴(pattern)의 재배치와 높이 및 접속면적의 조절이 가능한 구조의 웨이퍼 수준 칩크기 반도체 패키지와 그 제조방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a wafer-level chip size semiconductor package having protruding leads formed on a wafer, and in particular, rearrangement and adjustment of height and connection area of a lead pattern according to the mounting environment to an external circuit during package manufacture. A wafer level chip size semiconductor package having a possible structure and a method of manufacturing the same.
잘 알려진 바와 같이 반도체 소자는, 웨이퍼의 박막성장 기법에 의해 제조된 칩(chip)을 그 웨이퍼로부터 절단(sawing) 분리한 다음, 분리된 칩을 실드(shield)나 몰딩(molding)으로 외부의 습기나 불순물로부터 보호되고 또한 외부회로와의 접속을 위한 리드를 부착한 패키지(package) 형태로 상품화 된다. 반도체 패키지는 통상 리드 방식과 실드 또는 몰딩 구조에 따라 분류되고 있는데, 본 발명과 관련된 칩크기(chip size) 반도체 패키지는 대부분의 공간을 칩이 차지하는 정도의 크기로 되는 몰딩구조이고 몰딩 외부로 돌출된 리드를 가진 표면실장형이다. 이러한 칩크기 반도체 패키지는 그 자체가 단일한 미소 소자(micro device)로 상품화되어 회로기판에 있어서의 실장밀도를 높이고 또는 응용 주문형 집적회로(ASIC; application specific IC)등 각종 집적회로에서의 집적도를 높이는데 아주 유용하다.As is well known, a semiconductor device may saw-separate a chip manufactured by a thin film growth technique of a wafer from the wafer, and then separate or separate the chip into a shield or molding. It is commercialized in the form of a package which is protected from impurities and has a lead for connection with an external circuit. The semiconductor package is generally classified according to the lead method and the shield or molding structure. The chip size semiconductor package according to the present invention is a molding structure that is large enough to occupy most of the space and protrudes out of the molding. It is a surface mount type with leads. Such a chip size semiconductor package is commercialized as a single micro device itself to increase the mounting density on a circuit board or to increase the degree of integration in various integrated circuits such as an application specific IC (ASIC). Very useful.
칩크기 반도체 패키지의 구조 및 제조와 관련한 종래의 기술을 설명하면, 종래에는 도 1에 보인 바와 같이 베어칩(bare chip; 1)에 리드(2)를 직접 본딩(bonding)하고, 그 베어칩(1)의 패드와 리드의 접속을 위해 세금선(細金線)인 와이어(wire; 3)를 본딩한 후, 칩 주위를 에폭시 수지로 몰딩한 몸체(4)를 형성하였으며, 이때 리드(2)의 단부(외부리드)가 밑면에 노출되는 표면실장의 형태로 구성한 것이다.Referring to the related art related to the structure and fabrication of a chip size semiconductor package, the lead 2 is directly bonded to a bare chip 1 as shown in FIG. After bonding the wire 3, which is a tax wire, to connect the pad and the lead of 1), a body 4 formed by molding an epoxy resin around the chip was formed. It is configured in the form of surface mount in which the end portion (outer lead) of is exposed on the bottom surface.
종래기술에 의한 칩크기 반도체 패키지는 몸체 밑면에 노출된 리드의 높이가 낮고 그 표면적이 넓지 못하여 표면실장시 외부회로와의 접속상태 신뢰도가 낮은 문제점을 가진다. 한편, 종래기술에 의한 칩크기 반도체 패키지는 칩을 웨이퍼에서 분리한 후 웨에퍼 제조시와는 별도의 패키지 공정에 의해 제조되는 것이므로, 전체 크기를 줄이는데 한계가 있고, 와이어 본딩 및 몰딩 장비를 특히 여러 가지 칩크기에 따라 별도로 구비하여야 하는 관계로 그만큼 설비비용 부담이 크다는 문제점을 안고 있다.The chip size semiconductor package according to the prior art has a problem in that the height of the lead exposed to the bottom of the body is low and its surface area is not wide so that the reliability of the connection state with the external circuit is low when the surface is mounted. On the other hand, since the chip size semiconductor package according to the prior art is manufactured by a separate packaging process from the wafer manufacturing after the chip is separated from the wafer, there is a limit to reduce the overall size, and in particular wire bonding and molding equipment Since there are various chip sizes to be provided separately, there is a problem that the burden of equipment cost is large.
본 발명의 목적은 상기한 문제점들을 극복하기 위하여 웨이퍼로부터 칩을 분리하기 전에 그 웨이퍼 상에서 직접 리드 패턴을 형성하여 되는 웨이퍼수준 칩크기 반도체 패키지와 그 제조방법을 제공하는데 있다.SUMMARY OF THE INVENTION An object of the present invention is to provide a wafer-level chip size semiconductor package and a method of manufacturing the same, in which a lead pattern is formed directly on the wafer before the chip is separated from the wafer in order to overcome the above problems.
본 발명의 목적은 또한 표면실장에 용이하고 접속상태의 신뢰도가 높은 웨이퍼수준 칩크기 반도체 패키지와 그 제조방법을 제공하는 것이다.It is also an object of the present invention to provide a wafer level chip size semiconductor package which is easy to surface mount and has high reliability in connection state and a method of manufacturing the same.
상기한 목적을 달성하는 본 발명에 따른 웨이퍼 수준 칩크기 반도체 패키지는, 표면에 본딩패드 어레이(bonding pad array)를 가지는 웨이퍼 상태의 반도체 칩과, 이 반도체 칩의 표면에 외부회로의 접속패턴에 대응하여 형성되어 각 본딩패드와 전기접속된 전극들로 재배치된 전극패턴과, 재배치된 전극패턴의 각 전극 위에 접속되는 내부접속부와 외부회로와의 접속을 위한 외부접속부를 가지는 리드를 구비하여 되는 점에 그 특징이 있다.A wafer-level chip size semiconductor package according to the present invention, which achieves the above object, corresponds to a semiconductor chip in a wafer state having a bonding pad array on its surface, and a connection pattern of an external circuit on the surface of the semiconductor chip. And a lead having an electrode pattern rearranged to electrodes electrically connected to each bonding pad, and having an internal connection portion connected to each electrode of the rearranged electrode pattern and an external connection portion for connection with an external circuit. It has its features.
또한, 상기한 목적을 달성하는 본 발명에 따른 웨이퍼 수준 칩크기 반도체 패키지의 제조방법은, 웨이퍼 상태의 반도체 칩 표면에 그 표면상에 있는 본딩패드 어레이를 재배치하기 위한 전극패턴을 형성하는 단계와 그 재배치된 본딩패드 어레이의 전극패턴의 각 전극 위에 전기접속되는 내부접속부와 외부회로와의 접속을 위한 외부접속부를 갖는 리드를 형성하는 단계를 포함하여 웨이퍼 상태의 패키지 원판를 제작하고, 그 제작된 웨이퍼 상태의 패키지 원판으로부터 각 반도체 칩에 대응하는 단위 반도체 칩 패키지를 분리하는 과정을 수행하는 것이다.In addition, a method for manufacturing a wafer-level chip size semiconductor package according to the present invention, which achieves the above object, comprises the steps of forming an electrode pattern for repositioning a bonding pad array on the surface of a semiconductor chip in a wafer state; Forming a package original in a wafer state, including forming a lead having an internal connection portion electrically connected to each other in the electrode pattern of the rearranged bonding pad array and an external connection portion for connection with an external circuit, and the wafer state A process of separating the unit semiconductor chip package corresponding to each semiconductor chip from the package original plate is performed.
바람직하게는 본 발명의 실시에 있어서, 상기한 리드를 상기한 전극패턴의 각 전극에 직접 접촉하는 리드베이스층과 이 리드베이스층 위에 도금되는 납땜가능 리드층의 두층으로 형성함으로써 리드의 강성 및 납땜성을 확보하고, 또한 그 리드의 외부회로와 접속되는 부분을 상기 도전층 위에 전기접속된 부분보다 칩의 표면으로부터 더 높이 위치하게 형성하여, 제조시 외부회로의 접속환경에 따라 그 리드의 높이를 조절할 수 있게 하는 것이다.Preferably, in the practice of the present invention, the stiffness and soldering of the lead is formed by forming the lead as two layers of a lead base layer in direct contact with each electrode of the electrode pattern and a solderable lead layer plated on the lead base layer. And the part connected to the external circuit of the lead is positioned higher from the surface of the chip than the part electrically connected on the conductive layer, thereby increasing the height of the lead according to the connection environment of the external circuit during manufacturing. To control it.
이러한 본 발명에 따르면, 반도체 패키지를 웨이퍼 상태의 반도체 칩 위에 직접 형성하므로 기존의 와이어 본딩과 몰딩 공정을 배제할 수 있고, 특히 제조시에 외부회로의 접속환경에 맞춰서 리드의 높이와 면적을 적절하게 조절할 수 있어서, 칩크기 변화에 용이하게 대처할 수 있는 동시에 외부회로와의 접속상태에 신뢰성을 확보할 수 있게 된다.According to the present invention, since the semiconductor package is directly formed on the semiconductor chip in the wafer state, the existing wire bonding and molding process can be eliminated, and the height and area of the lead can be appropriately adjusted in accordance with the connection environment of the external circuit during manufacturing. By adjusting, it is possible to easily cope with the change in the chip size and to ensure the reliability of the connection state with the external circuit.
이와같은 본 발명에 따른 웨이퍼 수준 칩크기 반도체 패키지의 바람직한 실시예와 그 제조방법에 관하여 첨부된 도면을 참조하면서 보다 자세하게 설명하면 다음과 같다.Such a preferred embodiment of the wafer-level chip size semiconductor package according to the present invention and a method of manufacturing the same will be described in more detail with reference to the accompanying drawings.
첨부된 도면중 도 2는 본 발명에 따른 웨이퍼 수준 칩크기 반도체 패키지의 외관을 보인다. 도면에 나타난 바와 같이 본 발명에 따른 웨이퍼 수준 칩크기 반도체 패키지는 반도체 칩(11) 표면상에 통상적인 수개의 본딩패드(12)로 이루어지는 본딩패드 어레이를 외부회로의 접속패턴에 대응하여 재배치하도록 각 본딩패드(12)와 전기접속되게 형성된 수개의 전극(13)들로 이루어지는 형성된 전극패턴과, 이 전극패턴의 각 전극(13)의 먼 쪽 끝 부분에 전기접속된 내부접속부(14a)와 외부회로측의 외부접속부(14b)을 가지는 수개의 리드(14), 그리고 반도체 칩(11) 표면과 본딩패드 어레이 및 전극패턴의 전면(全面) 위에 도포된 보호막(17)을 가지고 있다. 여기서 리드(14)는 각 전극(13) 끝 부분에 직접 접촉하는 견고한 금속재질의 리드베이스층(15)과 이 리드베이스층(15) 위에 납땜이 용이한 금속을 도금하여 된 납땜가능 리드층(16)로 이루어지고, 또한 리드(14)의 외부접속부(14b)가 내부접속부(14a)보다 반도체 칩(11)의 표면으로부터 더 높게 위치하고 있다.Figure 2 of the accompanying drawings shows the appearance of a wafer-level chip size semiconductor package according to the present invention. As shown in the drawings, the wafer-level chip size semiconductor package according to the present invention may be arranged so as to rearrange a bonding pad array composed of several conventional bonding pads 12 on the surface of the semiconductor chip 11 in correspondence with a connection pattern of an external circuit. An electrode pattern formed of several electrodes 13 electrically connected to the bonding pads 12, an internal connection portion 14a and an external circuit electrically connected to the far end of each electrode 13 of the electrode pattern; Several leads 14 having an external connection portion 14b on the side, and a protective film 17 coated on the entire surface of the semiconductor chip 11, the bonding pad array, and the electrode pattern. Here, the lead 14 includes a lead metal layer 15 made of a solid metal which is in direct contact with the end of each electrode 13 and a solderable lead layer formed by plating an easy soldering metal on the lead base layer 15. 16, and the external connection portion 14b of the lead 14 is located higher from the surface of the semiconductor chip 11 than the internal connection portion 14a.
발명에 따른 웨이퍼 수준 칩크기 반도체 패키지는, 반도체 칩을 제조하는 통상적인 웨이퍼 제조 과정을 마친 이후에, 웨이퍼를 절단(sawing)하여 개개의 칩을 분리하기 전에, 그 웨이퍼 상태에 있는 반도체 칩 위에 패키지 요소를 직접 형성하여 되는 이른바 웨이퍼 상태의 패키지 원판을 제조한 다음, 그 제조된 웨이퍼 상태의 패키지 원판을 절단 분리하여 얻어지는 것이다. 각 단위 패키지 상의 본딩패드 어레이의 재배치된 전술한 전극패턴과 리드(14)의 높이와 그 접속면적 등은 패키지 원판 제조시에 외부회로의 접속환경을 감안하여 가장 적합하게 조정된 것이다.The wafer-level chip size semiconductor package according to the invention is packaged on a semiconductor chip in the wafer state after the normal wafer fabrication process for manufacturing the semiconductor chip is completed, before sawing the wafer to separate the individual chips. It is obtained by manufacturing a so-called wafer-shaped package original, which is formed by directly forming an element, and then cutting and separating the manufactured wafer-shaped package original. The repositioned electrode pattern of the bonding pad array on each unit package, the height of the lead 14, the connection area thereof, and the like are most suitably adjusted in consideration of the connection environment of the external circuit at the time of manufacturing the original package.
이하, 제3a도 내지 제3j도를 참조하여 도 2에 도시된 바와 같은 본 발명에 따른 바람직한 실시예에 의한 웨이퍼 수준 칩크기 반도체 패키지를 위한 웨이퍼 상태의 패키지 원판의 제조과정을 기술한다.Hereinafter, a manufacturing process of a wafer in a wafer state for a wafer level chip size semiconductor package according to a preferred embodiment according to the present invention as shown in Figure 2 with reference to Figures 3a to 3j.
도 3a는 웨이퍼를 절단하기 전 그 웨이퍼의 한 부분에 존재하는, 웨이퍼 상태의 단위 반도체 칩(11)을 묘사한다. 이 웨이퍼 상태의 반도체 칩(11) 표면에 통상과 같은 수개의 본딩패드(12)로 이루어지는 본딩패드 어레이가 있다. 본 발명의 제조방법은 그 첫 번째 단계로서, 웨이퍼 상태의 반도체 칩(11) 표면에 금속 스퍼터링(sputtering) 공정을 통해 도시하지 않은 외부회로의 접속패턴에 대응하여 도 3b와 같이 각 본딩패드(12)와 전기접속하여 일측으로 뻗은 전극(13)들로 이루어져 결과적으로 그 본딩패드 어레이를 재배치한 형태가 되는 그 전극패턴을 형성하고, 다음 단계에서는 도 3c 내지 도 3i와 같은 순서로 리드(14;15,16)를 형성하며, 그리고 도 3j와 같이 보호막(17)을 형성하여 웨이퍼 상태의 패키지 원판을 완성하는 것이다.3A depicts the unit semiconductor chip 11 in wafer state, present in a portion of the wafer prior to cutting the wafer. On the surface of the semiconductor chip 11 in the wafer state, there is a bonding pad array composed of several bonding pads 12 as usual. As a first step, the manufacturing method of the present invention corresponds to a connection pattern of an external circuit (not shown) through a metal sputtering process on a surface of a semiconductor chip 11 in a wafer state, as shown in FIG. 3B. ) And an electrode pattern which is formed of electrodes 13 extending to one side to eventually form a rearrangement of the bonding pad array. In the next step, the lead 14 is formed in the order shown in FIGS. 3C to 3I. 15 and 16 are formed, and the protective film 17 is formed as shown in FIG. 3J to complete the package original in the wafer state.
리드(14;15,16)를 형성함에 있어서는, 먼저 도 3c와 같이 포토레지스트(photoresist; 18)를 도포하고 부분식각하는 1차포토레지스트 공정을 통해 각 전극(13)의 끝 부분만이 노출되게 하며, 전극(13)의 노출된 부분을 포함하여 부분식각된 포토레지스트(18) 표면 전체에 견고한 재질의 금속을 스퍼터링하여 도 3d와 같이 예비 리드베이스층(19)을 형성하며, 예비 리드베이스층(19) 위에는 납땜하기에 용이한 재질의 금속을 전기도금하여 도 3e와 같이 예비 납땜가능 리드층(20)을 형성하며, 예비 납땜가능 리드층(20) 위에는 재차 포토레지스트(21)를 도포하고 부분식각하는 2차포토레지스트 공정을 통해 도 3f와 같이 그 예비 납땜가능 리드층(20)의 필요한 부분을 제외한 나머지 부분이 노출되게 하며, 이렇게 노출된 부분의 예비 납땜가능 리드층(20) 일부 그리고 그 밑의 예비 리드베이스층(19) 일부가 차례로 제거되도록 식각한 다음, 나머지 포토레지스트(18,21)를 모두 제거함으로써 도 3i와 같이 제거되지 않고 남은 부분으로 전술한 리드(14;15,16)를 형성하는 것이다. 여기서 리드(14;15,16)의 높이는 1차포토레지스트 공정시에 도포되는 포토레지스트(18)의 높이(두께)에 의하여 조절될 수 있다.In forming the leads 14; 15 and 16, first, only the ends of each electrode 13 are exposed through a first photoresist process of applying and partially etching a photoresist 18 as shown in FIG. 3C. And sputtering a metal of solid material over the entire surface of the partially etched photoresist 18 including the exposed portion of the electrode 13 to form a preliminary lead base layer 19 as shown in FIG. 3D. On the 19, a metal of a material that is easy to solder is electroplated to form a preliminary solderable lead layer 20 as shown in FIG. 3E, and the photoresist 21 is applied on the presolderable lead layer 20 again. The partially etched secondary photoresist process exposes the remaining portions of the pre-solderable lead layer 20 except for the necessary portion, as shown in FIG. 3F, and a portion of the pre-solderable lead layer 20 of the exposed portions. The example below A portion of the non-lead base layer 19 is etched in order, and then all the remaining photoresist 18 and 21 are removed to form the above-described leads 14 and 15 and 16 as the remaining portions, as shown in FIG. 3I. It is. Here, the heights of the leads 14; 15 and 16 may be adjusted by the height (thickness) of the photoresist 18 applied during the primary photoresist process.
다음으로는, 반도체 칩(11) 표면에는 리드(14;15,16)를 제외한 나머지 전체, 즉 전술한 본딩패드 어레이 및 전극패턴을 포함하여 그 전면을 절연체로 코팅하여 도 3j와 같이 보호막(17)을 형성함으로써 전술한 웨이퍼 상태의 패키지 원판을 완성하는 것이다.Next, the entire surface of the semiconductor chip 11 except for the leads 14; 15 and 16, that is, the entire surface of the semiconductor chip 11 including the above-described bonding pad array and the electrode pattern is coated with an insulator, thereby protecting the protective film 17 as shown in FIG. 3J. ) To complete the package original in the above-described wafer state.
전술한 도 2에 도시된 바와 같은 웨이퍼 수준 칩크기 반도체 패키지는 상기와 같은 과정으로 완성되어진 웨이퍼 상태의 패키지 원판을 통상적인 절단(sawing) 작업을 통해 각 반도체 칩(11)을 단위로 분리하여 얻어지는 것이다.The above-described wafer level chip size semiconductor package as shown in FIG. 2 is obtained by separating each semiconductor chip 11 by a unit through a conventional sawing operation of a package state of a wafer completed in the above process. will be.
한편, 제4도는 본 발명에 따른 웨이퍼 수준 칩크기 패키지의 응용된 다른 구조를 보인다. 이 응용된 패키지는 도면에서 보는 바와 같이 반도체 칩(11)의 표면과 리드(14) 사이에 채워져서 그 리드(14)의 이면부를 지지하는 버퍼층(22)을 더 가진다. 이 버퍼층(22)은, 전술한 예비 리드베이스층과 예비 납땜가능 리드층의 일부를 제거하는 공정 이후의 포토레지스트 제거 공정에서 1차포토레지스트 공정에 의한 포토레지스트(18)의 일부를 남겨둠으로써 별도의 공정을 수행하지 않고 간단히 형성될 수 있다. On the other hand, Fig. 4 shows another applied structure of the wafer level chip size package according to the present invention. This applied package further has a buffer layer 22 which is filled between the surface of the semiconductor chip 11 and the lid 14 as shown in the drawing to support the back side of the lid 14. The buffer layer 22 leaves part of the photoresist 18 by the primary photoresist process in the photoresist removal step after the steps of removing the preliminary lead base layer and the part of the preliminary solderable lead layer described above. It can be simply formed without performing a separate process.
이같은 버퍼층(22)을 통해 리드(14)의 이면부를 변형되지 않게 안정적으로 받쳐줄 수 있게 되므로 유통중 그 리드(14)의 변형을 방지하여 그 변형으로 인한 실장시의 접속불량 문제의 발생률을 낮출 수 있다. 바람직하게는 유통중 또는 실장시의 취급중 가해질 수 있는 충격에 의해 리드(14)의 기계적인 진동을 완충시킬 수 있도록 그 버퍼층(22)을 신축성있는 재질, 예를 들면 엘라스토머(elastomer) 용도의 포토레지스트를 적용할 수 있다.Since the buffer layer 22 can stably support the back surface of the lead 14 without being deformed, the deformation of the lead 14 can be prevented during distribution, thereby reducing the incidence of connection failure problems during mounting due to the deformation. have. Preferably, the buffer layer 22 is made of a flexible material, for example, an elastomer, so as to buffer the mechanical vibration of the lid 14 by an impact which may be applied during distribution or during handling during mounting. The resist can be applied.
도면으로 일일이 예시하지는 않았지만, 본 발명에 따른 웨이퍼 수준 칩크기 반도체 패키지는, 그 실시에 있어서 상기에 설명되고 도면에 예시된 것 외의 또다른 형태로 변형 또는 응용가능할 것이며, 또한 그러한 변형 및 응용가능한 형태를 위한 부가적인 또는 유사한 공정들을 배제하지 않는다.Although not illustrated in the drawings, the wafer-level chip size semiconductor package according to the present invention may, in its implementation, be modified or applicable to other forms than those described above and illustrated in the drawings, and also such variations and applicable forms. It does not exclude additional or similar processes for
이상에 설명된 바와 같은 웨이퍼 상에서 직접 패키지 요소를 형성하는 본 발명에 의하면, 기존 패키지 제조과정에서 필수적이었던 와이어 본딩을 웨이퍼의 박막성장 기법과 유사한 간단한 스퍼터링 공정으로 행할 수 있고, 또한 별도의 금형에서 행하였던 몰딩 역시 간단한 코팅 공정으로 행할 수 있다. 따라서 기존의 와이어 본딩과 몰딩 공정을 배제할 수 있게 되고 이에 따라 고가의 장비를 구비하지 않아도 되므로 훨씬 경제적이고 능률적으로 패키지를 제조할 수 있게 될 것이다. 뿐만 아니라 여러 가지 칩 크기와 외형이 달라진 경우에도 별도의 작업이나 장비를 필요로 하지 않는다. 또한 본 발명에 따르면, 패키지 제조시에 외부회로의 접속환경을 미리 감안하여 본딩패드 어레이를 재배치하고, 리드의 높이와 면적 등을 최적의 상태로 형성할 수 있어, 나중에 취급이 용이해 짐은 물론, 그 잘 조절된 리드의 높이와 면적 등에 의하여 외부회로와의 접속상태에 신뢰성을 확보할 수 있게 된다.According to the present invention for forming a package element directly on the wafer as described above, the wire bonding, which is essential in the conventional package manufacturing process, can be performed by a simple sputtering process similar to the thin film growth technique of the wafer, and also in a separate mold. Molding can also be done by a simple coating process. Therefore, it is possible to eliminate the existing wire bonding and molding process, thereby eliminating the need for expensive equipment, and thus will be able to manufacture the package much more economically and efficiently. In addition, different chip sizes and appearances do not require extra work or equipment. In addition, according to the present invention, the bonding pad array can be rearranged in advance in consideration of the connection environment of the external circuit at the time of manufacture of the package, and the height and area of the lid can be optimally formed, thereby facilitating the handling later. In addition, it is possible to ensure reliability in the connection state with the external circuit by the height and area of the well-adjusted lead.
따라서 본 발명은 리드가 돌출된 형태의 칩크기 반도체 패키지의 생산성 향상과 함께 높은 신뢰도를 보유한 품질 향상에 기여할 수 있다.Therefore, the present invention can contribute to the improvement of the productivity of the chip-sized semiconductor package of the protruding form with the high reliability.
또한, 본 발명은 리드 돌출 타입의 칩크기 반도체 패키지를 제공하여 회로기판 등에의 표면실장이 용이하게 하는 한편, 패키지 요소들을 웨이퍼 상에서 직접 형성하는 것을 통해 더욱 작아진 실질적인 칩크기(real chip size)의 반도체 패키지를 제공하므로, 각종 회로기판상의 실장밀도나 각종 집적회로의 집적도를 높이는 데에도 기여할 것이다.In addition, the present invention provides a chip-sized semiconductor package of the protruding lead type to facilitate surface mounting on a circuit board or the like, while reducing the actual chip size by using package elements directly formed on the wafer. Since the semiconductor package is provided, it will also contribute to increasing the mounting density on various circuit boards and the degree of integration of various integrated circuits.
도 1은 종래의 BLP형 칩크기 반도체 패키지 구조를 보인 단면도.1 is a cross-sectional view showing a conventional BLP chip size semiconductor package structure.
도 2는 본 발명에 따른 웨이퍼수준 칩크기 반도체 패키지의 외관을 보인 사시도.Figure 2 is a perspective view showing the appearance of a wafer-level chip size semiconductor package according to the present invention.
도 3a 내지 3j는 본 발명에 따른 웨이퍼수준 칩크기 반도체 패키지의 제조공정을 차례로 보인 각 공정에 의해 제조된 패키지의 단면도.3A to 3J are cross-sectional views of packages manufactured by each step in turn showing the manufacturing process of the wafer level chip size semiconductor package according to the present invention.
도 4는 본 발명에 따른 웨이퍼수준 칩크기 반도체 패키지의 다른 예를 보인 단면도.Figure 4 is a cross-sectional view showing another example of a wafer-level chip size semiconductor package according to the present invention.
* 도면의 주요부분에 대한 부호의 설명 * Explanation of symbols on main parts of drawing
11 : 웨이퍼 상태의 반도체 칩 12 : 본딩패드11 semiconductor chip in wafer state 12 bonding pad
13 : 전극 14 : 리드13 electrode 14 lead
14a : 내부접속부 14b : 외부접속부14a: internal connection 14b: external connection
15 : 리드베이스층 16 : 납땜가능 리드층15: lead base layer 16: solderable lead layer
17 : 보호막 17,21 : 포토레지스트17: protective film 17, 21: photoresist
22 : 버퍼층22: buffer layer
Claims (18)
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5598839A (en) * | 1979-01-23 | 1980-07-28 | Nec Corp | Semiconductor device |
| KR960000221A (en) * | 1994-06-15 | 1996-01-25 | 알렌 제이. 스피겔 | Pharmaceutical Compositions Containing CRF Antagonists |
| KR19980033347A (en) * | 1996-10-31 | 1998-07-25 | 가시오가즈오 | Semiconductor device and manufacturing method |
| KR19990065503A (en) * | 1998-01-14 | 1999-08-05 | 구본준 | Chip size package and its manufacturing method |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5598839A (en) * | 1979-01-23 | 1980-07-28 | Nec Corp | Semiconductor device |
| KR960000221A (en) * | 1994-06-15 | 1996-01-25 | 알렌 제이. 스피겔 | Pharmaceutical Compositions Containing CRF Antagonists |
| KR19980033347A (en) * | 1996-10-31 | 1998-07-25 | 가시오가즈오 | Semiconductor device and manufacturing method |
| KR19990065503A (en) * | 1998-01-14 | 1999-08-05 | 구본준 | Chip size package and its manufacturing method |
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| US11876052B2 (en) | 2021-01-06 | 2024-01-16 | SK Hynix Inc. | Semiconductor die bonding structure |
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