KR100502565B1 - Erasing confirmation circuit of flash memory cell - Google Patents

Abstract

According to an exemplary embodiment of the present invention, an erase check operation of a memory cell is repeatedly performed by an erase check mode in which a threshold voltage margin is increased for a memory cell performing an erase check operation according to a normal erase check mode. An erase confirmation circuit of a flash memory cell that can be detected in an erase confirmation mode.

The present invention provides a memory cell connected between a word line and a bit line, a first load transistor connected between a power supply terminal and the bit line, for supplying a power supply voltage supplied from the power supply terminal to the bit line, and the bit line. A normal erase confirmation supplied from the first voltage source according to an erase confirmation signal supplied through an inverter and a sand amplifier for outputting the output voltage through an output terminal after comparing the voltage with a reference voltage and supplied through an inverter. A first switching means for supplying a voltage to the word line, a second voltage source and the word line, and an erase confirmation voltage having an increased threshold voltage margin supplied from the second voltage source according to the erase confirmation signal; Second switching means for supplying a word line and the power supply according to the erase confirmation signal; An erase confirmation circuit of a flash memory cell including a second load transistor for supplying a power supply voltage supplied from the far end to the bit line is provided.

Description

Erasing confirmation circuit of flash memory cell

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an erase confirmation circuit of a flash memory cell. The present invention relates to an erase confirmation voltage in which a threshold voltage margin is increased for a memory cell that performs an erase verify operation according to a normal erase confirmation voltage. An erase confirmation circuit of a flash memory cell for repeatedly performing an erase confirmation operation of a cell is provided.

In general, an erase check operation is performed after an erase operation is performed on the flash memory cell. In the case of an erased cell, even if an erase operation of 100,000 cycles or a read operation is repeatedly performed for a long time (about 10 years), the threshold voltage Vt margin should not be changed.

1 is a block diagram of a general flash memory device, the operation of which is described below.

The command register 10 receives a predetermined bit of data DQ0 to DQN and addresses A0 to AM, respectively, and is operated by a write enable signal WEb. The state and looping control circuit 11 is driven according to the output signal of the command register 11 and the write enable signal WEb. The mode control circuit 9 outputs an output signal for controlling program, erase and read operations in accordance with the output signals of the state and looping control circuit 11. The input / output buffer 8 inputs and outputs data DQ0 to DQN according to the write enable signal WEb and the output enable signal OEb. The latch circuit 6 latches data input from the input / output buffer 8. In the memory cell array 1, a plurality of memory cells are connected in a matrix manner between a plurality of word lines WL0 to WLn and bit lines BL0 to BLn. The row decoder 2 selects the word lines WL0 to WLn of the memory cell array 1 according to the output signal of the mode control circuit 9. The column decoder 4 selects the bit lines BL0 to BLn through the Y-gating 3 circuit connected to the memory cell array 1. The Y-gating circuit 3 supplies the latched data to the latch circuit 6 to the bit line selected by the column decoder 4 according to the output signal of the mode control circuit 9, and also the column The data of the bit line selected by the decoder 4 is output to the input / output buffer 8 through the sand amplifier 5. The comparator 7 outputs a control signal by comparing the data output through the sand amplifier 5 with the data latched in the latch circuit 6. The control signal output from the comparator 7 controls the state and looping control circuit 11 and the mode control circuit 9.

FIG. 2 is a characteristic diagram illustrating a threshold voltage distribution of a flash moricell used in the memory cell array 1 of FIG. 1. The threshold voltage Vt of the flash memory cell is largely classified into four modes. That is, a threshold voltage (VtP: program threshold voltage) after a write operation, a read threshold voltage VtR = 0 for outputting program information of a memory cell, and a read threshold voltage VtR for outputting erase information of the memory cell. = 1) and a threshold voltage (VtE: erase threshold voltage) after an erase operation.

3 is an erase confirmation circuit diagram of a flash memory cell according to the prior art. The memory cell M1 is connected between the word line WL and the bit line BL. The NMOS transistor N1 serving as a load transistor is connected between the bit line BL and the power supply terminal Vcc. Also, the sand amplifier S / A is connected between the bit line BL and the output terminal OUT, and compares the voltage of the bit line BL with a reference voltage Vref and then through the output terminal OUT. Will print.

The conventional flash memory cell erase confirmation circuit supplies different word line WL voltages according to respective confirmation (program check, read and erase check) modes. That is, in the program check mode, a voltage of 5 V is applied to the word line WL to check whether the current I1 flowing through the memory cell M1 is present. At this time, if no current flows through the memory cell M1, the memory cell state is determined to be Pass, otherwise the memory cell M1 is determined to be Fail.

In the case of a read operation, a voltage of 3.5 V is applied to the word line WL to read information of the memory cell M1 through the sand amplifier S / A, and the output terminal OUT of the memory cell is read. Will print the information.

In addition, when the erase check operation is performed after the memory cell M1 is erased, the erase state of the memory cell M1 is confirmed by applying a voltage of 2V to the word line WL. At this time, when the memory cell M1 is in a sufficient erase state, the current I1 flows through the memory cell M1. In addition, during the read operation, a voltage of 3.5V is applied to the word line WL to read information of the memory cell M. At this time, when the memory cell M is sufficiently erased, the current I1 flows more through the memory cell M during the read operation than when the erase operation is confirmed.

However, as shown in FIG. 4, in the case of the abnormal memory cell B whose slope is slower than that of the normal memory cell A, the erase check mode passes normally and the read operation mode fails. It happens. In the case of the abnormal memory cell C of FIG. 4, it is confirmed as a failure in the erase confirmation mode. Therefore, it is possible to replace the normal redundancy cell through the repair operation at the beginning. However, in the case of the abnormal memory cell B of FIG. 3, in the erase check mode, the cell is normally erased. In the read operation mode, the memory cell is stressed and the threshold voltage is changed to identify the abnormally erased cell. As a result, the repair operation for the defective cell is delayed, which results in a decrease in productivity.

Accordingly, the present invention can eliminate the above-described disadvantages by repeatedly performing the erase check operation of the memory cell with the erase check voltage of which the threshold voltage margin is increased for the memory cell performing the erase check operation according to the normal erase check voltage. An object of the present invention is to provide an erase confirmation circuit of a flash memory cell.

An erase confirmation circuit of a flash memory cell according to the present invention for achieving the above object is a memory cell connected between a word line and a bit line, and a power supply terminal and the bit line, and a power supply voltage supplied from the power supply terminal. A first load transistor for supplying the bit line, a sand amplifier for comparing the bit line voltage with a reference voltage, and outputting the same through an output terminal, and a first voltage source and the word line, and are supplied through an inverter A first switching means for supplying a normal erasure confirmation voltage supplied from the first voltage source to the word line according to an erase confirmation signal, and a second voltage source and the word line, wherein the first switching means is connected according to the erase confirmation signal. 2, the erase confirmation voltage having an increased threshold voltage margin supplied from the voltage source is transferred to the word line. According to a second switching means and the check erase signal for supply to a second load transistors for supplying a power supply voltage supplied from the power supply terminal to the bit line characterized in that configured.

Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.

5 is an erase confirmation circuit diagram of a flash memory cell according to the present invention.

The memory cell M11 is connected between the word line WL and the bit line BL. The first NMOS transistor N11, which is the first load transistor, is connected between the power supply terminal Vcc and the bit line BL. The second NMOS transistor N12, which is the second load transistor, is connected between the power supply terminal Vcc and the bit line BL and is driven in accordance with the erase confirmation signal S1. In addition, the third NMOS transistor N13, which is the first switching means, is connected between the first voltage source V1 and the word line WL and is driven in accordance with the erase confirmation signal S1 input through the inverter IN1. The fourth NMOS transistor N14, which is the second switching means, is connected between the second voltage source V2 and the word line WL and is driven in accordance with the erase confirmation signal S1.

Meanwhile, the sand amplifier S / A is connected between the bit line BL and the output terminal OUT. The read terminal OUT is compared with the voltage of the bit line BL with a reference voltage Vref during a read operation. Will output via

Initially, the erasing confirmation signal S1 input from the outside during the normal erasing confirmation operation becomes low. Therefore, the fourth NMOS transistor N14 is turned off and the third NMOS transistor N13 is turned on. Therefore, the word line WL is supplied with the normal erasing confirmation voltage 2V from the first voltage source V1. In addition, the second NMOS transistor N12 that receives the erase confirmation signal S1 is turned off, and the first NMOS transistor N11 is turned on. Therefore, a power supply voltage is supplied to the bit line BL from the power supply terminal Vcc through the first NMOS transistor N11.

In this case, it is assumed that the memory cell M11 is the abnormal cell B of FIG. 3. As shown in FIG. 3, a current pass is formed through the memory cell M11 to the ground terminal Vss. As a result, the current I11 flowing through the memory cell M11 flows at the same 20 GHz margin as that of the normal cell A, so that the memory cell is normally confirmed.

Thereafter, when the erase confirmation signal S1 becomes high, the fourth NMOS transistor N14 is turned on and the third NMOS transistor N13 is turned off. Accordingly, the word line WL is supplied with the erase check voltage 3.5V from which the threshold voltage margin is increased from the second voltage source V2. In addition, both the second NMOS transistor N12 and the first NMOS transistor N11 that receive the erase confirmation signal S1 are turned on. Therefore, a power supply voltage is supplied to the bit line BL from the power supply terminal Vcc through the first and second NMOS transistors N11 and N12.

Similarly, assuming that the memory cell M11 is the abnormal cell B of FIG. 4, a current pass is formed through the memory cell M11 to the ground terminal Vss as shown in FIG. 4. do. In this case, the current margin is 35 mA in the case of the normal cell A, and the current margin flows to 25 mA in the abnormal cell B, and the memory cell is confirmed as defective. As described above, by repeatedly performing the erase check operation with the erase check voltage in which the threshold voltage margin is increased, the defective cell can be detected in the initial erase check mode.

As described above, according to the present invention, the erase check operation of the memory cell is repeatedly performed by the erase check voltage of which the threshold voltage margin is increased for the memory cell that has performed the erase check operation according to the normal erase check voltage. The cells can be detected in the initial erase confirmation mode, which has an excellent effect on improving productivity.

1 is a block diagram of a flash memory device.

2 is a threshold voltage distribution characteristic diagram of a flash memory cell.

3 is an erase confirmation circuit diagram of a flash memory cell according to the prior art.

4 is a word line voltage-current characteristic diagram of a flash memory cell.

5 is an erase confirmation circuit diagram of a flash memory cell according to the present invention;

<Description of the symbols for the main parts of the drawings>

N11 to N14: NMOS transistor IN1: inverter

M11: Memory Cell S / A: Sans Amp

Claims (4)

A memory cell connected between a word line and a bit line; A first load transistor connected between a power supply terminal and the bit line, for supplying a power supply voltage supplied from the power supply terminal to the bit line; A sand amplifier for comparing the bit line voltage with a reference voltage and outputting the same through an output terminal; First switching means connected between a first voltage source and the word line, for supplying a normal erasure confirmation voltage supplied from the first voltage source to the word line according to an erase confirmation signal supplied through an inverter; Second switching means connected between a second voltage source and the word line and configured to supply an erase confirmation voltage with an increased threshold voltage margin supplied from the second voltage source according to the erase confirmation signal to the word line; And a second load transistor configured to supply a power supply voltage supplied from the power supply terminal to the bit line in response to the erasing confirmation signal. The method of claim 1, And the second load transistor comprises an NMOS transistor. The method of claim 1, And the first switching transistor comprises an NMOS transistor. The method of claim 1, And the second switching transistor comprises an NMOS transistor.